1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Bay Trail Crystal Cove PMIC operation region driver
5 * Copyright (C) 2014 Intel Corporation. All rights reserved.
8 #include <linux/acpi.h>
9 #include <linux/init.h>
10 #include <linux/mfd/intel_soc_pmic.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include "intel_pmic.h"
15 #define PWR_SOURCE_SELECT BIT(1)
17 #define PMIC_A0LOCK_REG 0xc5
19 static struct pmic_table power_table[] = {
29 }, /* SYSX -> VSYS_SX */
34 }, /* SYSU -> VSYS_U */
39 }, /* SYSS -> VSYS_S */
44 }, /* V50S -> V5P0S */
49 }, /* HOST -> VHOST, USB2/3 host */
54 }, /* VBUS -> VBUS, USB2/3 OTG */
59 }, /* HDMI -> VHDMI */
69 }, /* X285 -> V2P85SX, camera */
79 }, /* V33S -> V3P3S, display/ssd/audio */
84 }, /* V33U -> V3P3U, SDIO wifi&bt */
86 .address = 0x34 .. 0x40,
89 }, ** V33I, V18A, REFQ, V12A */
94 }, /* V18S -> V1P8S, SOC/USB PHY/SIM */
99 }, /* V18X -> V1P8SX, eMMC/camara/audio */
104 }, /* V18U -> V1P8U, LPDDR */
109 }, /* V12X -> V1P2SX, SOC SFR */
114 }, /* V12S -> V1P2S, MIPI */
124 }, /* V10S -> V1P0S, SOC GFX */
129 }, /* V10X -> V1P0SX, SOC display/DDR IO/PCIe */
134 }, /* V105 -> V1P05S, L2 SRAM */
137 static struct pmic_table thermal_table[] = {
188 static int intel_crc_pmic_get_power(struct regmap *regmap, int reg,
193 if (regmap_read(regmap, reg, &data))
196 *value = (data & PWR_SOURCE_SELECT) && (data & BIT(bit)) ? 1 : 0;
200 static int intel_crc_pmic_update_power(struct regmap *regmap, int reg,
205 if (regmap_read(regmap, reg, &data))
209 data |= PWR_SOURCE_SELECT | BIT(bit);
212 data |= PWR_SOURCE_SELECT;
215 if (regmap_write(regmap, reg, data))
220 static int intel_crc_pmic_get_raw_temp(struct regmap *regmap, int reg)
225 * Raw temperature value is 10bits: 8bits in reg
226 * and 2bits in reg-1: bit0,1
228 if (regmap_read(regmap, reg, &temp_l) ||
229 regmap_read(regmap, reg - 1, &temp_h))
232 return temp_l | (temp_h & 0x3) << 8;
235 static int intel_crc_pmic_update_aux(struct regmap *regmap, int reg, int raw)
237 return regmap_write(regmap, reg, raw) ||
238 regmap_update_bits(regmap, reg - 1, 0x3, raw >> 8) ? -EIO : 0;
241 static int intel_crc_pmic_get_policy(struct regmap *regmap,
242 int reg, int bit, u64 *value)
246 if (regmap_read(regmap, reg, &pen))
252 static int intel_crc_pmic_update_policy(struct regmap *regmap,
253 int reg, int bit, int enable)
257 /* Update to policy enable bit requires unlocking a0lock */
258 if (regmap_read(regmap, PMIC_A0LOCK_REG, &alert0))
261 if (regmap_update_bits(regmap, PMIC_A0LOCK_REG, 0x01, 0))
264 if (regmap_update_bits(regmap, reg, 0x80, enable << 7))
268 if (regmap_write(regmap, PMIC_A0LOCK_REG, alert0))
274 static struct intel_pmic_opregion_data intel_crc_pmic_opregion_data = {
275 .get_power = intel_crc_pmic_get_power,
276 .update_power = intel_crc_pmic_update_power,
277 .get_raw_temp = intel_crc_pmic_get_raw_temp,
278 .update_aux = intel_crc_pmic_update_aux,
279 .get_policy = intel_crc_pmic_get_policy,
280 .update_policy = intel_crc_pmic_update_policy,
281 .power_table = power_table,
282 .power_table_count= ARRAY_SIZE(power_table),
283 .thermal_table = thermal_table,
284 .thermal_table_count = ARRAY_SIZE(thermal_table),
287 static int intel_crc_pmic_opregion_probe(struct platform_device *pdev)
289 struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
290 return intel_pmic_install_opregion_handler(&pdev->dev,
291 ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
292 &intel_crc_pmic_opregion_data);
295 static struct platform_driver intel_crc_pmic_opregion_driver = {
296 .probe = intel_crc_pmic_opregion_probe,
298 .name = "byt_crystal_cove_pmic",
301 builtin_platform_driver(intel_crc_pmic_opregion_driver);