2 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4 * (C) Copyright 2014, 2015 Linaro Ltd.
5 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
12 * CPPC describes a few methods for controlling CPU performance using
13 * information from a per CPU table called CPC. This table is described in
14 * the ACPI v5.0+ specification. The table consists of a list of
15 * registers which may be memory mapped or hardware registers and also may
16 * include some static integer values.
18 * CPU performance is on an abstract continuous scale as against a discretized
19 * P-state scale which is tied to CPU frequency only. In brief, the basic
22 * - OS makes a CPU performance request. (Can provide min and max bounds)
24 * - Platform (such as BMC) is free to optimize request within requested bounds
25 * depending on power/thermal budgets etc.
27 * - Platform conveys its decision back to OS
29 * The communication between OS and platform occurs through another medium
30 * called (PCC) Platform Communication Channel. This is a generic mailbox like
31 * mechanism which includes doorbell semantics to indicate register updates.
32 * See drivers/mailbox/pcc.c for details on PCC.
34 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
35 * above specifications.
38 #define pr_fmt(fmt) "ACPI CPPC: " fmt
40 #include <linux/cpufreq.h>
41 #include <linux/delay.h>
42 #include <linux/ktime.h>
43 #include <linux/rwsem.h>
44 #include <linux/wait.h>
46 #include <acpi/cppc_acpi.h>
48 struct cppc_pcc_data {
49 struct mbox_chan *pcc_channel;
50 void __iomem *pcc_comm_addr;
52 bool pcc_channel_acquired;
54 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
56 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
57 bool platform_owns_pcc; /* Ownership of PCC subspace */
58 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
61 * Lock to provide controlled access to the PCC channel.
63 * For performance critical usecases(currently cppc_set_perf)
64 * We need to take read_lock and check if channel belongs to OSPM
65 * before reading or writing to PCC subspace
66 * We need to take write_lock before transferring the channel
67 * ownership to the platform via a Doorbell
68 * This allows us to batch a number of CPPC requests if they happen
69 * to originate in about the same time
71 * For non-performance critical usecases(init)
72 * Take write_lock for all purposes which gives exclusive access
74 struct rw_semaphore pcc_lock;
76 /* Wait queue for CPUs whose requests were batched */
77 wait_queue_head_t pcc_write_wait_q;
80 /* Structure to represent the single PCC channel */
81 static struct cppc_pcc_data pcc_data = {
82 .pcc_subspace_idx = -1,
83 .platform_owns_pcc = true,
87 * The cpc_desc structure contains the ACPI register details
88 * as described in the per CPU _CPC tables. The details
89 * include the type of register (e.g. PCC, System IO, FFH etc.)
90 * and destination addresses which lets us READ/WRITE CPU performance
91 * information using the appropriate I/O methods.
93 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
95 /* pcc mapped address + header size + offset within PCC subspace */
96 #define GET_PCC_VADDR(offs) (pcc_data.pcc_comm_addr + 0x8 + (offs))
98 /* Check if a CPC regsiter is in PCC */
99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
100 (cpc)->cpc_entry.reg.space_id == \
101 ACPI_ADR_SPACE_PLATFORM_COMM)
103 /* Evalutes to True if reg is a NULL register descriptor */
104 #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
105 (reg)->address == 0 && \
106 (reg)->bit_width == 0 && \
107 (reg)->bit_offset == 0 && \
108 (reg)->access_width == 0)
110 /* Evalutes to True if an optional cpc field is supported */
111 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
112 !!(cpc)->cpc_entry.int_value : \
113 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
115 * Arbitrary Retries in case the remote processor is slow to respond
116 * to PCC commands. Keeping it high enough to cover emulators where
117 * the processors run painfully slow.
119 #define NUM_RETRIES 500
122 struct attribute attr;
123 ssize_t (*show)(struct kobject *kobj,
124 struct attribute *attr, char *buf);
125 ssize_t (*store)(struct kobject *kobj,
126 struct attribute *attr, const char *c, ssize_t count);
129 #define define_one_cppc_ro(_name) \
130 static struct cppc_attr _name = \
131 __ATTR(_name, 0444, show_##_name, NULL)
133 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
135 static ssize_t show_feedback_ctrs(struct kobject *kobj,
136 struct attribute *attr, char *buf)
138 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
139 struct cppc_perf_fb_ctrs fb_ctrs = {0};
141 cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
143 return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
144 fb_ctrs.reference, fb_ctrs.delivered);
146 define_one_cppc_ro(feedback_ctrs);
148 static ssize_t show_reference_perf(struct kobject *kobj,
149 struct attribute *attr, char *buf)
151 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
152 struct cppc_perf_fb_ctrs fb_ctrs = {0};
154 cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
156 return scnprintf(buf, PAGE_SIZE, "%llu\n",
157 fb_ctrs.reference_perf);
159 define_one_cppc_ro(reference_perf);
161 static ssize_t show_wraparound_time(struct kobject *kobj,
162 struct attribute *attr, char *buf)
164 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
165 struct cppc_perf_fb_ctrs fb_ctrs = {0};
167 cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
169 return scnprintf(buf, PAGE_SIZE, "%llu\n", fb_ctrs.ctr_wrap_time);
172 define_one_cppc_ro(wraparound_time);
174 static struct attribute *cppc_attrs[] = {
176 &reference_perf.attr,
177 &wraparound_time.attr,
181 static struct kobj_type cppc_ktype = {
182 .sysfs_ops = &kobj_sysfs_ops,
183 .default_attrs = cppc_attrs,
186 static int check_pcc_chan(bool chk_err_bit)
188 int ret = -EIO, status = 0;
189 struct acpi_pcct_shared_memory __iomem *generic_comm_base = pcc_data.pcc_comm_addr;
190 ktime_t next_deadline = ktime_add(ktime_get(), pcc_data.deadline);
192 if (!pcc_data.platform_owns_pcc)
195 /* Retry in case the remote processor was too slow to catch up. */
196 while (!ktime_after(ktime_get(), next_deadline)) {
198 * Per spec, prior to boot the PCC space wil be initialized by
199 * platform and should have set the command completion bit when
200 * PCC can be used by OSPM
202 status = readw_relaxed(&generic_comm_base->status);
203 if (status & PCC_CMD_COMPLETE_MASK) {
205 if (chk_err_bit && (status & PCC_ERROR_MASK))
210 * Reducing the bus traffic in case this loop takes longer than
217 pcc_data.platform_owns_pcc = false;
219 pr_err("PCC check channel failed. Status=%x\n", status);
225 * This function transfers the ownership of the PCC to the platform
226 * So it must be called while holding write_lock(pcc_lock)
228 static int send_pcc_cmd(u16 cmd)
231 struct acpi_pcct_shared_memory *generic_comm_base =
232 (struct acpi_pcct_shared_memory *) pcc_data.pcc_comm_addr;
233 static ktime_t last_cmd_cmpl_time, last_mpar_reset;
234 static int mpar_count;
235 unsigned int time_delta;
238 * For CMD_WRITE we know for a fact the caller should have checked
239 * the channel before writing to PCC space
241 if (cmd == CMD_READ) {
243 * If there are pending cpc_writes, then we stole the channel
244 * before write completion, so first send a WRITE command to
247 if (pcc_data.pending_pcc_write_cmd)
248 send_pcc_cmd(CMD_WRITE);
250 ret = check_pcc_chan(false);
253 } else /* CMD_WRITE */
254 pcc_data.pending_pcc_write_cmd = FALSE;
257 * Handle the Minimum Request Turnaround Time(MRTT)
258 * "The minimum amount of time that OSPM must wait after the completion
259 * of a command before issuing the next command, in microseconds"
261 if (pcc_data.pcc_mrtt) {
262 time_delta = ktime_us_delta(ktime_get(), last_cmd_cmpl_time);
263 if (pcc_data.pcc_mrtt > time_delta)
264 udelay(pcc_data.pcc_mrtt - time_delta);
268 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
269 * "The maximum number of periodic requests that the subspace channel can
270 * support, reported in commands per minute. 0 indicates no limitation."
272 * This parameter should be ideally zero or large enough so that it can
273 * handle maximum number of requests that all the cores in the system can
274 * collectively generate. If it is not, we will follow the spec and just
275 * not send the request to the platform after hitting the MPAR limit in
278 if (pcc_data.pcc_mpar) {
279 if (mpar_count == 0) {
280 time_delta = ktime_ms_delta(ktime_get(), last_mpar_reset);
281 if (time_delta < 60 * MSEC_PER_SEC) {
282 pr_debug("PCC cmd not sent due to MPAR limit");
286 last_mpar_reset = ktime_get();
287 mpar_count = pcc_data.pcc_mpar;
292 /* Write to the shared comm region. */
293 writew_relaxed(cmd, &generic_comm_base->command);
295 /* Flip CMD COMPLETE bit */
296 writew_relaxed(0, &generic_comm_base->status);
298 pcc_data.platform_owns_pcc = true;
301 ret = mbox_send_message(pcc_data.pcc_channel, &cmd);
303 pr_err("Err sending PCC mbox message. cmd:%d, ret:%d\n",
308 /* wait for completion and check for PCC errro bit */
309 ret = check_pcc_chan(true);
311 if (pcc_data.pcc_mrtt)
312 last_cmd_cmpl_time = ktime_get();
314 if (pcc_data.pcc_channel->mbox->txdone_irq)
315 mbox_chan_txdone(pcc_data.pcc_channel, ret);
317 mbox_client_txdone(pcc_data.pcc_channel, ret);
320 if (cmd == CMD_WRITE) {
322 for_each_possible_cpu(i) {
323 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
327 if (desc->write_cmd_id == pcc_data.pcc_write_cnt)
328 desc->write_cmd_status = ret;
331 pcc_data.pcc_write_cnt++;
332 wake_up_all(&pcc_data.pcc_write_wait_q);
338 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
341 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
344 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
348 struct mbox_client cppc_mbox_cl = {
349 .tx_done = cppc_chan_tx_done,
350 .knows_txdone = true,
353 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
355 int result = -EFAULT;
356 acpi_status status = AE_OK;
357 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
358 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
359 struct acpi_buffer state = {0, NULL};
360 union acpi_object *psd = NULL;
361 struct acpi_psd_package *pdomain;
363 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
364 &buffer, ACPI_TYPE_PACKAGE);
365 if (status == AE_NOT_FOUND) /* _PSD is optional */
367 if (ACPI_FAILURE(status))
370 psd = buffer.pointer;
371 if (!psd || psd->package.count != 1) {
372 pr_debug("Invalid _PSD data\n");
376 pdomain = &(cpc_ptr->domain_info);
378 state.length = sizeof(struct acpi_psd_package);
379 state.pointer = pdomain;
381 status = acpi_extract_package(&(psd->package.elements[0]),
383 if (ACPI_FAILURE(status)) {
384 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
388 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
389 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
393 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
394 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
398 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
399 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
400 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
401 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
407 kfree(buffer.pointer);
412 * acpi_get_psd_map - Map the CPUs in a common freq domain.
413 * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info.
415 * Return: 0 for success or negative value for err.
417 int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data)
422 cpumask_var_t covered_cpus;
423 struct cppc_cpudata *pr, *match_pr;
424 struct acpi_psd_package *pdomain;
425 struct acpi_psd_package *match_pdomain;
426 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
428 if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))
432 * Now that we have _PSD data from all CPUs, lets setup P-state
435 for_each_possible_cpu(i) {
436 pr = all_cpu_data[i];
440 if (cpumask_test_cpu(i, covered_cpus))
443 cpc_ptr = per_cpu(cpc_desc_ptr, i);
449 pdomain = &(cpc_ptr->domain_info);
450 cpumask_set_cpu(i, pr->shared_cpu_map);
451 cpumask_set_cpu(i, covered_cpus);
452 if (pdomain->num_processors <= 1)
455 /* Validate the Domain info */
456 count_target = pdomain->num_processors;
457 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
458 pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
459 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
460 pr->shared_type = CPUFREQ_SHARED_TYPE_HW;
461 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
462 pr->shared_type = CPUFREQ_SHARED_TYPE_ANY;
464 for_each_possible_cpu(j) {
468 match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
469 if (!match_cpc_ptr) {
474 match_pdomain = &(match_cpc_ptr->domain_info);
475 if (match_pdomain->domain != pdomain->domain)
478 /* Here i and j are in the same domain */
479 if (match_pdomain->num_processors != count_target) {
484 if (pdomain->coord_type != match_pdomain->coord_type) {
489 cpumask_set_cpu(j, covered_cpus);
490 cpumask_set_cpu(j, pr->shared_cpu_map);
493 for_each_possible_cpu(j) {
497 match_pr = all_cpu_data[j];
501 match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
502 if (!match_cpc_ptr) {
507 match_pdomain = &(match_cpc_ptr->domain_info);
508 if (match_pdomain->domain != pdomain->domain)
511 match_pr->shared_type = pr->shared_type;
512 cpumask_copy(match_pr->shared_cpu_map,
518 for_each_possible_cpu(i) {
519 pr = all_cpu_data[i];
523 /* Assume no coordination on any error parsing domain info */
525 cpumask_clear(pr->shared_cpu_map);
526 cpumask_set_cpu(i, pr->shared_cpu_map);
527 pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
531 free_cpumask_var(covered_cpus);
534 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
536 static int register_pcc_channel(int pcc_subspace_idx)
538 struct acpi_pcct_hw_reduced *cppc_ss;
541 if (pcc_subspace_idx >= 0) {
542 pcc_data.pcc_channel = pcc_mbox_request_channel(&cppc_mbox_cl,
545 if (IS_ERR(pcc_data.pcc_channel)) {
546 pr_err("Failed to find PCC communication channel\n");
551 * The PCC mailbox controller driver should
552 * have parsed the PCCT (global table of all
553 * PCC channels) and stored pointers to the
554 * subspace communication region in con_priv.
556 cppc_ss = (pcc_data.pcc_channel)->con_priv;
559 pr_err("No PCC subspace found for CPPC\n");
564 * cppc_ss->latency is just a Nominal value. In reality
565 * the remote processor could be much slower to reply.
566 * So add an arbitrary amount of wait on top of Nominal.
568 usecs_lat = NUM_RETRIES * cppc_ss->latency;
569 pcc_data.deadline = ns_to_ktime(usecs_lat * NSEC_PER_USEC);
570 pcc_data.pcc_mrtt = cppc_ss->min_turnaround_time;
571 pcc_data.pcc_mpar = cppc_ss->max_access_rate;
572 pcc_data.pcc_nominal = cppc_ss->latency;
574 pcc_data.pcc_comm_addr = acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
575 if (!pcc_data.pcc_comm_addr) {
576 pr_err("Failed to ioremap PCC comm region mem\n");
580 /* Set flag so that we dont come here for each CPU. */
581 pcc_data.pcc_channel_acquired = true;
588 * cpc_ffh_supported() - check if FFH reading supported
590 * Check if the architecture has support for functional fixed hardware
591 * read/write capability.
593 * Return: true for supported, false for not supported
595 bool __weak cpc_ffh_supported(void)
601 * An example CPC table looks like the following.
603 * Name(_CPC, Package()
609 * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
610 * // Highest Performance
611 * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
612 * // Nominal Performance
613 * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
614 * // Lowest Nonlinear Performance
615 * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
616 * // Lowest Performance
617 * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
618 * // Guaranteed Performance Register
619 * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
620 * // Desired Performance Register
621 * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
627 * Each Register() encodes how to access that specific register.
628 * e.g. a sample PCC entry has the following encoding:
632 * AddressSpaceKeyword
636 * //RegisterBitOffset
640 * //AccessSize (subspace ID)
647 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
648 * @pr: Ptr to acpi_processor containing this CPUs logical Id.
650 * Return: 0 for success or negative value for err.
652 int acpi_cppc_processor_probe(struct acpi_processor *pr)
654 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
655 union acpi_object *out_obj, *cpc_obj;
656 struct cpc_desc *cpc_ptr;
657 struct cpc_reg *gas_t;
658 struct device *cpu_dev;
659 acpi_handle handle = pr->handle;
660 unsigned int num_ent, i, cpc_rev;
664 /* Parse the ACPI _CPC table for this cpu. */
665 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
667 if (ACPI_FAILURE(status)) {
672 out_obj = (union acpi_object *) output.pointer;
674 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
680 /* First entry is NumEntries. */
681 cpc_obj = &out_obj->package.elements[0];
682 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
683 num_ent = cpc_obj->integer.value;
685 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
690 pr_debug("Unexpected entry type(%d) for NumEntries\n",
695 /* Only support CPPCv2. Bail otherwise. */
696 if (num_ent != CPPC_NUM_ENT) {
697 pr_debug("Firmware exports %d entries. Expected: %d\n",
698 num_ent, CPPC_NUM_ENT);
702 cpc_ptr->num_entries = num_ent;
704 /* Second entry should be revision. */
705 cpc_obj = &out_obj->package.elements[1];
706 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
707 cpc_rev = cpc_obj->integer.value;
709 pr_debug("Unexpected entry type(%d) for Revision\n",
714 if (cpc_rev != CPPC_REV) {
715 pr_debug("Firmware exports revision:%d. Expected:%d\n",
720 /* Iterate through remaining entries in _CPC */
721 for (i = 2; i < num_ent; i++) {
722 cpc_obj = &out_obj->package.elements[i];
724 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
725 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
726 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
727 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
728 gas_t = (struct cpc_reg *)
729 cpc_obj->buffer.pointer;
732 * The PCC Subspace index is encoded inside
733 * the CPC table entries. The same PCC index
734 * will be used for all the PCC entries,
735 * so extract it only once.
737 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
738 if (pcc_data.pcc_subspace_idx < 0)
739 pcc_data.pcc_subspace_idx = gas_t->access_width;
740 else if (pcc_data.pcc_subspace_idx != gas_t->access_width) {
741 pr_debug("Mismatched PCC ids.\n");
744 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
745 if (gas_t->address) {
748 addr = ioremap(gas_t->address, gas_t->bit_width/8);
751 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
754 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
755 /* Support only PCC ,SYS MEM and FFH type regs */
756 pr_debug("Unsupported register type: %d\n", gas_t->space_id);
761 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
762 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
764 pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
768 /* Store CPU Logical ID */
769 cpc_ptr->cpu_id = pr->id;
771 /* Parse PSD data for this CPU */
772 ret = acpi_get_psd(cpc_ptr, handle);
776 /* Register PCC channel once for all CPUs. */
777 if (!pcc_data.pcc_channel_acquired) {
778 ret = register_pcc_channel(pcc_data.pcc_subspace_idx);
782 init_rwsem(&pcc_data.pcc_lock);
783 init_waitqueue_head(&pcc_data.pcc_write_wait_q);
786 /* Plug PSD data into this CPUs CPC descriptor. */
787 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
789 /* Everything looks okay */
790 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
792 /* Add per logical CPU nodes for reading its feedback counters. */
793 cpu_dev = get_cpu_device(pr->id);
799 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
802 kobject_put(&cpc_ptr->kobj);
806 kfree(output.pointer);
810 /* Free all the mapped sys mem areas for this CPU */
811 for (i = 2; i < cpc_ptr->num_entries; i++) {
812 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
820 kfree(output.pointer);
823 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
826 * acpi_cppc_processor_exit - Cleanup CPC structs.
827 * @pr: Ptr to acpi_processor containing this CPUs logical Id.
831 void acpi_cppc_processor_exit(struct acpi_processor *pr)
833 struct cpc_desc *cpc_ptr;
837 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
839 /* Free all the mapped sys mem areas for this CPU */
840 for (i = 2; i < cpc_ptr->num_entries; i++) {
841 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
846 kobject_put(&cpc_ptr->kobj);
849 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
852 * cpc_read_ffh() - Read FFH register
853 * @cpunum: cpu number to read
854 * @reg: cppc register information
855 * @val: place holder for return value
857 * Read bit_width bits from a specified address and bit_offset
859 * Return: 0 for success and error code
861 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
867 * cpc_write_ffh() - Write FFH register
868 * @cpunum: cpu number to write
869 * @reg: cppc register information
870 * @val: value to write
872 * Write value of bit_width bits to a specified address and bit_offset
874 * Return: 0 for success and error code
876 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
882 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
883 * as fast as possible. We have already mapped the PCC subspace during init, so
884 * we can directly write to it.
887 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
890 void __iomem *vaddr = 0;
891 struct cpc_reg *reg = ®_res->cpc_entry.reg;
893 if (reg_res->type == ACPI_TYPE_INTEGER) {
894 *val = reg_res->cpc_entry.int_value;
899 if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
900 vaddr = GET_PCC_VADDR(reg->address);
901 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
902 vaddr = reg_res->sys_mem_vaddr;
903 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
904 return cpc_read_ffh(cpu, reg, val);
906 return acpi_os_read_memory((acpi_physical_address)reg->address,
907 val, reg->bit_width);
909 switch (reg->bit_width) {
911 *val = readb_relaxed(vaddr);
914 *val = readw_relaxed(vaddr);
917 *val = readl_relaxed(vaddr);
920 *val = readq_relaxed(vaddr);
923 pr_debug("Error: Cannot read %u bit width from PCC\n",
931 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
934 void __iomem *vaddr = 0;
935 struct cpc_reg *reg = ®_res->cpc_entry.reg;
937 if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
938 vaddr = GET_PCC_VADDR(reg->address);
939 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
940 vaddr = reg_res->sys_mem_vaddr;
941 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
942 return cpc_write_ffh(cpu, reg, val);
944 return acpi_os_write_memory((acpi_physical_address)reg->address,
945 val, reg->bit_width);
947 switch (reg->bit_width) {
949 writeb_relaxed(val, vaddr);
952 writew_relaxed(val, vaddr);
955 writel_relaxed(val, vaddr);
958 writeq_relaxed(val, vaddr);
961 pr_debug("Error: Cannot write %u bit width to PCC\n",
971 * cppc_get_perf_caps - Get a CPUs performance capabilities.
972 * @cpunum: CPU from which to get capabilities info.
973 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
975 * Return: 0 for success with perf_caps populated else -ERRNO.
977 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
979 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
980 struct cpc_register_resource *highest_reg, *lowest_reg, *ref_perf,
983 int ret = 0, regs_in_pcc = 0;
986 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
990 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
991 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
992 ref_perf = &cpc_desc->cpc_regs[REFERENCE_PERF];
993 nom_perf = &cpc_desc->cpc_regs[NOMINAL_PERF];
995 /* Are any of the regs PCC ?*/
996 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
997 CPC_IN_PCC(ref_perf) || CPC_IN_PCC(nom_perf)) {
999 down_write(&pcc_data.pcc_lock);
1000 /* Ring doorbell once to update PCC subspace */
1001 if (send_pcc_cmd(CMD_READ) < 0) {
1007 cpc_read(cpunum, highest_reg, &high);
1008 perf_caps->highest_perf = high;
1010 cpc_read(cpunum, lowest_reg, &low);
1011 perf_caps->lowest_perf = low;
1013 cpc_read(cpunum, nom_perf, &nom);
1014 perf_caps->nominal_perf = nom;
1016 if (!high || !low || !nom)
1021 up_write(&pcc_data.pcc_lock);
1024 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1027 * cppc_get_perf_ctrs - Read a CPUs performance feedback counters.
1028 * @cpunum: CPU from which to read counters.
1029 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1031 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1033 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1035 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1036 struct cpc_register_resource *delivered_reg, *reference_reg,
1037 *ref_perf_reg, *ctr_wrap_reg;
1038 u64 delivered, reference, ref_perf, ctr_wrap_time;
1039 int ret = 0, regs_in_pcc = 0;
1042 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1046 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1047 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1048 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1049 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1052 * If refernce perf register is not supported then we should
1053 * use the nominal perf value
1055 if (!CPC_SUPPORTED(ref_perf_reg))
1056 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1058 /* Are any of the regs PCC ?*/
1059 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1060 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1061 down_write(&pcc_data.pcc_lock);
1063 /* Ring doorbell once to update PCC subspace */
1064 if (send_pcc_cmd(CMD_READ) < 0) {
1070 cpc_read(cpunum, delivered_reg, &delivered);
1071 cpc_read(cpunum, reference_reg, &reference);
1072 cpc_read(cpunum, ref_perf_reg, &ref_perf);
1075 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1076 * performance counters are assumed to never wrap during the lifetime of
1079 ctr_wrap_time = (u64)(~((u64)0));
1080 if (CPC_SUPPORTED(ctr_wrap_reg))
1081 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1083 if (!delivered || !reference || !ref_perf) {
1088 perf_fb_ctrs->delivered = delivered;
1089 perf_fb_ctrs->reference = reference;
1090 perf_fb_ctrs->reference_perf = ref_perf;
1091 perf_fb_ctrs->ctr_wrap_time = ctr_wrap_time;
1094 up_write(&pcc_data.pcc_lock);
1097 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1100 * cppc_set_perf - Set a CPUs performance controls.
1101 * @cpu: CPU for which to set performance controls.
1102 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1104 * Return: 0 for success, -ERRNO otherwise.
1106 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1108 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1109 struct cpc_register_resource *desired_reg;
1113 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1117 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1120 * This is Phase-I where we want to write to CPC registers
1121 * -> We want all CPUs to be able to execute this phase in parallel
1123 * Since read_lock can be acquired by multiple CPUs simultaneously we
1124 * achieve that goal here
1126 if (CPC_IN_PCC(desired_reg)) {
1127 down_read(&pcc_data.pcc_lock); /* BEGIN Phase-I */
1128 if (pcc_data.platform_owns_pcc) {
1129 ret = check_pcc_chan(false);
1131 up_read(&pcc_data.pcc_lock);
1136 * Update the pending_write to make sure a PCC CMD_READ will not
1137 * arrive and steal the channel during the switch to write lock
1139 pcc_data.pending_pcc_write_cmd = true;
1140 cpc_desc->write_cmd_id = pcc_data.pcc_write_cnt;
1141 cpc_desc->write_cmd_status = 0;
1145 * Skip writing MIN/MAX until Linux knows how to come up with
1148 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1150 if (CPC_IN_PCC(desired_reg))
1151 up_read(&pcc_data.pcc_lock); /* END Phase-I */
1153 * This is Phase-II where we transfer the ownership of PCC to Platform
1155 * Short Summary: Basically if we think of a group of cppc_set_perf
1156 * requests that happened in short overlapping interval. The last CPU to
1157 * come out of Phase-I will enter Phase-II and ring the doorbell.
1159 * We have the following requirements for Phase-II:
1160 * 1. We want to execute Phase-II only when there are no CPUs
1161 * currently executing in Phase-I
1162 * 2. Once we start Phase-II we want to avoid all other CPUs from
1164 * 3. We want only one CPU among all those who went through Phase-I
1167 * If write_trylock fails to get the lock and doesn't transfer the
1168 * PCC ownership to the platform, then one of the following will be TRUE
1169 * 1. There is at-least one CPU in Phase-I which will later execute
1170 * write_trylock, so the CPUs in Phase-I will be responsible for
1171 * executing the Phase-II.
1172 * 2. Some other CPU has beaten this CPU to successfully execute the
1173 * write_trylock and has already acquired the write_lock. We know for a
1174 * fact it(other CPU acquiring the write_lock) couldn't have happened
1175 * before this CPU's Phase-I as we held the read_lock.
1176 * 3. Some other CPU executing pcc CMD_READ has stolen the
1177 * down_write, in which case, send_pcc_cmd will check for pending
1178 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1179 * So this CPU can be certain that its request will be delivered
1180 * So in all cases, this CPU knows that its request will be delivered
1181 * by another CPU and can return
1183 * After getting the down_write we still need to check for
1184 * pending_pcc_write_cmd to take care of the following scenario
1185 * The thread running this code could be scheduled out between
1186 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1187 * could have delivered the request to Platform by triggering the
1188 * doorbell and transferred the ownership of PCC to platform. So this
1189 * avoids triggering an unnecessary doorbell and more importantly before
1190 * triggering the doorbell it makes sure that the PCC channel ownership
1191 * is still with OSPM.
1192 * pending_pcc_write_cmd can also be cleared by a different CPU, if
1193 * there was a pcc CMD_READ waiting on down_write and it steals the lock
1194 * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this
1195 * case during a CMD_READ and if there are pending writes it delivers
1196 * the write command before servicing the read command
1198 if (CPC_IN_PCC(desired_reg)) {
1199 if (down_write_trylock(&pcc_data.pcc_lock)) { /* BEGIN Phase-II */
1200 /* Update only if there are pending write commands */
1201 if (pcc_data.pending_pcc_write_cmd)
1202 send_pcc_cmd(CMD_WRITE);
1203 up_write(&pcc_data.pcc_lock); /* END Phase-II */
1205 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1206 wait_event(pcc_data.pcc_write_wait_q,
1207 cpc_desc->write_cmd_id != pcc_data.pcc_write_cnt);
1209 /* send_pcc_cmd updates the status in case of failure */
1210 ret = cpc_desc->write_cmd_status;
1214 EXPORT_SYMBOL_GPL(cppc_set_perf);
1217 * cppc_get_transition_latency - returns frequency transition latency in ns
1219 * ACPI CPPC does not explicitly specifiy how a platform can specify the
1220 * transition latency for perfromance change requests. The closest we have
1221 * is the timing information from the PCCT tables which provides the info
1222 * on the number and frequency of PCC commands the platform can handle.
1224 unsigned int cppc_get_transition_latency(int cpu_num)
1227 * Expected transition latency is based on the PCCT timing values
1228 * Below are definition from ACPI spec:
1229 * pcc_nominal- Expected latency to process a command, in microseconds
1230 * pcc_mpar - The maximum number of periodic requests that the subspace
1231 * channel can support, reported in commands per minute. 0
1232 * indicates no limitation.
1233 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1234 * completion of a command before issuing the next command,
1237 unsigned int latency_ns = 0;
1238 struct cpc_desc *cpc_desc;
1239 struct cpc_register_resource *desired_reg;
1241 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1243 return CPUFREQ_ETERNAL;
1245 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1246 if (!CPC_IN_PCC(desired_reg))
1247 return CPUFREQ_ETERNAL;
1249 if (pcc_data.pcc_mpar)
1250 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_data.pcc_mpar);
1252 latency_ns = max(latency_ns, pcc_data.pcc_nominal * 1000);
1253 latency_ns = max(latency_ns, pcc_data.pcc_mrtt * 1000);
1257 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);