drivers/acpi/cppc_acpi.c

   1 /*
   2  * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
   3  *
   4  * (C) Copyright 2014, 2015 Linaro Ltd.
   5  * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  *
  12  * CPPC describes a few methods for controlling CPU performance using
  13  * information from a per CPU table called CPC. This table is described in
  14  * the ACPI v5.0+ specification. The table consists of a list of
  15  * registers which may be memory mapped or hardware registers and also may
  16  * include some static integer values.
  17  *
  18  * CPU performance is on an abstract continuous scale as against a discretized
  19  * P-state scale which is tied to CPU frequency only. In brief, the basic
  20  * operation involves:
  21  *
  22  * - OS makes a CPU performance request. (Can provide min and max bounds)
  23  *
  24  * - Platform (such as BMC) is free to optimize request within requested bounds
  25  *   depending on power/thermal budgets etc.
  26  *
  27  * - Platform conveys its decision back to OS
  28  *
  29  * The communication between OS and platform occurs through another medium
  30  * called (PCC) Platform Communication Channel. This is a generic mailbox like
  31  * mechanism which includes doorbell semantics to indicate register updates.
  32  * See drivers/mailbox/pcc.c for details on PCC.
  33  *
  34  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
  35  * above specifications.
  36  */
  37
  38 #define pr_fmt(fmt)     "ACPI CPPC: " fmt
  39
  40 #include <linux/cpufreq.h>
  41 #include <linux/delay.h>
  42 #include <linux/ktime.h>
  43 #include <linux/rwsem.h>
  44 #include <linux/wait.h>
  45
  46 #include <acpi/cppc_acpi.h>
  47
  48 struct cppc_pcc_data {
  49         struct mbox_chan *pcc_channel;
  50         void __iomem *pcc_comm_addr;
  51         int pcc_subspace_idx;
  52         bool pcc_channel_acquired;
  53         ktime_t deadline;
  54         unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
  55
  56         bool pending_pcc_write_cmd;     /* Any pending/batched PCC write cmds? */
  57         bool platform_owns_pcc;         /* Ownership of PCC subspace */
  58         unsigned int pcc_write_cnt;     /* Running count of PCC write commands */
  59
  60         /*
  61          * Lock to provide controlled access to the PCC channel.
  62          *
  63          * For performance critical usecases(currently cppc_set_perf)
  64          *      We need to take read_lock and check if channel belongs to OSPM
  65          * before reading or writing to PCC subspace
  66          *      We need to take write_lock before transferring the channel
  67          * ownership to the platform via a Doorbell
  68          *      This allows us to batch a number of CPPC requests if they happen
  69          * to originate in about the same time
  70          *
  71          * For non-performance critical usecases(init)
  72          *      Take write_lock for all purposes which gives exclusive access
  73          */
  74         struct rw_semaphore pcc_lock;
  75
  76         /* Wait queue for CPUs whose requests were batched */
  77         wait_queue_head_t pcc_write_wait_q;
  78 };
  79
  80 /* Structure to represent the single PCC channel */
  81 static struct cppc_pcc_data pcc_data = {
  82         .pcc_subspace_idx = -1,
  83         .platform_owns_pcc = true,
  84 };
  85
  86 /*
  87  * The cpc_desc structure contains the ACPI register details
  88  * as described in the per CPU _CPC tables. The details
  89  * include the type of register (e.g. PCC, System IO, FFH etc.)
  90  * and destination addresses which lets us READ/WRITE CPU performance
  91  * information using the appropriate I/O methods.
  92  */
  93 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  94
  95 /* pcc mapped address + header size + offset within PCC subspace */
  96 #define GET_PCC_VADDR(offs) (pcc_data.pcc_comm_addr + 0x8 + (offs))
  97
  98 /* Check if a CPC register is in PCC */
  99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&             \
 100                                 (cpc)->cpc_entry.reg.space_id ==        \
 101                                 ACPI_ADR_SPACE_PLATFORM_COMM)
 102
 103 /* Evalutes to True if reg is a NULL register descriptor */
 104 #define IS_NULL_REG(reg) ((reg)->space_id ==  ACPI_ADR_SPACE_SYSTEM_MEMORY && \
 105                                 (reg)->address == 0 &&                  \
 106                                 (reg)->bit_width == 0 &&                \
 107                                 (reg)->bit_offset == 0 &&               \
 108                                 (reg)->access_width == 0)
 109
 110 /* Evalutes to True if an optional cpc field is supported */
 111 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ?          \
 112                                 !!(cpc)->cpc_entry.int_value :          \
 113                                 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
 114 /*
 115  * Arbitrary Retries in case the remote processor is slow to respond
 116  * to PCC commands. Keeping it high enough to cover emulators where
 117  * the processors run painfully slow.
 118  */
 119 #define NUM_RETRIES 500
 120
 121 #define define_one_cppc_ro(_name)               \
 122 static struct kobj_attribute _name =            \
 123 __ATTR(_name, 0444, show_##_name, NULL)
 124
 125 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
 126
 127 #define show_cppc_data(access_fn, struct_name, member_name)             \
 128         static ssize_t show_##member_name(struct kobject *kobj,         \
 129                                 struct kobj_attribute *attr, char *buf) \
 130         {                                                               \
 131                 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);           \
 132                 struct struct_name st_name = {0};                       \
 133                 int ret;                                                \
 134                                                                         \
 135                 ret = access_fn(cpc_ptr->cpu_id, &st_name);             \
 136                 if (ret)                                                \
 137                         return ret;                                     \
 138                                                                         \
 139                 return scnprintf(buf, PAGE_SIZE, "%llu\n",              \
 140                                 (u64)st_name.member_name);              \
 141         }                                                               \
 142         define_one_cppc_ro(member_name)
 143
 144 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
 145 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
 146 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
 147 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
 148 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
 149 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
 150
 151 static ssize_t show_feedback_ctrs(struct kobject *kobj,
 152                 struct kobj_attribute *attr, char *buf)
 153 {
 154         struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
 155         struct cppc_perf_fb_ctrs fb_ctrs = {0};
 156         int ret;
 157
 158         ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
 159         if (ret)
 160                 return ret;
 161
 162         return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
 163                         fb_ctrs.reference, fb_ctrs.delivered);
 164 }
 165 define_one_cppc_ro(feedback_ctrs);
 166
 167 static struct attribute *cppc_attrs[] = {
 168         &feedback_ctrs.attr,
 169         &reference_perf.attr,
 170         &wraparound_time.attr,
 171         &highest_perf.attr,
 172         &lowest_perf.attr,
 173         &lowest_nonlinear_perf.attr,
 174         &nominal_perf.attr,
 175         NULL
 176 };
 177
 178 static struct kobj_type cppc_ktype = {
 179         .sysfs_ops = &kobj_sysfs_ops,
 180         .default_attrs = cppc_attrs,
 181 };
 182
 183 static int check_pcc_chan(bool chk_err_bit)
 184 {
 185         int ret = -EIO, status = 0;
 186         struct acpi_pcct_shared_memory __iomem *generic_comm_base = pcc_data.pcc_comm_addr;
 187         ktime_t next_deadline = ktime_add(ktime_get(), pcc_data.deadline);
 188
 189         if (!pcc_data.platform_owns_pcc)
 190                 return 0;
 191
 192         /* Retry in case the remote processor was too slow to catch up. */
 193         while (!ktime_after(ktime_get(), next_deadline)) {
 194                 /*
 195                  * Per spec, prior to boot the PCC space wil be initialized by
 196                  * platform and should have set the command completion bit when
 197                  * PCC can be used by OSPM
 198                  */
 199                 status = readw_relaxed(&generic_comm_base->status);
 200                 if (status & PCC_CMD_COMPLETE_MASK) {
 201                         ret = 0;
 202                         if (chk_err_bit && (status & PCC_ERROR_MASK))
 203                                 ret = -EIO;
 204                         break;
 205                 }
 206                 /*
 207                  * Reducing the bus traffic in case this loop takes longer than
 208                  * a few retries.
 209                  */
 210                 udelay(3);
 211         }
 212
 213         if (likely(!ret))
 214                 pcc_data.platform_owns_pcc = false;
 215         else
 216                 pr_err("PCC check channel failed. Status=%x\n", status);
 217
 218         return ret;
 219 }
 220
 221 /*
 222  * This function transfers the ownership of the PCC to the platform
 223  * So it must be called while holding write_lock(pcc_lock)
 224  */
 225 static int send_pcc_cmd(u16 cmd)
 226 {
 227         int ret = -EIO, i;
 228         struct acpi_pcct_shared_memory *generic_comm_base =
 229                 (struct acpi_pcct_shared_memory *) pcc_data.pcc_comm_addr;
 230         static ktime_t last_cmd_cmpl_time, last_mpar_reset;
 231         static int mpar_count;
 232         unsigned int time_delta;
 233
 234         /*
 235          * For CMD_WRITE we know for a fact the caller should have checked
 236          * the channel before writing to PCC space
 237          */
 238         if (cmd == CMD_READ) {
 239                 /*
 240                  * If there are pending cpc_writes, then we stole the channel
 241                  * before write completion, so first send a WRITE command to
 242                  * platform
 243                  */
 244                 if (pcc_data.pending_pcc_write_cmd)
 245                         send_pcc_cmd(CMD_WRITE);
 246
 247                 ret = check_pcc_chan(false);
 248                 if (ret)
 249                         goto end;
 250         } else /* CMD_WRITE */
 251                 pcc_data.pending_pcc_write_cmd = FALSE;
 252
 253         /*
 254          * Handle the Minimum Request Turnaround Time(MRTT)
 255          * "The minimum amount of time that OSPM must wait after the completion
 256          * of a command before issuing the next command, in microseconds"
 257          */
 258         if (pcc_data.pcc_mrtt) {
 259                 time_delta = ktime_us_delta(ktime_get(), last_cmd_cmpl_time);
 260                 if (pcc_data.pcc_mrtt > time_delta)
 261                         udelay(pcc_data.pcc_mrtt - time_delta);
 262         }
 263
 264         /*
 265          * Handle the non-zero Maximum Periodic Access Rate(MPAR)
 266          * "The maximum number of periodic requests that the subspace channel can
 267          * support, reported in commands per minute. 0 indicates no limitation."
 268          *
 269          * This parameter should be ideally zero or large enough so that it can
 270          * handle maximum number of requests that all the cores in the system can
 271          * collectively generate. If it is not, we will follow the spec and just
 272          * not send the request to the platform after hitting the MPAR limit in
 273          * any 60s window
 274          */
 275         if (pcc_data.pcc_mpar) {
 276                 if (mpar_count == 0) {
 277                         time_delta = ktime_ms_delta(ktime_get(), last_mpar_reset);
 278                         if (time_delta < 60 * MSEC_PER_SEC) {
 279                                 pr_debug("PCC cmd not sent due to MPAR limit");
 280                                 ret = -EIO;
 281                                 goto end;
 282                         }
 283                         last_mpar_reset = ktime_get();
 284                         mpar_count = pcc_data.pcc_mpar;
 285                 }
 286                 mpar_count--;
 287         }
 288
 289         /* Write to the shared comm region. */
 290         writew_relaxed(cmd, &generic_comm_base->command);
 291
 292         /* Flip CMD COMPLETE bit */
 293         writew_relaxed(0, &generic_comm_base->status);
 294
 295         pcc_data.platform_owns_pcc = true;
 296
 297         /* Ring doorbell */
 298         ret = mbox_send_message(pcc_data.pcc_channel, &cmd);
 299         if (ret < 0) {
 300                 pr_err("Err sending PCC mbox message. cmd:%d, ret:%d\n",
 301                                 cmd, ret);
 302                 goto end;
 303         }
 304
 305         /* wait for completion and check for PCC errro bit */
 306         ret = check_pcc_chan(true);
 307
 308         if (pcc_data.pcc_mrtt)
 309                 last_cmd_cmpl_time = ktime_get();
 310
 311         if (pcc_data.pcc_channel->mbox->txdone_irq)
 312                 mbox_chan_txdone(pcc_data.pcc_channel, ret);
 313         else
 314                 mbox_client_txdone(pcc_data.pcc_channel, ret);
 315
 316 end:
 317         if (cmd == CMD_WRITE) {
 318                 if (unlikely(ret)) {
 319                         for_each_possible_cpu(i) {
 320                                 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
 321                                 if (!desc)
 322                                         continue;
 323
 324                                 if (desc->write_cmd_id == pcc_data.pcc_write_cnt)
 325                                         desc->write_cmd_status = ret;
 326                         }
 327                 }
 328                 pcc_data.pcc_write_cnt++;
 329                 wake_up_all(&pcc_data.pcc_write_wait_q);
 330         }
 331
 332         return ret;
 333 }
 334
 335 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
 336 {
 337         if (ret < 0)
 338                 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
 339                                 *(u16 *)msg, ret);
 340         else
 341                 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
 342                                 *(u16 *)msg, ret);
 343 }
 344
 345 struct mbox_client cppc_mbox_cl = {
 346         .tx_done = cppc_chan_tx_done,
 347         .knows_txdone = true,
 348 };
 349
 350 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
 351 {
 352         int result = -EFAULT;
 353         acpi_status status = AE_OK;
 354         struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
 355         struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
 356         struct acpi_buffer state = {0, NULL};
 357         union acpi_object  *psd = NULL;
 358         struct acpi_psd_package *pdomain;
 359
 360         status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
 361                                             &buffer, ACPI_TYPE_PACKAGE);
 362         if (status == AE_NOT_FOUND)     /* _PSD is optional */
 363                 return 0;
 364         if (ACPI_FAILURE(status))
 365                 return -ENODEV;
 366
 367         psd = buffer.pointer;
 368         if (!psd || psd->package.count != 1) {
 369                 pr_debug("Invalid _PSD data\n");
 370                 goto end;
 371         }
 372
 373         pdomain = &(cpc_ptr->domain_info);
 374
 375         state.length = sizeof(struct acpi_psd_package);
 376         state.pointer = pdomain;
 377
 378         status = acpi_extract_package(&(psd->package.elements[0]),
 379                 &format, &state);
 380         if (ACPI_FAILURE(status)) {
 381                 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
 382                 goto end;
 383         }
 384
 385         if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
 386                 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
 387                 goto end;
 388         }
 389
 390         if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
 391                 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
 392                 goto end;
 393         }
 394
 395         if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
 396             pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
 397             pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
 398                 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
 399                 goto end;
 400         }
 401
 402         result = 0;
 403 end:
 404         kfree(buffer.pointer);
 405         return result;
 406 }
 407
 408 /**
 409  * acpi_get_psd_map - Map the CPUs in a common freq domain.
 410  * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info.
 411  *
 412  *      Return: 0 for success or negative value for err.
 413  */
 414 int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data)
 415 {
 416         int count_target;
 417         int retval = 0;
 418         unsigned int i, j;
 419         cpumask_var_t covered_cpus;
 420         struct cppc_cpudata *pr, *match_pr;
 421         struct acpi_psd_package *pdomain;
 422         struct acpi_psd_package *match_pdomain;
 423         struct cpc_desc *cpc_ptr, *match_cpc_ptr;
 424
 425         if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))
 426                 return -ENOMEM;
 427
 428         /*
 429          * Now that we have _PSD data from all CPUs, lets setup P-state
 430          * domain info.
 431          */
 432         for_each_possible_cpu(i) {
 433                 pr = all_cpu_data[i];
 434                 if (!pr)
 435                         continue;
 436
 437                 if (cpumask_test_cpu(i, covered_cpus))
 438                         continue;
 439
 440                 cpc_ptr = per_cpu(cpc_desc_ptr, i);
 441                 if (!cpc_ptr) {
 442                         retval = -EFAULT;
 443                         goto err_ret;
 444                 }
 445
 446                 pdomain = &(cpc_ptr->domain_info);
 447                 cpumask_set_cpu(i, pr->shared_cpu_map);
 448                 cpumask_set_cpu(i, covered_cpus);
 449                 if (pdomain->num_processors <= 1)
 450                         continue;
 451
 452                 /* Validate the Domain info */
 453                 count_target = pdomain->num_processors;
 454                 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
 455                         pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 456                 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
 457                         pr->shared_type = CPUFREQ_SHARED_TYPE_HW;
 458                 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
 459                         pr->shared_type = CPUFREQ_SHARED_TYPE_ANY;
 460
 461                 for_each_possible_cpu(j) {
 462                         if (i == j)
 463                                 continue;
 464
 465                         match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
 466                         if (!match_cpc_ptr) {
 467                                 retval = -EFAULT;
 468                                 goto err_ret;
 469                         }
 470
 471                         match_pdomain = &(match_cpc_ptr->domain_info);
 472                         if (match_pdomain->domain != pdomain->domain)
 473                                 continue;
 474
 475                         /* Here i and j are in the same domain */
 476                         if (match_pdomain->num_processors != count_target) {
 477                                 retval = -EFAULT;
 478                                 goto err_ret;
 479                         }
 480
 481                         if (pdomain->coord_type != match_pdomain->coord_type) {
 482                                 retval = -EFAULT;
 483                                 goto err_ret;
 484                         }
 485
 486                         cpumask_set_cpu(j, covered_cpus);
 487                         cpumask_set_cpu(j, pr->shared_cpu_map);
 488                 }
 489
 490                 for_each_possible_cpu(j) {
 491                         if (i == j)
 492                                 continue;
 493
 494                         match_pr = all_cpu_data[j];
 495                         if (!match_pr)
 496                                 continue;
 497
 498                         match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
 499                         if (!match_cpc_ptr) {
 500                                 retval = -EFAULT;
 501                                 goto err_ret;
 502                         }
 503
 504                         match_pdomain = &(match_cpc_ptr->domain_info);
 505                         if (match_pdomain->domain != pdomain->domain)
 506                                 continue;
 507
 508                         match_pr->shared_type = pr->shared_type;
 509                         cpumask_copy(match_pr->shared_cpu_map,
 510                                      pr->shared_cpu_map);
 511                 }
 512         }
 513
 514 err_ret:
 515         for_each_possible_cpu(i) {
 516                 pr = all_cpu_data[i];
 517                 if (!pr)
 518                         continue;
 519
 520                 /* Assume no coordination on any error parsing domain info */
 521                 if (retval) {
 522                         cpumask_clear(pr->shared_cpu_map);
 523                         cpumask_set_cpu(i, pr->shared_cpu_map);
 524                         pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 525                 }
 526         }
 527
 528         free_cpumask_var(covered_cpus);
 529         return retval;
 530 }
 531 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
 532
 533 static int register_pcc_channel(int pcc_subspace_idx)
 534 {
 535         struct acpi_pcct_hw_reduced *cppc_ss;
 536         u64 usecs_lat;
 537
 538         if (pcc_subspace_idx >= 0) {
 539                 pcc_data.pcc_channel = pcc_mbox_request_channel(&cppc_mbox_cl,
 540                                 pcc_subspace_idx);
 541
 542                 if (IS_ERR(pcc_data.pcc_channel)) {
 543                         pr_err("Failed to find PCC communication channel\n");
 544                         return -ENODEV;
 545                 }
 546
 547                 /*
 548                  * The PCC mailbox controller driver should
 549                  * have parsed the PCCT (global table of all
 550                  * PCC channels) and stored pointers to the
 551                  * subspace communication region in con_priv.
 552                  */
 553                 cppc_ss = (pcc_data.pcc_channel)->con_priv;
 554
 555                 if (!cppc_ss) {
 556                         pr_err("No PCC subspace found for CPPC\n");
 557                         return -ENODEV;
 558                 }
 559
 560                 /*
 561                  * cppc_ss->latency is just a Nominal value. In reality
 562                  * the remote processor could be much slower to reply.
 563                  * So add an arbitrary amount of wait on top of Nominal.
 564                  */
 565                 usecs_lat = NUM_RETRIES * cppc_ss->latency;
 566                 pcc_data.deadline = ns_to_ktime(usecs_lat * NSEC_PER_USEC);
 567                 pcc_data.pcc_mrtt = cppc_ss->min_turnaround_time;
 568                 pcc_data.pcc_mpar = cppc_ss->max_access_rate;
 569                 pcc_data.pcc_nominal = cppc_ss->latency;
 570
 571                 pcc_data.pcc_comm_addr = acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
 572                 if (!pcc_data.pcc_comm_addr) {
 573                         pr_err("Failed to ioremap PCC comm region mem\n");
 574                         return -ENOMEM;
 575                 }
 576
 577                 /* Set flag so that we dont come here for each CPU. */
 578                 pcc_data.pcc_channel_acquired = true;
 579         }
 580
 581         return 0;
 582 }
 583
 584 /**
 585  * cpc_ffh_supported() - check if FFH reading supported
 586  *
 587  * Check if the architecture has support for functional fixed hardware
 588  * read/write capability.
 589  *
 590  * Return: true for supported, false for not supported
 591  */
 592 bool __weak cpc_ffh_supported(void)
 593 {
 594         return false;
 595 }
 596
 597 /*
 598  * An example CPC table looks like the following.
 599  *
 600  *      Name(_CPC, Package()
 601  *                      {
 602  *                      17,
 603  *                      NumEntries
 604  *                      1,
 605  *                      // Revision
 606  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
 607  *                      // Highest Performance
 608  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
 609  *                      // Nominal Performance
 610  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
 611  *                      // Lowest Nonlinear Performance
 612  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
 613  *                      // Lowest Performance
 614  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
 615  *                      // Guaranteed Performance Register
 616  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
 617  *                      // Desired Performance Register
 618  *                      ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
 619  *                      ..
 620  *                      ..
 621  *                      ..
 622  *
 623  *              }
 624  * Each Register() encodes how to access that specific register.
 625  * e.g. a sample PCC entry has the following encoding:
 626  *
 627  *      Register (
 628  *              PCC,
 629  *              AddressSpaceKeyword
 630  *              8,
 631  *              //RegisterBitWidth
 632  *              8,
 633  *              //RegisterBitOffset
 634  *              0x30,
 635  *              //RegisterAddress
 636  *              9
 637  *              //AccessSize (subspace ID)
 638  *              0
 639  *              )
 640  *      }
 641  */
 642
 643 /**
 644  * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
 645  * @pr: Ptr to acpi_processor containing this CPUs logical Id.
 646  *
 647  *      Return: 0 for success or negative value for err.
 648  */
 649 int acpi_cppc_processor_probe(struct acpi_processor *pr)
 650 {
 651         struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
 652         union acpi_object *out_obj, *cpc_obj;
 653         struct cpc_desc *cpc_ptr;
 654         struct cpc_reg *gas_t;
 655         struct device *cpu_dev;
 656         acpi_handle handle = pr->handle;
 657         unsigned int num_ent, i, cpc_rev;
 658         acpi_status status;
 659         int ret = -EFAULT;
 660
 661         /* Parse the ACPI _CPC table for this cpu. */
 662         status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
 663                         ACPI_TYPE_PACKAGE);
 664         if (ACPI_FAILURE(status)) {
 665                 ret = -ENODEV;
 666                 goto out_buf_free;
 667         }
 668
 669         out_obj = (union acpi_object *) output.pointer;
 670
 671         cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
 672         if (!cpc_ptr) {
 673                 ret = -ENOMEM;
 674                 goto out_buf_free;
 675         }
 676
 677         /* First entry is NumEntries. */
 678         cpc_obj = &out_obj->package.elements[0];
 679         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 680                 num_ent = cpc_obj->integer.value;
 681         } else {
 682                 pr_debug("Unexpected entry type(%d) for NumEntries\n",
 683                                 cpc_obj->type);
 684                 goto out_free;
 685         }
 686
 687         /* Only support CPPCv2. Bail otherwise. */
 688         if (num_ent != CPPC_NUM_ENT) {
 689                 pr_debug("Firmware exports %d entries. Expected: %d\n",
 690                                 num_ent, CPPC_NUM_ENT);
 691                 goto out_free;
 692         }
 693
 694         cpc_ptr->num_entries = num_ent;
 695
 696         /* Second entry should be revision. */
 697         cpc_obj = &out_obj->package.elements[1];
 698         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 699                 cpc_rev = cpc_obj->integer.value;
 700         } else {
 701                 pr_debug("Unexpected entry type(%d) for Revision\n",
 702                                 cpc_obj->type);
 703                 goto out_free;
 704         }
 705
 706         if (cpc_rev != CPPC_REV) {
 707                 pr_debug("Firmware exports revision:%d. Expected:%d\n",
 708                                 cpc_rev, CPPC_REV);
 709                 goto out_free;
 710         }
 711
 712         /* Iterate through remaining entries in _CPC */
 713         for (i = 2; i < num_ent; i++) {
 714                 cpc_obj = &out_obj->package.elements[i];
 715
 716                 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 717                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
 718                         cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
 719                 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
 720                         gas_t = (struct cpc_reg *)
 721                                 cpc_obj->buffer.pointer;
 722
 723                         /*
 724                          * The PCC Subspace index is encoded inside
 725                          * the CPC table entries. The same PCC index
 726                          * will be used for all the PCC entries,
 727                          * so extract it only once.
 728                          */
 729                         if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 730                                 if (pcc_data.pcc_subspace_idx < 0)
 731                                         pcc_data.pcc_subspace_idx = gas_t->access_width;
 732                                 else if (pcc_data.pcc_subspace_idx != gas_t->access_width) {
 733                                         pr_debug("Mismatched PCC ids.\n");
 734                                         goto out_free;
 735                                 }
 736                         } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
 737                                 if (gas_t->address) {
 738                                         void __iomem *addr;
 739
 740                                         addr = ioremap(gas_t->address, gas_t->bit_width/8);
 741                                         if (!addr)
 742                                                 goto out_free;
 743                                         cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
 744                                 }
 745                         } else {
 746                                 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
 747                                         /* Support only PCC ,SYS MEM and FFH type regs */
 748                                         pr_debug("Unsupported register type: %d\n", gas_t->space_id);
 749                                         goto out_free;
 750                                 }
 751                         }
 752
 753                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
 754                         memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
 755                 } else {
 756                         pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
 757                         goto out_free;
 758                 }
 759         }
 760         /* Store CPU Logical ID */
 761         cpc_ptr->cpu_id = pr->id;
 762
 763         /* Parse PSD data for this CPU */
 764         ret = acpi_get_psd(cpc_ptr, handle);
 765         if (ret)
 766                 goto out_free;
 767
 768         /* Register PCC channel once for all CPUs. */
 769         if (!pcc_data.pcc_channel_acquired) {
 770                 ret = register_pcc_channel(pcc_data.pcc_subspace_idx);
 771                 if (ret)
 772                         goto out_free;
 773
 774                 init_rwsem(&pcc_data.pcc_lock);
 775                 init_waitqueue_head(&pcc_data.pcc_write_wait_q);
 776         }
 777
 778         /* Everything looks okay */
 779         pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
 780
 781         /* Add per logical CPU nodes for reading its feedback counters. */
 782         cpu_dev = get_cpu_device(pr->id);
 783         if (!cpu_dev) {
 784                 ret = -EINVAL;
 785                 goto out_free;
 786         }
 787
 788         /* Plug PSD data into this CPUs CPC descriptor. */
 789         per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
 790
 791         ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
 792                         "acpi_cppc");
 793         if (ret) {
 794                 per_cpu(cpc_desc_ptr, pr->id) = NULL;
 795                 kobject_put(&cpc_ptr->kobj);
 796                 goto out_free;
 797         }
 798
 799         kfree(output.pointer);
 800         return 0;
 801
 802 out_free:
 803         /* Free all the mapped sys mem areas for this CPU */
 804         for (i = 2; i < cpc_ptr->num_entries; i++) {
 805                 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 806
 807                 if (addr)
 808                         iounmap(addr);
 809         }
 810         kfree(cpc_ptr);
 811
 812 out_buf_free:
 813         kfree(output.pointer);
 814         return ret;
 815 }
 816 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
 817
 818 /**
 819  * acpi_cppc_processor_exit - Cleanup CPC structs.
 820  * @pr: Ptr to acpi_processor containing this CPUs logical Id.
 821  *
 822  * Return: Void
 823  */
 824 void acpi_cppc_processor_exit(struct acpi_processor *pr)
 825 {
 826         struct cpc_desc *cpc_ptr;
 827         unsigned int i;
 828         void __iomem *addr;
 829
 830         cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
 831         if (!cpc_ptr)
 832                 return;
 833
 834         /* Free all the mapped sys mem areas for this CPU */
 835         for (i = 2; i < cpc_ptr->num_entries; i++) {
 836                 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 837                 if (addr)
 838                         iounmap(addr);
 839         }
 840
 841         kobject_put(&cpc_ptr->kobj);
 842         kfree(cpc_ptr);
 843 }
 844 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
 845
 846 /**
 847  * cpc_read_ffh() - Read FFH register
 848  * @cpunum:     cpu number to read
 849  * @reg:        cppc register information
 850  * @val:        place holder for return value
 851  *
 852  * Read bit_width bits from a specified address and bit_offset
 853  *
 854  * Return: 0 for success and error code
 855  */
 856 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
 857 {
 858         return -ENOTSUPP;
 859 }
 860
 861 /**
 862  * cpc_write_ffh() - Write FFH register
 863  * @cpunum:     cpu number to write
 864  * @reg:        cppc register information
 865  * @val:        value to write
 866  *
 867  * Write value of bit_width bits to a specified address and bit_offset
 868  *
 869  * Return: 0 for success and error code
 870  */
 871 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
 872 {
 873         return -ENOTSUPP;
 874 }
 875
 876 /*
 877  * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
 878  * as fast as possible. We have already mapped the PCC subspace during init, so
 879  * we can directly write to it.
 880  */
 881
 882 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 883 {
 884         int ret_val = 0;
 885         void __iomem *vaddr = 0;
 886         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 887
 888         if (reg_res->type == ACPI_TYPE_INTEGER) {
 889                 *val = reg_res->cpc_entry.int_value;
 890                 return ret_val;
 891         }
 892
 893         *val = 0;
 894         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
 895                 vaddr = GET_PCC_VADDR(reg->address);
 896         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 897                 vaddr = reg_res->sys_mem_vaddr;
 898         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 899                 return cpc_read_ffh(cpu, reg, val);
 900         else
 901                 return acpi_os_read_memory((acpi_physical_address)reg->address,
 902                                 val, reg->bit_width);
 903
 904         switch (reg->bit_width) {
 905                 case 8:
 906                         *val = readb_relaxed(vaddr);
 907                         break;
 908                 case 16:
 909                         *val = readw_relaxed(vaddr);
 910                         break;
 911                 case 32:
 912                         *val = readl_relaxed(vaddr);
 913                         break;
 914                 case 64:
 915                         *val = readq_relaxed(vaddr);
 916                         break;
 917                 default:
 918                         pr_debug("Error: Cannot read %u bit width from PCC\n",
 919                                         reg->bit_width);
 920                         ret_val = -EFAULT;
 921         }
 922
 923         return ret_val;
 924 }
 925
 926 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 927 {
 928         int ret_val = 0;
 929         void __iomem *vaddr = 0;
 930         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 931
 932         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
 933                 vaddr = GET_PCC_VADDR(reg->address);
 934         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 935                 vaddr = reg_res->sys_mem_vaddr;
 936         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 937                 return cpc_write_ffh(cpu, reg, val);
 938         else
 939                 return acpi_os_write_memory((acpi_physical_address)reg->address,
 940                                 val, reg->bit_width);
 941
 942         switch (reg->bit_width) {
 943                 case 8:
 944                         writeb_relaxed(val, vaddr);
 945                         break;
 946                 case 16:
 947                         writew_relaxed(val, vaddr);
 948                         break;
 949                 case 32:
 950                         writel_relaxed(val, vaddr);
 951                         break;
 952                 case 64:
 953                         writeq_relaxed(val, vaddr);
 954                         break;
 955                 default:
 956                         pr_debug("Error: Cannot write %u bit width to PCC\n",
 957                                         reg->bit_width);
 958                         ret_val = -EFAULT;
 959                         break;
 960         }
 961
 962         return ret_val;
 963 }
 964
 965 /**
 966  * cppc_get_perf_caps - Get a CPUs performance capabilities.
 967  * @cpunum: CPU from which to get capabilities info.
 968  * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
 969  *
 970  * Return: 0 for success with perf_caps populated else -ERRNO.
 971  */
 972 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
 973 {
 974         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
 975         struct cpc_register_resource *highest_reg, *lowest_reg,
 976                 *lowest_non_linear_reg, *nominal_reg;
 977         u64 high, low, nom, min_nonlinear;
 978         int ret = 0, regs_in_pcc = 0;
 979
 980         if (!cpc_desc) {
 981                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
 982                 return -ENODEV;
 983         }
 984
 985         highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
 986         lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
 987         lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
 988         nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
 989
 990         /* Are any of the regs PCC ?*/
 991         if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
 992                 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg)) {
 993                 regs_in_pcc = 1;
 994                 down_write(&pcc_data.pcc_lock);
 995                 /* Ring doorbell once to update PCC subspace */
 996                 if (send_pcc_cmd(CMD_READ) < 0) {
 997                         ret = -EIO;
 998                         goto out_err;
 999                 }
1000         }
1001
1002         cpc_read(cpunum, highest_reg, &high);
1003         perf_caps->highest_perf = high;
1004
1005         cpc_read(cpunum, lowest_reg, &low);
1006         perf_caps->lowest_perf = low;
1007
1008         cpc_read(cpunum, nominal_reg, &nom);
1009         perf_caps->nominal_perf = nom;
1010
1011         cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1012         perf_caps->lowest_nonlinear_perf = min_nonlinear;
1013
1014         if (!high || !low || !nom || !min_nonlinear)
1015                 ret = -EFAULT;
1016
1017 out_err:
1018         if (regs_in_pcc)
1019                 up_write(&pcc_data.pcc_lock);
1020         return ret;
1021 }
1022 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1023
1024 /**
1025  * cppc_get_perf_ctrs - Read a CPUs performance feedback counters.
1026  * @cpunum: CPU from which to read counters.
1027  * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1028  *
1029  * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1030  */
1031 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1032 {
1033         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1034         struct cpc_register_resource *delivered_reg, *reference_reg,
1035                 *ref_perf_reg, *ctr_wrap_reg;
1036         u64 delivered, reference, ref_perf, ctr_wrap_time;
1037         int ret = 0, regs_in_pcc = 0;
1038
1039         if (!cpc_desc) {
1040                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1041                 return -ENODEV;
1042         }
1043
1044         delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1045         reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1046         ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1047         ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1048
1049         /*
1050          * If refernce perf register is not supported then we should
1051          * use the nominal perf value
1052          */
1053         if (!CPC_SUPPORTED(ref_perf_reg))
1054                 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1055
1056         /* Are any of the regs PCC ?*/
1057         if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1058                 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1059                 down_write(&pcc_data.pcc_lock);
1060                 regs_in_pcc = 1;
1061                 /* Ring doorbell once to update PCC subspace */
1062                 if (send_pcc_cmd(CMD_READ) < 0) {
1063                         ret = -EIO;
1064                         goto out_err;
1065                 }
1066         }
1067
1068         cpc_read(cpunum, delivered_reg, &delivered);
1069         cpc_read(cpunum, reference_reg, &reference);
1070         cpc_read(cpunum, ref_perf_reg, &ref_perf);
1071
1072         /*
1073          * Per spec, if ctr_wrap_time optional register is unsupported, then the
1074          * performance counters are assumed to never wrap during the lifetime of
1075          * platform
1076          */
1077         ctr_wrap_time = (u64)(~((u64)0));
1078         if (CPC_SUPPORTED(ctr_wrap_reg))
1079                 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1080
1081         if (!delivered || !reference || !ref_perf) {
1082                 ret = -EFAULT;
1083                 goto out_err;
1084         }
1085
1086         perf_fb_ctrs->delivered = delivered;
1087         perf_fb_ctrs->reference = reference;
1088         perf_fb_ctrs->reference_perf = ref_perf;
1089         perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1090 out_err:
1091         if (regs_in_pcc)
1092                 up_write(&pcc_data.pcc_lock);
1093         return ret;
1094 }
1095 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1096
1097 /**
1098  * cppc_set_perf - Set a CPUs performance controls.
1099  * @cpu: CPU for which to set performance controls.
1100  * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1101  *
1102  * Return: 0 for success, -ERRNO otherwise.
1103  */
1104 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1105 {
1106         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1107         struct cpc_register_resource *desired_reg;
1108         int ret = 0;
1109
1110         if (!cpc_desc) {
1111                 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1112                 return -ENODEV;
1113         }
1114
1115         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1116
1117         /*
1118          * This is Phase-I where we want to write to CPC registers
1119          * -> We want all CPUs to be able to execute this phase in parallel
1120          *
1121          * Since read_lock can be acquired by multiple CPUs simultaneously we
1122          * achieve that goal here
1123          */
1124         if (CPC_IN_PCC(desired_reg)) {
1125                 down_read(&pcc_data.pcc_lock);  /* BEGIN Phase-I */
1126                 if (pcc_data.platform_owns_pcc) {
1127                         ret = check_pcc_chan(false);
1128                         if (ret) {
1129                                 up_read(&pcc_data.pcc_lock);
1130                                 return ret;
1131                         }
1132                 }
1133                 /*
1134                  * Update the pending_write to make sure a PCC CMD_READ will not
1135                  * arrive and steal the channel during the switch to write lock
1136                  */
1137                 pcc_data.pending_pcc_write_cmd = true;
1138                 cpc_desc->write_cmd_id = pcc_data.pcc_write_cnt;
1139                 cpc_desc->write_cmd_status = 0;
1140         }
1141
1142         /*
1143          * Skip writing MIN/MAX until Linux knows how to come up with
1144          * useful values.
1145          */
1146         cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1147
1148         if (CPC_IN_PCC(desired_reg))
1149                 up_read(&pcc_data.pcc_lock);    /* END Phase-I */
1150         /*
1151          * This is Phase-II where we transfer the ownership of PCC to Platform
1152          *
1153          * Short Summary: Basically if we think of a group of cppc_set_perf
1154          * requests that happened in short overlapping interval. The last CPU to
1155          * come out of Phase-I will enter Phase-II and ring the doorbell.
1156          *
1157          * We have the following requirements for Phase-II:
1158          *     1. We want to execute Phase-II only when there are no CPUs
1159          * currently executing in Phase-I
1160          *     2. Once we start Phase-II we want to avoid all other CPUs from
1161          * entering Phase-I.
1162          *     3. We want only one CPU among all those who went through Phase-I
1163          * to run phase-II
1164          *
1165          * If write_trylock fails to get the lock and doesn't transfer the
1166          * PCC ownership to the platform, then one of the following will be TRUE
1167          *     1. There is at-least one CPU in Phase-I which will later execute
1168          * write_trylock, so the CPUs in Phase-I will be responsible for
1169          * executing the Phase-II.
1170          *     2. Some other CPU has beaten this CPU to successfully execute the
1171          * write_trylock and has already acquired the write_lock. We know for a
1172          * fact it(other CPU acquiring the write_lock) couldn't have happened
1173          * before this CPU's Phase-I as we held the read_lock.
1174          *     3. Some other CPU executing pcc CMD_READ has stolen the
1175          * down_write, in which case, send_pcc_cmd will check for pending
1176          * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1177          * So this CPU can be certain that its request will be delivered
1178          *    So in all cases, this CPU knows that its request will be delivered
1179          * by another CPU and can return
1180          *
1181          * After getting the down_write we still need to check for
1182          * pending_pcc_write_cmd to take care of the following scenario
1183          *    The thread running this code could be scheduled out between
1184          * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1185          * could have delivered the request to Platform by triggering the
1186          * doorbell and transferred the ownership of PCC to platform. So this
1187          * avoids triggering an unnecessary doorbell and more importantly before
1188          * triggering the doorbell it makes sure that the PCC channel ownership
1189          * is still with OSPM.
1190          *   pending_pcc_write_cmd can also be cleared by a different CPU, if
1191          * there was a pcc CMD_READ waiting on down_write and it steals the lock
1192          * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this
1193          * case during a CMD_READ and if there are pending writes it delivers
1194          * the write command before servicing the read command
1195          */
1196         if (CPC_IN_PCC(desired_reg)) {
1197                 if (down_write_trylock(&pcc_data.pcc_lock)) {   /* BEGIN Phase-II */
1198                         /* Update only if there are pending write commands */
1199                         if (pcc_data.pending_pcc_write_cmd)
1200                                 send_pcc_cmd(CMD_WRITE);
1201                         up_write(&pcc_data.pcc_lock);           /* END Phase-II */
1202                 } else
1203                         /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1204                         wait_event(pcc_data.pcc_write_wait_q,
1205                                 cpc_desc->write_cmd_id != pcc_data.pcc_write_cnt);
1206
1207                 /* send_pcc_cmd updates the status in case of failure */
1208                 ret = cpc_desc->write_cmd_status;
1209         }
1210         return ret;
1211 }
1212 EXPORT_SYMBOL_GPL(cppc_set_perf);
1213
1214 /**
1215  * cppc_get_transition_latency - returns frequency transition latency in ns
1216  *
1217  * ACPI CPPC does not explicitly specifiy how a platform can specify the
1218  * transition latency for perfromance change requests. The closest we have
1219  * is the timing information from the PCCT tables which provides the info
1220  * on the number and frequency of PCC commands the platform can handle.
1221  */
1222 unsigned int cppc_get_transition_latency(int cpu_num)
1223 {
1224         /*
1225          * Expected transition latency is based on the PCCT timing values
1226          * Below are definition from ACPI spec:
1227          * pcc_nominal- Expected latency to process a command, in microseconds
1228          * pcc_mpar   - The maximum number of periodic requests that the subspace
1229          *              channel can support, reported in commands per minute. 0
1230          *              indicates no limitation.
1231          * pcc_mrtt   - The minimum amount of time that OSPM must wait after the
1232          *              completion of a command before issuing the next command,
1233          *              in microseconds.
1234          */
1235         unsigned int latency_ns = 0;
1236         struct cpc_desc *cpc_desc;
1237         struct cpc_register_resource *desired_reg;
1238
1239         cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1240         if (!cpc_desc)
1241                 return CPUFREQ_ETERNAL;
1242
1243         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1244         if (!CPC_IN_PCC(desired_reg))
1245                 return CPUFREQ_ETERNAL;
1246
1247         if (pcc_data.pcc_mpar)
1248                 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_data.pcc_mpar);
1249
1250         latency_ns = max(latency_ns, pcc_data.pcc_nominal * 1000);
1251         latency_ns = max(latency_ns, pcc_data.pcc_mrtt * 1000);
1252
1253         return latency_ns;
1254 }
1255 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);