drivers/acpi/cppc_acpi.c

   1 /*
   2  * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
   3  *
   4  * (C) Copyright 2014, 2015 Linaro Ltd.
   5  * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  *
  12  * CPPC describes a few methods for controlling CPU performance using
  13  * information from a per CPU table called CPC. This table is described in
  14  * the ACPI v5.0+ specification. The table consists of a list of
  15  * registers which may be memory mapped or hardware registers and also may
  16  * include some static integer values.
  17  *
  18  * CPU performance is on an abstract continuous scale as against a discretized
  19  * P-state scale which is tied to CPU frequency only. In brief, the basic
  20  * operation involves:
  21  *
  22  * - OS makes a CPU performance request. (Can provide min and max bounds)
  23  *
  24  * - Platform (such as BMC) is free to optimize request within requested bounds
  25  *   depending on power/thermal budgets etc.
  26  *
  27  * - Platform conveys its decision back to OS
  28  *
  29  * The communication between OS and platform occurs through another medium
  30  * called (PCC) Platform Communication Channel. This is a generic mailbox like
  31  * mechanism which includes doorbell semantics to indicate register updates.
  32  * See drivers/mailbox/pcc.c for details on PCC.
  33  *
  34  * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
  35  * above specifications.
  36  */
  37
  38 #define pr_fmt(fmt)     "ACPI CPPC: " fmt
  39
  40 #include <linux/cpufreq.h>
  41 #include <linux/delay.h>
  42 #include <linux/ktime.h>
  43 #include <linux/rwsem.h>
  44 #include <linux/wait.h>
  45
  46 #include <acpi/cppc_acpi.h>
  47
  48 struct cppc_pcc_data {
  49         struct mbox_chan *pcc_channel;
  50         void __iomem *pcc_comm_addr;
  51         int pcc_subspace_idx;
  52         bool pcc_channel_acquired;
  53         ktime_t deadline;
  54         unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
  55
  56         bool pending_pcc_write_cmd;     /* Any pending/batched PCC write cmds? */
  57         bool platform_owns_pcc;         /* Ownership of PCC subspace */
  58         unsigned int pcc_write_cnt;     /* Running count of PCC write commands */
  59
  60         /*
  61          * Lock to provide controlled access to the PCC channel.
  62          *
  63          * For performance critical usecases(currently cppc_set_perf)
  64          *      We need to take read_lock and check if channel belongs to OSPM
  65          * before reading or writing to PCC subspace
  66          *      We need to take write_lock before transferring the channel
  67          * ownership to the platform via a Doorbell
  68          *      This allows us to batch a number of CPPC requests if they happen
  69          * to originate in about the same time
  70          *
  71          * For non-performance critical usecases(init)
  72          *      Take write_lock for all purposes which gives exclusive access
  73          */
  74         struct rw_semaphore pcc_lock;
  75
  76         /* Wait queue for CPUs whose requests were batched */
  77         wait_queue_head_t pcc_write_wait_q;
  78 };
  79
  80 /* Structure to represent the single PCC channel */
  81 static struct cppc_pcc_data pcc_data = {
  82         .pcc_subspace_idx = -1,
  83         .platform_owns_pcc = true,
  84 };
  85
  86 /*
  87  * The cpc_desc structure contains the ACPI register details
  88  * as described in the per CPU _CPC tables. The details
  89  * include the type of register (e.g. PCC, System IO, FFH etc.)
  90  * and destination addresses which lets us READ/WRITE CPU performance
  91  * information using the appropriate I/O methods.
  92  */
  93 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  94
  95 /* pcc mapped address + header size + offset within PCC subspace */
  96 #define GET_PCC_VADDR(offs) (pcc_data.pcc_comm_addr + 0x8 + (offs))
  97
  98 /* Check if a CPC regsiter is in PCC */
  99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&             \
 100                                 (cpc)->cpc_entry.reg.space_id ==        \
 101                                 ACPI_ADR_SPACE_PLATFORM_COMM)
 102
 103 /* Evalutes to True if reg is a NULL register descriptor */
 104 #define IS_NULL_REG(reg) ((reg)->space_id ==  ACPI_ADR_SPACE_SYSTEM_MEMORY && \
 105                                 (reg)->address == 0 &&                  \
 106                                 (reg)->bit_width == 0 &&                \
 107                                 (reg)->bit_offset == 0 &&               \
 108                                 (reg)->access_width == 0)
 109
 110 /* Evalutes to True if an optional cpc field is supported */
 111 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ?          \
 112                                 !!(cpc)->cpc_entry.int_value :          \
 113                                 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
 114 /*
 115  * Arbitrary Retries in case the remote processor is slow to respond
 116  * to PCC commands. Keeping it high enough to cover emulators where
 117  * the processors run painfully slow.
 118  */
 119 #define NUM_RETRIES 500
 120
 121 struct cppc_attr {
 122         struct attribute attr;
 123         ssize_t (*show)(struct kobject *kobj,
 124                         struct attribute *attr, char *buf);
 125         ssize_t (*store)(struct kobject *kobj,
 126                         struct attribute *attr, const char *c, ssize_t count);
 127 };
 128
 129 #define define_one_cppc_ro(_name)               \
 130 static struct cppc_attr _name =                 \
 131 __ATTR(_name, 0444, show_##_name, NULL)
 132
 133 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
 134
 135 static ssize_t show_feedback_ctrs(struct kobject *kobj,
 136                 struct attribute *attr, char *buf)
 137 {
 138         struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
 139         struct cppc_perf_fb_ctrs fb_ctrs = {0};
 140
 141         cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
 142
 143         return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
 144                         fb_ctrs.reference, fb_ctrs.delivered);
 145 }
 146 define_one_cppc_ro(feedback_ctrs);
 147
 148 static ssize_t show_reference_perf(struct kobject *kobj,
 149                 struct attribute *attr, char *buf)
 150 {
 151         struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
 152         struct cppc_perf_fb_ctrs fb_ctrs = {0};
 153
 154         cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
 155
 156         return scnprintf(buf, PAGE_SIZE, "%llu\n",
 157                         fb_ctrs.reference_perf);
 158 }
 159 define_one_cppc_ro(reference_perf);
 160
 161 static ssize_t show_wraparound_time(struct kobject *kobj,
 162                                 struct attribute *attr, char *buf)
 163 {
 164         struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
 165         struct cppc_perf_fb_ctrs fb_ctrs = {0};
 166
 167         cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
 168
 169         return scnprintf(buf, PAGE_SIZE, "%llu\n", fb_ctrs.ctr_wrap_time);
 170
 171 }
 172 define_one_cppc_ro(wraparound_time);
 173
 174 static struct attribute *cppc_attrs[] = {
 175         &feedback_ctrs.attr,
 176         &reference_perf.attr,
 177         &wraparound_time.attr,
 178         NULL
 179 };
 180
 181 static struct kobj_type cppc_ktype = {
 182         .sysfs_ops = &kobj_sysfs_ops,
 183         .default_attrs = cppc_attrs,
 184 };
 185
 186 static int check_pcc_chan(bool chk_err_bit)
 187 {
 188         int ret = -EIO, status = 0;
 189         struct acpi_pcct_shared_memory __iomem *generic_comm_base = pcc_data.pcc_comm_addr;
 190         ktime_t next_deadline = ktime_add(ktime_get(), pcc_data.deadline);
 191
 192         if (!pcc_data.platform_owns_pcc)
 193                 return 0;
 194
 195         /* Retry in case the remote processor was too slow to catch up. */
 196         while (!ktime_after(ktime_get(), next_deadline)) {
 197                 /*
 198                  * Per spec, prior to boot the PCC space wil be initialized by
 199                  * platform and should have set the command completion bit when
 200                  * PCC can be used by OSPM
 201                  */
 202                 status = readw_relaxed(&generic_comm_base->status);
 203                 if (status & PCC_CMD_COMPLETE_MASK) {
 204                         ret = 0;
 205                         if (chk_err_bit && (status & PCC_ERROR_MASK))
 206                                 ret = -EIO;
 207                         break;
 208                 }
 209                 /*
 210                  * Reducing the bus traffic in case this loop takes longer than
 211                  * a few retries.
 212                  */
 213                 udelay(3);
 214         }
 215
 216         if (likely(!ret))
 217                 pcc_data.platform_owns_pcc = false;
 218         else
 219                 pr_err("PCC check channel failed. Status=%x\n", status);
 220
 221         return ret;
 222 }
 223
 224 /*
 225  * This function transfers the ownership of the PCC to the platform
 226  * So it must be called while holding write_lock(pcc_lock)
 227  */
 228 static int send_pcc_cmd(u16 cmd)
 229 {
 230         int ret = -EIO, i;
 231         struct acpi_pcct_shared_memory *generic_comm_base =
 232                 (struct acpi_pcct_shared_memory *) pcc_data.pcc_comm_addr;
 233         static ktime_t last_cmd_cmpl_time, last_mpar_reset;
 234         static int mpar_count;
 235         unsigned int time_delta;
 236
 237         /*
 238          * For CMD_WRITE we know for a fact the caller should have checked
 239          * the channel before writing to PCC space
 240          */
 241         if (cmd == CMD_READ) {
 242                 /*
 243                  * If there are pending cpc_writes, then we stole the channel
 244                  * before write completion, so first send a WRITE command to
 245                  * platform
 246                  */
 247                 if (pcc_data.pending_pcc_write_cmd)
 248                         send_pcc_cmd(CMD_WRITE);
 249
 250                 ret = check_pcc_chan(false);
 251                 if (ret)
 252                         goto end;
 253         } else /* CMD_WRITE */
 254                 pcc_data.pending_pcc_write_cmd = FALSE;
 255
 256         /*
 257          * Handle the Minimum Request Turnaround Time(MRTT)
 258          * "The minimum amount of time that OSPM must wait after the completion
 259          * of a command before issuing the next command, in microseconds"
 260          */
 261         if (pcc_data.pcc_mrtt) {
 262                 time_delta = ktime_us_delta(ktime_get(), last_cmd_cmpl_time);
 263                 if (pcc_data.pcc_mrtt > time_delta)
 264                         udelay(pcc_data.pcc_mrtt - time_delta);
 265         }
 266
 267         /*
 268          * Handle the non-zero Maximum Periodic Access Rate(MPAR)
 269          * "The maximum number of periodic requests that the subspace channel can
 270          * support, reported in commands per minute. 0 indicates no limitation."
 271          *
 272          * This parameter should be ideally zero or large enough so that it can
 273          * handle maximum number of requests that all the cores in the system can
 274          * collectively generate. If it is not, we will follow the spec and just
 275          * not send the request to the platform after hitting the MPAR limit in
 276          * any 60s window
 277          */
 278         if (pcc_data.pcc_mpar) {
 279                 if (mpar_count == 0) {
 280                         time_delta = ktime_ms_delta(ktime_get(), last_mpar_reset);
 281                         if (time_delta < 60 * MSEC_PER_SEC) {
 282                                 pr_debug("PCC cmd not sent due to MPAR limit");
 283                                 ret = -EIO;
 284                                 goto end;
 285                         }
 286                         last_mpar_reset = ktime_get();
 287                         mpar_count = pcc_data.pcc_mpar;
 288                 }
 289                 mpar_count--;
 290         }
 291
 292         /* Write to the shared comm region. */
 293         writew_relaxed(cmd, &generic_comm_base->command);
 294
 295         /* Flip CMD COMPLETE bit */
 296         writew_relaxed(0, &generic_comm_base->status);
 297
 298         pcc_data.platform_owns_pcc = true;
 299
 300         /* Ring doorbell */
 301         ret = mbox_send_message(pcc_data.pcc_channel, &cmd);
 302         if (ret < 0) {
 303                 pr_err("Err sending PCC mbox message. cmd:%d, ret:%d\n",
 304                                 cmd, ret);
 305                 goto end;
 306         }
 307
 308         /* wait for completion and check for PCC errro bit */
 309         ret = check_pcc_chan(true);
 310
 311         if (pcc_data.pcc_mrtt)
 312                 last_cmd_cmpl_time = ktime_get();
 313
 314         if (pcc_data.pcc_channel->mbox->txdone_irq)
 315                 mbox_chan_txdone(pcc_data.pcc_channel, ret);
 316         else
 317                 mbox_client_txdone(pcc_data.pcc_channel, ret);
 318
 319 end:
 320         if (cmd == CMD_WRITE) {
 321                 if (unlikely(ret)) {
 322                         for_each_possible_cpu(i) {
 323                                 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
 324                                 if (!desc)
 325                                         continue;
 326
 327                                 if (desc->write_cmd_id == pcc_data.pcc_write_cnt)
 328                                         desc->write_cmd_status = ret;
 329                         }
 330                 }
 331                 pcc_data.pcc_write_cnt++;
 332                 wake_up_all(&pcc_data.pcc_write_wait_q);
 333         }
 334
 335         return ret;
 336 }
 337
 338 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
 339 {
 340         if (ret < 0)
 341                 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
 342                                 *(u16 *)msg, ret);
 343         else
 344                 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
 345                                 *(u16 *)msg, ret);
 346 }
 347
 348 struct mbox_client cppc_mbox_cl = {
 349         .tx_done = cppc_chan_tx_done,
 350         .knows_txdone = true,
 351 };
 352
 353 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
 354 {
 355         int result = -EFAULT;
 356         acpi_status status = AE_OK;
 357         struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
 358         struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
 359         struct acpi_buffer state = {0, NULL};
 360         union acpi_object  *psd = NULL;
 361         struct acpi_psd_package *pdomain;
 362
 363         status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
 364                                             &buffer, ACPI_TYPE_PACKAGE);
 365         if (status == AE_NOT_FOUND)     /* _PSD is optional */
 366                 return 0;
 367         if (ACPI_FAILURE(status))
 368                 return -ENODEV;
 369
 370         psd = buffer.pointer;
 371         if (!psd || psd->package.count != 1) {
 372                 pr_debug("Invalid _PSD data\n");
 373                 goto end;
 374         }
 375
 376         pdomain = &(cpc_ptr->domain_info);
 377
 378         state.length = sizeof(struct acpi_psd_package);
 379         state.pointer = pdomain;
 380
 381         status = acpi_extract_package(&(psd->package.elements[0]),
 382                 &format, &state);
 383         if (ACPI_FAILURE(status)) {
 384                 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
 385                 goto end;
 386         }
 387
 388         if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
 389                 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
 390                 goto end;
 391         }
 392
 393         if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
 394                 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
 395                 goto end;
 396         }
 397
 398         if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
 399             pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
 400             pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
 401                 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
 402                 goto end;
 403         }
 404
 405         result = 0;
 406 end:
 407         kfree(buffer.pointer);
 408         return result;
 409 }
 410
 411 /**
 412  * acpi_get_psd_map - Map the CPUs in a common freq domain.
 413  * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info.
 414  *
 415  *      Return: 0 for success or negative value for err.
 416  */
 417 int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data)
 418 {
 419         int count_target;
 420         int retval = 0;
 421         unsigned int i, j;
 422         cpumask_var_t covered_cpus;
 423         struct cppc_cpudata *pr, *match_pr;
 424         struct acpi_psd_package *pdomain;
 425         struct acpi_psd_package *match_pdomain;
 426         struct cpc_desc *cpc_ptr, *match_cpc_ptr;
 427
 428         if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))
 429                 return -ENOMEM;
 430
 431         /*
 432          * Now that we have _PSD data from all CPUs, lets setup P-state
 433          * domain info.
 434          */
 435         for_each_possible_cpu(i) {
 436                 pr = all_cpu_data[i];
 437                 if (!pr)
 438                         continue;
 439
 440                 if (cpumask_test_cpu(i, covered_cpus))
 441                         continue;
 442
 443                 cpc_ptr = per_cpu(cpc_desc_ptr, i);
 444                 if (!cpc_ptr) {
 445                         retval = -EFAULT;
 446                         goto err_ret;
 447                 }
 448
 449                 pdomain = &(cpc_ptr->domain_info);
 450                 cpumask_set_cpu(i, pr->shared_cpu_map);
 451                 cpumask_set_cpu(i, covered_cpus);
 452                 if (pdomain->num_processors <= 1)
 453                         continue;
 454
 455                 /* Validate the Domain info */
 456                 count_target = pdomain->num_processors;
 457                 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
 458                         pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 459                 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
 460                         pr->shared_type = CPUFREQ_SHARED_TYPE_HW;
 461                 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
 462                         pr->shared_type = CPUFREQ_SHARED_TYPE_ANY;
 463
 464                 for_each_possible_cpu(j) {
 465                         if (i == j)
 466                                 continue;
 467
 468                         match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
 469                         if (!match_cpc_ptr) {
 470                                 retval = -EFAULT;
 471                                 goto err_ret;
 472                         }
 473
 474                         match_pdomain = &(match_cpc_ptr->domain_info);
 475                         if (match_pdomain->domain != pdomain->domain)
 476                                 continue;
 477
 478                         /* Here i and j are in the same domain */
 479                         if (match_pdomain->num_processors != count_target) {
 480                                 retval = -EFAULT;
 481                                 goto err_ret;
 482                         }
 483
 484                         if (pdomain->coord_type != match_pdomain->coord_type) {
 485                                 retval = -EFAULT;
 486                                 goto err_ret;
 487                         }
 488
 489                         cpumask_set_cpu(j, covered_cpus);
 490                         cpumask_set_cpu(j, pr->shared_cpu_map);
 491                 }
 492
 493                 for_each_possible_cpu(j) {
 494                         if (i == j)
 495                                 continue;
 496
 497                         match_pr = all_cpu_data[j];
 498                         if (!match_pr)
 499                                 continue;
 500
 501                         match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
 502                         if (!match_cpc_ptr) {
 503                                 retval = -EFAULT;
 504                                 goto err_ret;
 505                         }
 506
 507                         match_pdomain = &(match_cpc_ptr->domain_info);
 508                         if (match_pdomain->domain != pdomain->domain)
 509                                 continue;
 510
 511                         match_pr->shared_type = pr->shared_type;
 512                         cpumask_copy(match_pr->shared_cpu_map,
 513                                      pr->shared_cpu_map);
 514                 }
 515         }
 516
 517 err_ret:
 518         for_each_possible_cpu(i) {
 519                 pr = all_cpu_data[i];
 520                 if (!pr)
 521                         continue;
 522
 523                 /* Assume no coordination on any error parsing domain info */
 524                 if (retval) {
 525                         cpumask_clear(pr->shared_cpu_map);
 526                         cpumask_set_cpu(i, pr->shared_cpu_map);
 527                         pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 528                 }
 529         }
 530
 531         free_cpumask_var(covered_cpus);
 532         return retval;
 533 }
 534 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
 535
 536 static int register_pcc_channel(int pcc_subspace_idx)
 537 {
 538         struct acpi_pcct_hw_reduced *cppc_ss;
 539         u64 usecs_lat;
 540
 541         if (pcc_subspace_idx >= 0) {
 542                 pcc_data.pcc_channel = pcc_mbox_request_channel(&cppc_mbox_cl,
 543                                 pcc_subspace_idx);
 544
 545                 if (IS_ERR(pcc_data.pcc_channel)) {
 546                         pr_err("Failed to find PCC communication channel\n");
 547                         return -ENODEV;
 548                 }
 549
 550                 /*
 551                  * The PCC mailbox controller driver should
 552                  * have parsed the PCCT (global table of all
 553                  * PCC channels) and stored pointers to the
 554                  * subspace communication region in con_priv.
 555                  */
 556                 cppc_ss = (pcc_data.pcc_channel)->con_priv;
 557
 558                 if (!cppc_ss) {
 559                         pr_err("No PCC subspace found for CPPC\n");
 560                         return -ENODEV;
 561                 }
 562
 563                 /*
 564                  * cppc_ss->latency is just a Nominal value. In reality
 565                  * the remote processor could be much slower to reply.
 566                  * So add an arbitrary amount of wait on top of Nominal.
 567                  */
 568                 usecs_lat = NUM_RETRIES * cppc_ss->latency;
 569                 pcc_data.deadline = ns_to_ktime(usecs_lat * NSEC_PER_USEC);
 570                 pcc_data.pcc_mrtt = cppc_ss->min_turnaround_time;
 571                 pcc_data.pcc_mpar = cppc_ss->max_access_rate;
 572                 pcc_data.pcc_nominal = cppc_ss->latency;
 573
 574                 pcc_data.pcc_comm_addr = acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
 575                 if (!pcc_data.pcc_comm_addr) {
 576                         pr_err("Failed to ioremap PCC comm region mem\n");
 577                         return -ENOMEM;
 578                 }
 579
 580                 /* Set flag so that we dont come here for each CPU. */
 581                 pcc_data.pcc_channel_acquired = true;
 582         }
 583
 584         return 0;
 585 }
 586
 587 /**
 588  * cpc_ffh_supported() - check if FFH reading supported
 589  *
 590  * Check if the architecture has support for functional fixed hardware
 591  * read/write capability.
 592  *
 593  * Return: true for supported, false for not supported
 594  */
 595 bool __weak cpc_ffh_supported(void)
 596 {
 597         return false;
 598 }
 599
 600 /*
 601  * An example CPC table looks like the following.
 602  *
 603  *      Name(_CPC, Package()
 604  *                      {
 605  *                      17,
 606  *                      NumEntries
 607  *                      1,
 608  *                      // Revision
 609  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
 610  *                      // Highest Performance
 611  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
 612  *                      // Nominal Performance
 613  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
 614  *                      // Lowest Nonlinear Performance
 615  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
 616  *                      // Lowest Performance
 617  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
 618  *                      // Guaranteed Performance Register
 619  *                      ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
 620  *                      // Desired Performance Register
 621  *                      ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
 622  *                      ..
 623  *                      ..
 624  *                      ..
 625  *
 626  *              }
 627  * Each Register() encodes how to access that specific register.
 628  * e.g. a sample PCC entry has the following encoding:
 629  *
 630  *      Register (
 631  *              PCC,
 632  *              AddressSpaceKeyword
 633  *              8,
 634  *              //RegisterBitWidth
 635  *              8,
 636  *              //RegisterBitOffset
 637  *              0x30,
 638  *              //RegisterAddress
 639  *              9
 640  *              //AccessSize (subspace ID)
 641  *              0
 642  *              )
 643  *      }
 644  */
 645
 646 /**
 647  * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
 648  * @pr: Ptr to acpi_processor containing this CPUs logical Id.
 649  *
 650  *      Return: 0 for success or negative value for err.
 651  */
 652 int acpi_cppc_processor_probe(struct acpi_processor *pr)
 653 {
 654         struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
 655         union acpi_object *out_obj, *cpc_obj;
 656         struct cpc_desc *cpc_ptr;
 657         struct cpc_reg *gas_t;
 658         struct device *cpu_dev;
 659         acpi_handle handle = pr->handle;
 660         unsigned int num_ent, i, cpc_rev;
 661         acpi_status status;
 662         int ret = -EFAULT;
 663
 664         /* Parse the ACPI _CPC table for this cpu. */
 665         status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
 666                         ACPI_TYPE_PACKAGE);
 667         if (ACPI_FAILURE(status)) {
 668                 ret = -ENODEV;
 669                 goto out_buf_free;
 670         }
 671
 672         out_obj = (union acpi_object *) output.pointer;
 673
 674         cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
 675         if (!cpc_ptr) {
 676                 ret = -ENOMEM;
 677                 goto out_buf_free;
 678         }
 679
 680         /* First entry is NumEntries. */
 681         cpc_obj = &out_obj->package.elements[0];
 682         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 683                 num_ent = cpc_obj->integer.value;
 684         } else {
 685                 pr_debug("Unexpected entry type(%d) for NumEntries\n",
 686                                 cpc_obj->type);
 687                 goto out_free;
 688         }
 689
 690         /* Only support CPPCv2. Bail otherwise. */
 691         if (num_ent != CPPC_NUM_ENT) {
 692                 pr_debug("Firmware exports %d entries. Expected: %d\n",
 693                                 num_ent, CPPC_NUM_ENT);
 694                 goto out_free;
 695         }
 696
 697         cpc_ptr->num_entries = num_ent;
 698
 699         /* Second entry should be revision. */
 700         cpc_obj = &out_obj->package.elements[1];
 701         if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 702                 cpc_rev = cpc_obj->integer.value;
 703         } else {
 704                 pr_debug("Unexpected entry type(%d) for Revision\n",
 705                                 cpc_obj->type);
 706                 goto out_free;
 707         }
 708
 709         if (cpc_rev != CPPC_REV) {
 710                 pr_debug("Firmware exports revision:%d. Expected:%d\n",
 711                                 cpc_rev, CPPC_REV);
 712                 goto out_free;
 713         }
 714
 715         /* Iterate through remaining entries in _CPC */
 716         for (i = 2; i < num_ent; i++) {
 717                 cpc_obj = &out_obj->package.elements[i];
 718
 719                 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 720                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
 721                         cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
 722                 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
 723                         gas_t = (struct cpc_reg *)
 724                                 cpc_obj->buffer.pointer;
 725
 726                         /*
 727                          * The PCC Subspace index is encoded inside
 728                          * the CPC table entries. The same PCC index
 729                          * will be used for all the PCC entries,
 730                          * so extract it only once.
 731                          */
 732                         if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 733                                 if (pcc_data.pcc_subspace_idx < 0)
 734                                         pcc_data.pcc_subspace_idx = gas_t->access_width;
 735                                 else if (pcc_data.pcc_subspace_idx != gas_t->access_width) {
 736                                         pr_debug("Mismatched PCC ids.\n");
 737                                         goto out_free;
 738                                 }
 739                         } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
 740                                 if (gas_t->address) {
 741                                         void __iomem *addr;
 742
 743                                         addr = ioremap(gas_t->address, gas_t->bit_width/8);
 744                                         if (!addr)
 745                                                 goto out_free;
 746                                         cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
 747                                 }
 748                         } else {
 749                                 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
 750                                         /* Support only PCC ,SYS MEM and FFH type regs */
 751                                         pr_debug("Unsupported register type: %d\n", gas_t->space_id);
 752                                         goto out_free;
 753                                 }
 754                         }
 755
 756                         cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
 757                         memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
 758                 } else {
 759                         pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
 760                         goto out_free;
 761                 }
 762         }
 763         /* Store CPU Logical ID */
 764         cpc_ptr->cpu_id = pr->id;
 765
 766         /* Parse PSD data for this CPU */
 767         ret = acpi_get_psd(cpc_ptr, handle);
 768         if (ret)
 769                 goto out_free;
 770
 771         /* Register PCC channel once for all CPUs. */
 772         if (!pcc_data.pcc_channel_acquired) {
 773                 ret = register_pcc_channel(pcc_data.pcc_subspace_idx);
 774                 if (ret)
 775                         goto out_free;
 776
 777                 init_rwsem(&pcc_data.pcc_lock);
 778                 init_waitqueue_head(&pcc_data.pcc_write_wait_q);
 779         }
 780
 781         /* Plug PSD data into this CPUs CPC descriptor. */
 782         per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
 783
 784         /* Everything looks okay */
 785         pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
 786
 787         /* Add per logical CPU nodes for reading its feedback counters. */
 788         cpu_dev = get_cpu_device(pr->id);
 789         if (!cpu_dev) {
 790                 ret = -EINVAL;
 791                 goto out_free;
 792         }
 793
 794         ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
 795                         "acpi_cppc");
 796         if (ret) {
 797                 kobject_put(&cpc_ptr->kobj);
 798                 goto out_free;
 799         }
 800
 801         kfree(output.pointer);
 802         return 0;
 803
 804 out_free:
 805         /* Free all the mapped sys mem areas for this CPU */
 806         for (i = 2; i < cpc_ptr->num_entries; i++) {
 807                 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 808
 809                 if (addr)
 810                         iounmap(addr);
 811         }
 812         kfree(cpc_ptr);
 813
 814 out_buf_free:
 815         kfree(output.pointer);
 816         return ret;
 817 }
 818 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
 819
 820 /**
 821  * acpi_cppc_processor_exit - Cleanup CPC structs.
 822  * @pr: Ptr to acpi_processor containing this CPUs logical Id.
 823  *
 824  * Return: Void
 825  */
 826 void acpi_cppc_processor_exit(struct acpi_processor *pr)
 827 {
 828         struct cpc_desc *cpc_ptr;
 829         unsigned int i;
 830         void __iomem *addr;
 831
 832         cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
 833
 834         /* Free all the mapped sys mem areas for this CPU */
 835         for (i = 2; i < cpc_ptr->num_entries; i++) {
 836                 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 837                 if (addr)
 838                         iounmap(addr);
 839         }
 840
 841         kobject_put(&cpc_ptr->kobj);
 842         kfree(cpc_ptr);
 843 }
 844 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
 845
 846 /**
 847  * cpc_read_ffh() - Read FFH register
 848  * @cpunum:     cpu number to read
 849  * @reg:        cppc register information
 850  * @val:        place holder for return value
 851  *
 852  * Read bit_width bits from a specified address and bit_offset
 853  *
 854  * Return: 0 for success and error code
 855  */
 856 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
 857 {
 858         return -ENOTSUPP;
 859 }
 860
 861 /**
 862  * cpc_write_ffh() - Write FFH register
 863  * @cpunum:     cpu number to write
 864  * @reg:        cppc register information
 865  * @val:        value to write
 866  *
 867  * Write value of bit_width bits to a specified address and bit_offset
 868  *
 869  * Return: 0 for success and error code
 870  */
 871 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
 872 {
 873         return -ENOTSUPP;
 874 }
 875
 876 /*
 877  * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
 878  * as fast as possible. We have already mapped the PCC subspace during init, so
 879  * we can directly write to it.
 880  */
 881
 882 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 883 {
 884         int ret_val = 0;
 885         void __iomem *vaddr = 0;
 886         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 887
 888         if (reg_res->type == ACPI_TYPE_INTEGER) {
 889                 *val = reg_res->cpc_entry.int_value;
 890                 return ret_val;
 891         }
 892
 893         *val = 0;
 894         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
 895                 vaddr = GET_PCC_VADDR(reg->address);
 896         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 897                 vaddr = reg_res->sys_mem_vaddr;
 898         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 899                 return cpc_read_ffh(cpu, reg, val);
 900         else
 901                 return acpi_os_read_memory((acpi_physical_address)reg->address,
 902                                 val, reg->bit_width);
 903
 904         switch (reg->bit_width) {
 905                 case 8:
 906                         *val = readb_relaxed(vaddr);
 907                         break;
 908                 case 16:
 909                         *val = readw_relaxed(vaddr);
 910                         break;
 911                 case 32:
 912                         *val = readl_relaxed(vaddr);
 913                         break;
 914                 case 64:
 915                         *val = readq_relaxed(vaddr);
 916                         break;
 917                 default:
 918                         pr_debug("Error: Cannot read %u bit width from PCC\n",
 919                                         reg->bit_width);
 920                         ret_val = -EFAULT;
 921         }
 922
 923         return ret_val;
 924 }
 925
 926 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 927 {
 928         int ret_val = 0;
 929         void __iomem *vaddr = 0;
 930         struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 931
 932         if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
 933                 vaddr = GET_PCC_VADDR(reg->address);
 934         else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 935                 vaddr = reg_res->sys_mem_vaddr;
 936         else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 937                 return cpc_write_ffh(cpu, reg, val);
 938         else
 939                 return acpi_os_write_memory((acpi_physical_address)reg->address,
 940                                 val, reg->bit_width);
 941
 942         switch (reg->bit_width) {
 943                 case 8:
 944                         writeb_relaxed(val, vaddr);
 945                         break;
 946                 case 16:
 947                         writew_relaxed(val, vaddr);
 948                         break;
 949                 case 32:
 950                         writel_relaxed(val, vaddr);
 951                         break;
 952                 case 64:
 953                         writeq_relaxed(val, vaddr);
 954                         break;
 955                 default:
 956                         pr_debug("Error: Cannot write %u bit width to PCC\n",
 957                                         reg->bit_width);
 958                         ret_val = -EFAULT;
 959                         break;
 960         }
 961
 962         return ret_val;
 963 }
 964
 965 /**
 966  * cppc_get_perf_caps - Get a CPUs performance capabilities.
 967  * @cpunum: CPU from which to get capabilities info.
 968  * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
 969  *
 970  * Return: 0 for success with perf_caps populated else -ERRNO.
 971  */
 972 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
 973 {
 974         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
 975         struct cpc_register_resource *highest_reg, *lowest_reg, *ref_perf,
 976                                                                  *nom_perf;
 977         u64 high, low, nom;
 978         int ret = 0, regs_in_pcc = 0;
 979
 980         if (!cpc_desc) {
 981                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
 982                 return -ENODEV;
 983         }
 984
 985         highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
 986         lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
 987         ref_perf = &cpc_desc->cpc_regs[REFERENCE_PERF];
 988         nom_perf = &cpc_desc->cpc_regs[NOMINAL_PERF];
 989
 990         /* Are any of the regs PCC ?*/
 991         if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
 992                 CPC_IN_PCC(ref_perf) || CPC_IN_PCC(nom_perf)) {
 993                 regs_in_pcc = 1;
 994                 down_write(&pcc_data.pcc_lock);
 995                 /* Ring doorbell once to update PCC subspace */
 996                 if (send_pcc_cmd(CMD_READ) < 0) {
 997                         ret = -EIO;
 998                         goto out_err;
 999                 }
1000         }
1001
1002         cpc_read(cpunum, highest_reg, &high);
1003         perf_caps->highest_perf = high;
1004
1005         cpc_read(cpunum, lowest_reg, &low);
1006         perf_caps->lowest_perf = low;
1007
1008         cpc_read(cpunum, nom_perf, &nom);
1009         perf_caps->nominal_perf = nom;
1010
1011         if (!high || !low || !nom)
1012                 ret = -EFAULT;
1013
1014 out_err:
1015         if (regs_in_pcc)
1016                 up_write(&pcc_data.pcc_lock);
1017         return ret;
1018 }
1019 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1020
1021 /**
1022  * cppc_get_perf_ctrs - Read a CPUs performance feedback counters.
1023  * @cpunum: CPU from which to read counters.
1024  * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1025  *
1026  * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1027  */
1028 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1029 {
1030         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1031         struct cpc_register_resource *delivered_reg, *reference_reg,
1032                 *ref_perf_reg, *ctr_wrap_reg;
1033         u64 delivered, reference, ref_perf, ctr_wrap_time;
1034         int ret = 0, regs_in_pcc = 0;
1035
1036         if (!cpc_desc) {
1037                 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1038                 return -ENODEV;
1039         }
1040
1041         delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1042         reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1043         ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1044         ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1045
1046         /*
1047          * If refernce perf register is not supported then we should
1048          * use the nominal perf value
1049          */
1050         if (!CPC_SUPPORTED(ref_perf_reg))
1051                 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1052
1053         /* Are any of the regs PCC ?*/
1054         if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1055                 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1056                 down_write(&pcc_data.pcc_lock);
1057                 regs_in_pcc = 1;
1058                 /* Ring doorbell once to update PCC subspace */
1059                 if (send_pcc_cmd(CMD_READ) < 0) {
1060                         ret = -EIO;
1061                         goto out_err;
1062                 }
1063         }
1064
1065         cpc_read(cpunum, delivered_reg, &delivered);
1066         cpc_read(cpunum, reference_reg, &reference);
1067         cpc_read(cpunum, ref_perf_reg, &ref_perf);
1068
1069         /*
1070          * Per spec, if ctr_wrap_time optional register is unsupported, then the
1071          * performance counters are assumed to never wrap during the lifetime of
1072          * platform
1073          */
1074         ctr_wrap_time = (u64)(~((u64)0));
1075         if (CPC_SUPPORTED(ctr_wrap_reg))
1076                 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1077
1078         if (!delivered || !reference || !ref_perf) {
1079                 ret = -EFAULT;
1080                 goto out_err;
1081         }
1082
1083         perf_fb_ctrs->delivered = delivered;
1084         perf_fb_ctrs->reference = reference;
1085         perf_fb_ctrs->reference_perf = ref_perf;
1086         perf_fb_ctrs->ctr_wrap_time = ctr_wrap_time;
1087 out_err:
1088         if (regs_in_pcc)
1089                 up_write(&pcc_data.pcc_lock);
1090         return ret;
1091 }
1092 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1093
1094 /**
1095  * cppc_set_perf - Set a CPUs performance controls.
1096  * @cpu: CPU for which to set performance controls.
1097  * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1098  *
1099  * Return: 0 for success, -ERRNO otherwise.
1100  */
1101 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1102 {
1103         struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1104         struct cpc_register_resource *desired_reg;
1105         int ret = 0;
1106
1107         if (!cpc_desc) {
1108                 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1109                 return -ENODEV;
1110         }
1111
1112         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1113
1114         /*
1115          * This is Phase-I where we want to write to CPC registers
1116          * -> We want all CPUs to be able to execute this phase in parallel
1117          *
1118          * Since read_lock can be acquired by multiple CPUs simultaneously we
1119          * achieve that goal here
1120          */
1121         if (CPC_IN_PCC(desired_reg)) {
1122                 down_read(&pcc_data.pcc_lock);  /* BEGIN Phase-I */
1123                 if (pcc_data.platform_owns_pcc) {
1124                         ret = check_pcc_chan(false);
1125                         if (ret) {
1126                                 up_read(&pcc_data.pcc_lock);
1127                                 return ret;
1128                         }
1129                 }
1130                 /*
1131                  * Update the pending_write to make sure a PCC CMD_READ will not
1132                  * arrive and steal the channel during the switch to write lock
1133                  */
1134                 pcc_data.pending_pcc_write_cmd = true;
1135                 cpc_desc->write_cmd_id = pcc_data.pcc_write_cnt;
1136                 cpc_desc->write_cmd_status = 0;
1137         }
1138
1139         /*
1140          * Skip writing MIN/MAX until Linux knows how to come up with
1141          * useful values.
1142          */
1143         cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1144
1145         if (CPC_IN_PCC(desired_reg))
1146                 up_read(&pcc_data.pcc_lock);    /* END Phase-I */
1147         /*
1148          * This is Phase-II where we transfer the ownership of PCC to Platform
1149          *
1150          * Short Summary: Basically if we think of a group of cppc_set_perf
1151          * requests that happened in short overlapping interval. The last CPU to
1152          * come out of Phase-I will enter Phase-II and ring the doorbell.
1153          *
1154          * We have the following requirements for Phase-II:
1155          *     1. We want to execute Phase-II only when there are no CPUs
1156          * currently executing in Phase-I
1157          *     2. Once we start Phase-II we want to avoid all other CPUs from
1158          * entering Phase-I.
1159          *     3. We want only one CPU among all those who went through Phase-I
1160          * to run phase-II
1161          *
1162          * If write_trylock fails to get the lock and doesn't transfer the
1163          * PCC ownership to the platform, then one of the following will be TRUE
1164          *     1. There is at-least one CPU in Phase-I which will later execute
1165          * write_trylock, so the CPUs in Phase-I will be responsible for
1166          * executing the Phase-II.
1167          *     2. Some other CPU has beaten this CPU to successfully execute the
1168          * write_trylock and has already acquired the write_lock. We know for a
1169          * fact it(other CPU acquiring the write_lock) couldn't have happened
1170          * before this CPU's Phase-I as we held the read_lock.
1171          *     3. Some other CPU executing pcc CMD_READ has stolen the
1172          * down_write, in which case, send_pcc_cmd will check for pending
1173          * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1174          * So this CPU can be certain that its request will be delivered
1175          *    So in all cases, this CPU knows that its request will be delivered
1176          * by another CPU and can return
1177          *
1178          * After getting the down_write we still need to check for
1179          * pending_pcc_write_cmd to take care of the following scenario
1180          *    The thread running this code could be scheduled out between
1181          * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1182          * could have delivered the request to Platform by triggering the
1183          * doorbell and transferred the ownership of PCC to platform. So this
1184          * avoids triggering an unnecessary doorbell and more importantly before
1185          * triggering the doorbell it makes sure that the PCC channel ownership
1186          * is still with OSPM.
1187          *   pending_pcc_write_cmd can also be cleared by a different CPU, if
1188          * there was a pcc CMD_READ waiting on down_write and it steals the lock
1189          * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this
1190          * case during a CMD_READ and if there are pending writes it delivers
1191          * the write command before servicing the read command
1192          */
1193         if (CPC_IN_PCC(desired_reg)) {
1194                 if (down_write_trylock(&pcc_data.pcc_lock)) {   /* BEGIN Phase-II */
1195                         /* Update only if there are pending write commands */
1196                         if (pcc_data.pending_pcc_write_cmd)
1197                                 send_pcc_cmd(CMD_WRITE);
1198                         up_write(&pcc_data.pcc_lock);           /* END Phase-II */
1199                 } else
1200                         /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1201                         wait_event(pcc_data.pcc_write_wait_q,
1202                                 cpc_desc->write_cmd_id != pcc_data.pcc_write_cnt);
1203
1204                 /* send_pcc_cmd updates the status in case of failure */
1205                 ret = cpc_desc->write_cmd_status;
1206         }
1207         return ret;
1208 }
1209 EXPORT_SYMBOL_GPL(cppc_set_perf);
1210
1211 /**
1212  * cppc_get_transition_latency - returns frequency transition latency in ns
1213  *
1214  * ACPI CPPC does not explicitly specifiy how a platform can specify the
1215  * transition latency for perfromance change requests. The closest we have
1216  * is the timing information from the PCCT tables which provides the info
1217  * on the number and frequency of PCC commands the platform can handle.
1218  */
1219 unsigned int cppc_get_transition_latency(int cpu_num)
1220 {
1221         /*
1222          * Expected transition latency is based on the PCCT timing values
1223          * Below are definition from ACPI spec:
1224          * pcc_nominal- Expected latency to process a command, in microseconds
1225          * pcc_mpar   - The maximum number of periodic requests that the subspace
1226          *              channel can support, reported in commands per minute. 0
1227          *              indicates no limitation.
1228          * pcc_mrtt   - The minimum amount of time that OSPM must wait after the
1229          *              completion of a command before issuing the next command,
1230          *              in microseconds.
1231          */
1232         unsigned int latency_ns = 0;
1233         struct cpc_desc *cpc_desc;
1234         struct cpc_register_resource *desired_reg;
1235
1236         cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1237         if (!cpc_desc)
1238                 return CPUFREQ_ETERNAL;
1239
1240         desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1241         if (!CPC_IN_PCC(desired_reg))
1242                 return CPUFREQ_ETERNAL;
1243
1244         if (pcc_data.pcc_mpar)
1245                 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_data.pcc_mpar);
1246
1247         latency_ns = max(latency_ns, pcc_data.pcc_nominal * 1000);
1248         latency_ns = max(latency_ns, pcc_data.pcc_mrtt * 1000);
1249
1250         return latency_ns;
1251 }
1252 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);