1 // SPDX-License-Identifier: GPL-2.0-only
3 * ACPI support for Intel Lynxpoint LPSS.
5 * Copyright (C) 2013, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
10 #include <linux/acpi.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/dmi.h>
14 #include <linux/err.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/x86/clk-lpss.h>
20 #include <linux/platform_data/x86/pmc_atom.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/pwm.h>
24 #include <linux/pxa2xx_ssp.h>
25 #include <linux/suspend.h>
26 #include <linux/delay.h>
30 #ifdef CONFIG_X86_INTEL_LPSS
32 #include <asm/cpu_device_id.h>
33 #include <asm/intel-family.h>
34 #include <asm/iosf_mbi.h>
36 #define LPSS_ADDR(desc) ((unsigned long)&desc)
38 #define LPSS_CLK_SIZE 0x04
39 #define LPSS_LTR_SIZE 0x18
41 /* Offsets relative to LPSS_PRIVATE_OFFSET */
42 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
43 #define LPSS_RESETS 0x04
44 #define LPSS_RESETS_RESET_FUNC BIT(0)
45 #define LPSS_RESETS_RESET_APB BIT(1)
46 #define LPSS_GENERAL 0x08
47 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
48 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
49 #define LPSS_SW_LTR 0x10
50 #define LPSS_AUTO_LTR 0x14
51 #define LPSS_LTR_SNOOP_REQ BIT(15)
52 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
53 #define LPSS_LTR_SNOOP_LAT_1US 0x800
54 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
55 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
56 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
57 #define LPSS_LTR_MAX_VAL 0x3FF
58 #define LPSS_TX_INT 0x20
59 #define LPSS_TX_INT_MASK BIT(1)
61 #define LPSS_PRV_REG_COUNT 9
64 #define LPSS_CLK BIT(0)
65 #define LPSS_CLK_GATE BIT(1)
66 #define LPSS_CLK_DIVIDER BIT(2)
67 #define LPSS_LTR BIT(3)
68 #define LPSS_SAVE_CTX BIT(4)
70 * For some devices the DSDT AML code for another device turns off the device
71 * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff)
72 * as ctx register values.
73 * Luckily these devices always use the same ctx register values, so we can
74 * work around this by saving the ctx registers once on activation.
76 #define LPSS_SAVE_CTX_ONCE BIT(5)
77 #define LPSS_NO_D3_DELAY BIT(6)
79 struct lpss_private_data;
81 struct lpss_device_desc {
83 const char *clk_con_id;
84 unsigned int prv_offset;
85 size_t prv_size_override;
86 const struct property_entry *properties;
87 void (*setup)(struct lpss_private_data *pdata);
88 bool resume_from_noirq;
91 static const struct lpss_device_desc lpss_dma_desc = {
95 struct lpss_private_data {
96 struct acpi_device *adev;
97 void __iomem *mmio_base;
98 resource_size_t mmio_size;
99 unsigned int fixed_clk_rate;
101 const struct lpss_device_desc *dev_desc;
102 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
105 /* Devices which need to be in D3 before lpss_iosf_enter_d3_state() proceeds */
106 static u32 pmc_atom_d3_mask = 0xfe000ffe;
108 /* LPSS run time quirks */
109 static unsigned int lpss_quirks;
112 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
114 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
115 * it can be powered off automatically whenever the last LPSS device goes down.
116 * In case of no power any access to the DMA controller will hang the system.
117 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
118 * well as on ASuS T100TA transformer.
120 * This quirk overrides power state of entire LPSS island to keep DMA powered
121 * on whenever we have at least one other device in use.
123 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
125 /* UART Component Parameter Register */
126 #define LPSS_UART_CPR 0xF4
127 #define LPSS_UART_CPR_AFCE BIT(4)
129 static void lpss_uart_setup(struct lpss_private_data *pdata)
134 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
135 val = readl(pdata->mmio_base + offset);
136 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
138 val = readl(pdata->mmio_base + LPSS_UART_CPR);
139 if (!(val & LPSS_UART_CPR_AFCE)) {
140 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
141 val = readl(pdata->mmio_base + offset);
142 val |= LPSS_GENERAL_UART_RTS_OVRD;
143 writel(val, pdata->mmio_base + offset);
147 static void lpss_deassert_reset(struct lpss_private_data *pdata)
152 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
153 val = readl(pdata->mmio_base + offset);
154 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
155 writel(val, pdata->mmio_base + offset);
159 * BYT PWM used for backlight control by the i915 driver on systems without
160 * the Crystal Cove PMIC.
162 static struct pwm_lookup byt_pwm_lookup[] = {
163 PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0",
164 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
165 "pwm-lpss-platform"),
168 static void byt_pwm_setup(struct lpss_private_data *pdata)
170 struct acpi_device *adev = pdata->adev;
172 /* Only call pwm_add_table for the first PWM controller */
173 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
176 pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
179 #define LPSS_I2C_ENABLE 0x6c
181 static void byt_i2c_setup(struct lpss_private_data *pdata)
183 const char *uid_str = acpi_device_uid(pdata->adev);
184 acpi_handle handle = pdata->adev->handle;
185 unsigned long long shared_host = 0;
189 /* Expected to always be true, but better safe then sorry */
190 if (uid_str && !kstrtol(uid_str, 10, &uid) && uid) {
191 /* Detect I2C bus shared with PUNIT and ignore its d3 status */
192 status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host);
193 if (ACPI_SUCCESS(status) && shared_host)
194 pmc_atom_d3_mask &= ~(BIT_LPSS2_F1_I2C1 << (uid - 1));
197 lpss_deassert_reset(pdata);
199 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
200 pdata->fixed_clk_rate = 133000000;
202 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
205 /* BSW PWM used for backlight control by the i915 driver */
206 static struct pwm_lookup bsw_pwm_lookup[] = {
207 PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
208 "pwm_soc_backlight", 0, PWM_POLARITY_NORMAL,
209 "pwm-lpss-platform"),
212 static void bsw_pwm_setup(struct lpss_private_data *pdata)
214 struct acpi_device *adev = pdata->adev;
216 /* Only call pwm_add_table for the first PWM controller */
217 if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
220 pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
223 static const struct property_entry lpt_spi_properties[] = {
224 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_LPT_SSP),
228 static const struct lpss_device_desc lpt_spi_dev_desc = {
229 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
232 .properties = lpt_spi_properties,
235 static const struct lpss_device_desc lpt_i2c_dev_desc = {
236 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
240 static struct property_entry uart_properties[] = {
241 PROPERTY_ENTRY_U32("reg-io-width", 4),
242 PROPERTY_ENTRY_U32("reg-shift", 2),
243 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
247 static const struct lpss_device_desc lpt_uart_dev_desc = {
248 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
250 .clk_con_id = "baudclk",
252 .setup = lpss_uart_setup,
253 .properties = uart_properties,
256 static const struct lpss_device_desc lpt_sdio_dev_desc = {
258 .prv_offset = 0x1000,
259 .prv_size_override = 0x1018,
262 static const struct lpss_device_desc byt_pwm_dev_desc = {
263 .flags = LPSS_SAVE_CTX,
265 .setup = byt_pwm_setup,
268 static const struct lpss_device_desc bsw_pwm_dev_desc = {
269 .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY,
271 .setup = bsw_pwm_setup,
272 .resume_from_noirq = true,
275 static const struct lpss_device_desc byt_uart_dev_desc = {
276 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
277 .clk_con_id = "baudclk",
279 .setup = lpss_uart_setup,
280 .properties = uart_properties,
283 static const struct lpss_device_desc bsw_uart_dev_desc = {
284 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
286 .clk_con_id = "baudclk",
288 .setup = lpss_uart_setup,
289 .properties = uart_properties,
292 static const struct property_entry byt_spi_properties[] = {
293 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BYT_SSP),
297 static const struct lpss_device_desc byt_spi_dev_desc = {
298 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
300 .properties = byt_spi_properties,
303 static const struct lpss_device_desc byt_sdio_dev_desc = {
307 static const struct lpss_device_desc byt_i2c_dev_desc = {
308 .flags = LPSS_CLK | LPSS_SAVE_CTX,
310 .setup = byt_i2c_setup,
311 .resume_from_noirq = true,
314 static const struct lpss_device_desc bsw_i2c_dev_desc = {
315 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
317 .setup = byt_i2c_setup,
318 .resume_from_noirq = true,
321 static const struct property_entry bsw_spi_properties[] = {
322 PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BSW_SSP),
326 static const struct lpss_device_desc bsw_spi_dev_desc = {
327 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
330 .setup = lpss_deassert_reset,
331 .properties = bsw_spi_properties,
334 static const struct x86_cpu_id lpss_cpu_ids[] = {
335 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
336 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
342 #define LPSS_ADDR(desc) (0UL)
344 #endif /* CONFIG_X86_INTEL_LPSS */
346 static const struct acpi_device_id acpi_lpss_device_ids[] = {
347 /* Generic LPSS devices */
348 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
350 /* Lynxpoint LPSS devices */
351 { "INT33C0", LPSS_ADDR(lpt_spi_dev_desc) },
352 { "INT33C1", LPSS_ADDR(lpt_spi_dev_desc) },
353 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
354 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
355 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
356 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
357 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
360 /* BayTrail LPSS devices */
361 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
362 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
363 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
364 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
365 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
369 /* Braswell LPSS devices */
370 { "80862286", LPSS_ADDR(lpss_dma_desc) },
371 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
372 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
373 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
374 { "808622C0", LPSS_ADDR(lpss_dma_desc) },
375 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
377 /* Broadwell LPSS devices */
378 { "INT3430", LPSS_ADDR(lpt_spi_dev_desc) },
379 { "INT3431", LPSS_ADDR(lpt_spi_dev_desc) },
380 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
381 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
382 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
383 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
384 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
387 /* Wildcat Point LPSS devices */
388 { "INT3438", LPSS_ADDR(lpt_spi_dev_desc) },
393 #ifdef CONFIG_X86_INTEL_LPSS
395 static int is_memory(struct acpi_resource *res, void *not_used)
399 return !acpi_dev_resource_memory(res, &r);
402 /* LPSS main clock device. */
403 static struct platform_device *lpss_clk_dev;
405 static inline void lpt_register_clock_device(void)
407 lpss_clk_dev = platform_device_register_simple("clk-lpss-atom",
412 static int register_device_clock(struct acpi_device *adev,
413 struct lpss_private_data *pdata)
415 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
416 const char *devname = dev_name(&adev->dev);
418 struct lpss_clk_data *clk_data;
419 const char *parent, *clk_name;
420 void __iomem *prv_base;
423 lpt_register_clock_device();
425 clk_data = platform_get_drvdata(lpss_clk_dev);
430 if (!pdata->mmio_base
431 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
434 parent = clk_data->name;
435 prv_base = pdata->mmio_base + dev_desc->prv_offset;
437 if (pdata->fixed_clk_rate) {
438 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
439 pdata->fixed_clk_rate);
443 if (dev_desc->flags & LPSS_CLK_GATE) {
444 clk = clk_register_gate(NULL, devname, parent, 0,
445 prv_base, 0, 0, NULL);
449 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
450 /* Prevent division by zero */
451 if (!readl(prv_base))
452 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
454 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
457 clk = clk_register_fractional_divider(NULL, clk_name, parent,
458 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
459 prv_base, 1, 15, 16, 15, 0, NULL);
462 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
467 clk = clk_register_gate(NULL, clk_name, parent,
468 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
469 prv_base, 31, 0, NULL);
478 clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
482 struct lpss_device_links {
483 const char *supplier_hid;
484 const char *supplier_uid;
485 const char *consumer_hid;
486 const char *consumer_uid;
488 const struct dmi_system_id *dep_missing_ids;
491 /* Please keep this list sorted alphabetically by vendor and model */
492 static const struct dmi_system_id i2c1_dep_missing_dmi_ids[] = {
495 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
496 DMI_MATCH(DMI_PRODUCT_NAME, "T200TA"),
503 * The _DEP method is used to identify dependencies but instead of creating
504 * device links for every handle in _DEP, only links in the following list are
505 * created. That is necessary because, in the general case, _DEP can refer to
506 * devices that might not have drivers, or that are on different buses, or where
507 * the supplier is not enumerated until after the consumer is probed.
509 static const struct lpss_device_links lpss_device_links[] = {
510 /* CHT External sdcard slot controller depends on PMIC I2C ctrl */
511 {"808622C1", "7", "80860F14", "3", DL_FLAG_PM_RUNTIME},
512 /* CHT iGPU depends on PMIC I2C controller */
513 {"808622C1", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
514 /* BYT iGPU depends on the Embedded Controller I2C controller (UID 1) */
515 {"80860F41", "1", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME,
516 i2c1_dep_missing_dmi_ids},
517 /* BYT CR iGPU depends on PMIC I2C controller (UID 5 on CR) */
518 {"80860F41", "5", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
519 /* BYT iGPU depends on PMIC I2C controller (UID 7 on non CR) */
520 {"80860F41", "7", "LNXVIDEO", NULL, DL_FLAG_PM_RUNTIME},
523 static bool acpi_lpss_is_supplier(struct acpi_device *adev,
524 const struct lpss_device_links *link)
526 return acpi_dev_hid_uid_match(adev, link->supplier_hid, link->supplier_uid);
529 static bool acpi_lpss_is_consumer(struct acpi_device *adev,
530 const struct lpss_device_links *link)
532 return acpi_dev_hid_uid_match(adev, link->consumer_hid, link->consumer_uid);
540 static int match_hid_uid(struct device *dev, const void *data)
542 struct acpi_device *adev = ACPI_COMPANION(dev);
543 const struct hid_uid *id = data;
548 return acpi_dev_hid_uid_match(adev, id->hid, id->uid);
551 static struct device *acpi_lpss_find_device(const char *hid, const char *uid)
555 struct hid_uid data = {
560 dev = bus_find_device(&platform_bus_type, NULL, &data, match_hid_uid);
564 return bus_find_device(&pci_bus_type, NULL, &data, match_hid_uid);
567 static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)
569 struct acpi_handle_list dep_devices;
573 if (!acpi_has_method(adev->handle, "_DEP"))
576 status = acpi_evaluate_reference(adev->handle, "_DEP", NULL,
578 if (ACPI_FAILURE(status)) {
579 dev_dbg(&adev->dev, "Failed to evaluate _DEP.\n");
583 for (i = 0; i < dep_devices.count; i++) {
584 if (dep_devices.handles[i] == handle)
591 static void acpi_lpss_link_consumer(struct device *dev1,
592 const struct lpss_device_links *link)
596 dev2 = acpi_lpss_find_device(link->consumer_hid, link->consumer_uid);
600 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
601 || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))
602 device_link_add(dev2, dev1, link->flags);
607 static void acpi_lpss_link_supplier(struct device *dev1,
608 const struct lpss_device_links *link)
612 dev2 = acpi_lpss_find_device(link->supplier_hid, link->supplier_uid);
616 if ((link->dep_missing_ids && dmi_check_system(link->dep_missing_ids))
617 || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))
618 device_link_add(dev1, dev2, link->flags);
623 static void acpi_lpss_create_device_links(struct acpi_device *adev,
624 struct platform_device *pdev)
628 for (i = 0; i < ARRAY_SIZE(lpss_device_links); i++) {
629 const struct lpss_device_links *link = &lpss_device_links[i];
631 if (acpi_lpss_is_supplier(adev, link))
632 acpi_lpss_link_consumer(&pdev->dev, link);
634 if (acpi_lpss_is_consumer(adev, link))
635 acpi_lpss_link_supplier(&pdev->dev, link);
639 static int acpi_lpss_create_device(struct acpi_device *adev,
640 const struct acpi_device_id *id)
642 const struct lpss_device_desc *dev_desc;
643 struct lpss_private_data *pdata;
644 struct resource_entry *rentry;
645 struct list_head resource_list;
646 struct platform_device *pdev;
649 dev_desc = (const struct lpss_device_desc *)id->driver_data;
651 pdev = acpi_create_platform_device(adev, NULL);
652 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
654 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
658 INIT_LIST_HEAD(&resource_list);
659 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
663 list_for_each_entry(rentry, &resource_list, node)
664 if (resource_type(rentry->res) == IORESOURCE_MEM) {
665 if (dev_desc->prv_size_override)
666 pdata->mmio_size = dev_desc->prv_size_override;
668 pdata->mmio_size = resource_size(rentry->res);
669 pdata->mmio_base = ioremap(rentry->res->start,
674 acpi_dev_free_resource_list(&resource_list);
676 if (!pdata->mmio_base) {
677 /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */
678 adev->pnp.type.platform_id = 0;
679 /* Skip the device, but continue the namespace scan. */
685 pdata->dev_desc = dev_desc;
688 dev_desc->setup(pdata);
690 if (dev_desc->flags & LPSS_CLK) {
691 ret = register_device_clock(adev, pdata);
693 /* Skip the device, but continue the namespace scan. */
700 * This works around a known issue in ACPI tables where LPSS devices
701 * have _PS0 and _PS3 without _PSC (and no power resources), so
702 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
704 acpi_device_fix_up_power(adev);
706 adev->driver_data = pdata;
707 pdev = acpi_create_platform_device(adev, dev_desc->properties);
708 if (!IS_ERR_OR_NULL(pdev)) {
709 acpi_lpss_create_device_links(adev, pdev);
714 adev->driver_data = NULL;
721 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
723 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
726 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
729 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
732 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
734 struct acpi_device *adev = ACPI_COMPANION(dev);
735 struct lpss_private_data *pdata;
742 spin_lock_irqsave(&dev->power.lock, flags);
743 if (pm_runtime_suspended(dev)) {
747 pdata = acpi_driver_data(adev);
748 if (WARN_ON(!pdata || !pdata->mmio_base)) {
752 *val = __lpss_reg_read(pdata, reg);
756 spin_unlock_irqrestore(&dev->power.lock, flags);
760 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
767 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
768 ret = lpss_reg_read(dev, reg, <r_value);
772 return sysfs_emit(buf, "%08x\n", ltr_value);
775 static ssize_t lpss_ltr_mode_show(struct device *dev,
776 struct device_attribute *attr, char *buf)
782 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
786 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
787 return sprintf(buf, "%s\n", outstr);
790 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
791 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
792 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
794 static struct attribute *lpss_attrs[] = {
795 &dev_attr_auto_ltr.attr,
796 &dev_attr_sw_ltr.attr,
797 &dev_attr_ltr_mode.attr,
801 static const struct attribute_group lpss_attr_group = {
806 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
808 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
809 u32 ltr_mode, ltr_val;
811 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
813 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
814 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
815 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
819 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
820 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
821 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
822 val = LPSS_LTR_MAX_VAL;
823 } else if (val > LPSS_LTR_MAX_VAL) {
824 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
825 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
827 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
830 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
831 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
832 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
833 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
839 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
841 * @pdata: pointer to the private data of the LPSS device
843 * Most LPSS devices have private registers which may loose their context when
844 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
847 static void acpi_lpss_save_ctx(struct device *dev,
848 struct lpss_private_data *pdata)
852 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
853 unsigned long offset = i * sizeof(u32);
855 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
856 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
857 pdata->prv_reg_ctx[i], offset);
862 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
864 * @pdata: pointer to the private data of the LPSS device
866 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
868 static void acpi_lpss_restore_ctx(struct device *dev,
869 struct lpss_private_data *pdata)
873 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
874 unsigned long offset = i * sizeof(u32);
876 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
877 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
878 pdata->prv_reg_ctx[i], offset);
882 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
885 * The following delay is needed or the subsequent write operations may
886 * fail. The LPSS devices are actually PCI devices and the PCI spec
887 * expects 10ms delay before the device can be accessed after D3 to D0
888 * transition. However some platforms like BSW does not need this delay.
890 unsigned int delay = 10; /* default 10ms delay */
892 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
898 static int acpi_lpss_activate(struct device *dev)
900 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
903 ret = acpi_dev_resume(dev);
907 acpi_lpss_d3_to_d0_delay(pdata);
910 * This is called only on ->probe() stage where a device is either in
911 * known state defined by BIOS or most likely powered off. Due to this
912 * we have to deassert reset line to be sure that ->probe() will
913 * recognize the device.
915 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
916 lpss_deassert_reset(pdata);
919 if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE)
920 acpi_lpss_save_ctx(dev, pdata);
926 static void acpi_lpss_dismiss(struct device *dev)
928 acpi_dev_suspend(dev, false);
931 /* IOSF SB for LPSS island */
932 #define LPSS_IOSF_UNIT_LPIOEP 0xA0
933 #define LPSS_IOSF_UNIT_LPIO1 0xAB
934 #define LPSS_IOSF_UNIT_LPIO2 0xAC
936 #define LPSS_IOSF_PMCSR 0x84
937 #define LPSS_PMCSR_D0 0
938 #define LPSS_PMCSR_D3hot 3
939 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
941 #define LPSS_IOSF_GPIODEF0 0x154
942 #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
943 #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
944 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
945 #define LPSS_GPIODEF0_DMA_LLP BIT(13)
947 static DEFINE_MUTEX(lpss_iosf_mutex);
948 static bool lpss_iosf_d3_entered = true;
950 static void lpss_iosf_enter_d3_state(void)
953 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
954 u32 value2 = LPSS_PMCSR_D3hot;
955 u32 mask2 = LPSS_PMCSR_Dx_MASK;
957 * PMC provides an information about actual status of the LPSS devices.
958 * Here we read the values related to LPSS power island, i.e. LPSS
959 * devices, excluding both LPSS DMA controllers, along with SCC domain.
961 u32 func_dis, d3_sts_0, pmc_status;
964 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
968 mutex_lock(&lpss_iosf_mutex);
970 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
975 * Get the status of entire LPSS power island per device basis.
976 * Shutdown both LPSS DMA controllers if and only if all other devices
977 * are already in D3hot.
979 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_atom_d3_mask;
983 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
984 LPSS_IOSF_PMCSR, value2, mask2);
986 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
987 LPSS_IOSF_PMCSR, value2, mask2);
989 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
990 LPSS_IOSF_GPIODEF0, value1, mask1);
992 lpss_iosf_d3_entered = true;
995 mutex_unlock(&lpss_iosf_mutex);
998 static void lpss_iosf_exit_d3_state(void)
1000 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
1001 LPSS_GPIODEF0_DMA_LLP;
1002 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
1003 u32 value2 = LPSS_PMCSR_D0;
1004 u32 mask2 = LPSS_PMCSR_Dx_MASK;
1006 mutex_lock(&lpss_iosf_mutex);
1008 if (!lpss_iosf_d3_entered)
1011 lpss_iosf_d3_entered = false;
1013 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
1014 LPSS_IOSF_GPIODEF0, value1, mask1);
1016 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
1017 LPSS_IOSF_PMCSR, value2, mask2);
1019 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
1020 LPSS_IOSF_PMCSR, value2, mask2);
1023 mutex_unlock(&lpss_iosf_mutex);
1026 static int acpi_lpss_suspend(struct device *dev, bool wakeup)
1028 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1031 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
1032 acpi_lpss_save_ctx(dev, pdata);
1034 ret = acpi_dev_suspend(dev, wakeup);
1037 * This call must be last in the sequence, otherwise PMC will return
1038 * wrong status for devices being about to be powered off. See
1039 * lpss_iosf_enter_d3_state() for further information.
1041 if (acpi_target_system_state() == ACPI_STATE_S0 &&
1042 lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1043 lpss_iosf_enter_d3_state();
1048 static int acpi_lpss_resume(struct device *dev)
1050 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1054 * This call is kept first to be in symmetry with
1055 * acpi_lpss_runtime_suspend() one.
1057 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
1058 lpss_iosf_exit_d3_state();
1060 ret = acpi_dev_resume(dev);
1064 acpi_lpss_d3_to_d0_delay(pdata);
1066 if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE))
1067 acpi_lpss_restore_ctx(dev, pdata);
1072 #ifdef CONFIG_PM_SLEEP
1073 static int acpi_lpss_do_suspend_late(struct device *dev)
1077 if (dev_pm_skip_suspend(dev))
1080 ret = pm_generic_suspend_late(dev);
1081 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1084 static int acpi_lpss_suspend_late(struct device *dev)
1086 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1088 if (pdata->dev_desc->resume_from_noirq)
1091 return acpi_lpss_do_suspend_late(dev);
1094 static int acpi_lpss_suspend_noirq(struct device *dev)
1096 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1099 if (pdata->dev_desc->resume_from_noirq) {
1101 * The driver's ->suspend_late callback will be invoked by
1102 * acpi_lpss_do_suspend_late(), with the assumption that the
1103 * driver really wanted to run that code in ->suspend_noirq, but
1104 * it could not run after acpi_dev_suspend() and the driver
1105 * expected the latter to be called in the "late" phase.
1107 ret = acpi_lpss_do_suspend_late(dev);
1112 return acpi_subsys_suspend_noirq(dev);
1115 static int acpi_lpss_do_resume_early(struct device *dev)
1117 int ret = acpi_lpss_resume(dev);
1119 return ret ? ret : pm_generic_resume_early(dev);
1122 static int acpi_lpss_resume_early(struct device *dev)
1124 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1126 if (pdata->dev_desc->resume_from_noirq)
1129 if (dev_pm_skip_resume(dev))
1132 return acpi_lpss_do_resume_early(dev);
1135 static int acpi_lpss_resume_noirq(struct device *dev)
1137 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1140 /* Follow acpi_subsys_resume_noirq(). */
1141 if (dev_pm_skip_resume(dev))
1144 ret = pm_generic_resume_noirq(dev);
1148 if (!pdata->dev_desc->resume_from_noirq)
1152 * The driver's ->resume_early callback will be invoked by
1153 * acpi_lpss_do_resume_early(), with the assumption that the driver
1154 * really wanted to run that code in ->resume_noirq, but it could not
1155 * run before acpi_dev_resume() and the driver expected the latter to be
1156 * called in the "early" phase.
1158 return acpi_lpss_do_resume_early(dev);
1161 static int acpi_lpss_do_restore_early(struct device *dev)
1163 int ret = acpi_lpss_resume(dev);
1165 return ret ? ret : pm_generic_restore_early(dev);
1168 static int acpi_lpss_restore_early(struct device *dev)
1170 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1172 if (pdata->dev_desc->resume_from_noirq)
1175 return acpi_lpss_do_restore_early(dev);
1178 static int acpi_lpss_restore_noirq(struct device *dev)
1180 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1183 ret = pm_generic_restore_noirq(dev);
1187 if (!pdata->dev_desc->resume_from_noirq)
1190 /* This is analogous to what happens in acpi_lpss_resume_noirq(). */
1191 return acpi_lpss_do_restore_early(dev);
1194 static int acpi_lpss_do_poweroff_late(struct device *dev)
1196 int ret = pm_generic_poweroff_late(dev);
1198 return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev));
1201 static int acpi_lpss_poweroff_late(struct device *dev)
1203 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1205 if (dev_pm_skip_suspend(dev))
1208 if (pdata->dev_desc->resume_from_noirq)
1211 return acpi_lpss_do_poweroff_late(dev);
1214 static int acpi_lpss_poweroff_noirq(struct device *dev)
1216 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1218 if (dev_pm_skip_suspend(dev))
1221 if (pdata->dev_desc->resume_from_noirq) {
1222 /* This is analogous to the acpi_lpss_suspend_noirq() case. */
1223 int ret = acpi_lpss_do_poweroff_late(dev);
1229 return pm_generic_poweroff_noirq(dev);
1231 #endif /* CONFIG_PM_SLEEP */
1233 static int acpi_lpss_runtime_suspend(struct device *dev)
1235 int ret = pm_generic_runtime_suspend(dev);
1237 return ret ? ret : acpi_lpss_suspend(dev, true);
1240 static int acpi_lpss_runtime_resume(struct device *dev)
1242 int ret = acpi_lpss_resume(dev);
1244 return ret ? ret : pm_generic_runtime_resume(dev);
1246 #endif /* CONFIG_PM */
1248 static struct dev_pm_domain acpi_lpss_pm_domain = {
1250 .activate = acpi_lpss_activate,
1251 .dismiss = acpi_lpss_dismiss,
1255 #ifdef CONFIG_PM_SLEEP
1256 .prepare = acpi_subsys_prepare,
1257 .complete = acpi_subsys_complete,
1258 .suspend = acpi_subsys_suspend,
1259 .suspend_late = acpi_lpss_suspend_late,
1260 .suspend_noirq = acpi_lpss_suspend_noirq,
1261 .resume_noirq = acpi_lpss_resume_noirq,
1262 .resume_early = acpi_lpss_resume_early,
1263 .freeze = acpi_subsys_freeze,
1264 .poweroff = acpi_subsys_poweroff,
1265 .poweroff_late = acpi_lpss_poweroff_late,
1266 .poweroff_noirq = acpi_lpss_poweroff_noirq,
1267 .restore_noirq = acpi_lpss_restore_noirq,
1268 .restore_early = acpi_lpss_restore_early,
1270 .runtime_suspend = acpi_lpss_runtime_suspend,
1271 .runtime_resume = acpi_lpss_runtime_resume,
1276 static int acpi_lpss_platform_notify(struct notifier_block *nb,
1277 unsigned long action, void *data)
1279 struct platform_device *pdev = to_platform_device(data);
1280 struct lpss_private_data *pdata;
1281 struct acpi_device *adev;
1282 const struct acpi_device_id *id;
1284 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
1285 if (!id || !id->driver_data)
1288 adev = ACPI_COMPANION(&pdev->dev);
1292 pdata = acpi_driver_data(adev);
1296 if (pdata->mmio_base &&
1297 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
1298 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
1303 case BUS_NOTIFY_BIND_DRIVER:
1304 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1306 case BUS_NOTIFY_DRIVER_NOT_BOUND:
1307 case BUS_NOTIFY_UNBOUND_DRIVER:
1308 dev_pm_domain_set(&pdev->dev, NULL);
1310 case BUS_NOTIFY_ADD_DEVICE:
1311 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
1312 if (pdata->dev_desc->flags & LPSS_LTR)
1313 return sysfs_create_group(&pdev->dev.kobj,
1316 case BUS_NOTIFY_DEL_DEVICE:
1317 if (pdata->dev_desc->flags & LPSS_LTR)
1318 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
1319 dev_pm_domain_set(&pdev->dev, NULL);
1328 static struct notifier_block acpi_lpss_nb = {
1329 .notifier_call = acpi_lpss_platform_notify,
1332 static void acpi_lpss_bind(struct device *dev)
1334 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
1336 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
1339 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
1340 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
1342 dev_err(dev, "MMIO size insufficient to access LTR\n");
1345 static void acpi_lpss_unbind(struct device *dev)
1347 dev->power.set_latency_tolerance = NULL;
1350 static struct acpi_scan_handler lpss_handler = {
1351 .ids = acpi_lpss_device_ids,
1352 .attach = acpi_lpss_create_device,
1353 .bind = acpi_lpss_bind,
1354 .unbind = acpi_lpss_unbind,
1357 void __init acpi_lpss_init(void)
1359 const struct x86_cpu_id *id;
1362 ret = lpss_atom_clk_init();
1366 id = x86_match_cpu(lpss_cpu_ids);
1368 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
1370 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
1371 acpi_scan_add_handler(&lpss_handler);
1376 static struct acpi_scan_handler lpss_handler = {
1377 .ids = acpi_lpss_device_ids,
1380 void __init acpi_lpss_init(void)
1382 acpi_scan_add_handler(&lpss_handler);
1385 #endif /* CONFIG_X86_INTEL_LPSS */