GNU Linux-libre 4.4.289-gnu1
[releases.git] / drivers / acpi / acpi_lpss.c
1 /*
2  * ACPI support for Intel Lynxpoint LPSS.
3  *
4  * Copyright (C) 2013, Intel Corporation
5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/acpi.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk-provider.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/platform_device.h>
19 #include <linux/platform_data/clk-lpss.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/delay.h>
22
23 #include "internal.h"
24
25 ACPI_MODULE_NAME("acpi_lpss");
26
27 #ifdef CONFIG_X86_INTEL_LPSS
28
29 #define LPSS_ADDR(desc) ((unsigned long)&desc)
30
31 #define LPSS_CLK_SIZE   0x04
32 #define LPSS_LTR_SIZE   0x18
33
34 /* Offsets relative to LPSS_PRIVATE_OFFSET */
35 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
36 #define LPSS_RESETS                     0x04
37 #define LPSS_RESETS_RESET_FUNC          BIT(0)
38 #define LPSS_RESETS_RESET_APB           BIT(1)
39 #define LPSS_GENERAL                    0x08
40 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
41 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
42 #define LPSS_SW_LTR                     0x10
43 #define LPSS_AUTO_LTR                   0x14
44 #define LPSS_LTR_SNOOP_REQ              BIT(15)
45 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
46 #define LPSS_LTR_SNOOP_LAT_1US          0x800
47 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
48 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
49 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
50 #define LPSS_LTR_MAX_VAL                0x3FF
51 #define LPSS_TX_INT                     0x20
52 #define LPSS_TX_INT_MASK                BIT(1)
53
54 #define LPSS_PRV_REG_COUNT              9
55
56 /* LPSS Flags */
57 #define LPSS_CLK                        BIT(0)
58 #define LPSS_CLK_GATE                   BIT(1)
59 #define LPSS_CLK_DIVIDER                BIT(2)
60 #define LPSS_LTR                        BIT(3)
61 #define LPSS_SAVE_CTX                   BIT(4)
62 #define LPSS_NO_D3_DELAY                BIT(5)
63
64 struct lpss_private_data;
65
66 struct lpss_device_desc {
67         unsigned int flags;
68         const char *clk_con_id;
69         unsigned int prv_offset;
70         size_t prv_size_override;
71         void (*setup)(struct lpss_private_data *pdata);
72 };
73
74 static struct lpss_device_desc lpss_dma_desc = {
75         .flags = LPSS_CLK,
76 };
77
78 struct lpss_private_data {
79         void __iomem *mmio_base;
80         resource_size_t mmio_size;
81         unsigned int fixed_clk_rate;
82         struct clk *clk;
83         const struct lpss_device_desc *dev_desc;
84         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
85 };
86
87 /* UART Component Parameter Register */
88 #define LPSS_UART_CPR                   0xF4
89 #define LPSS_UART_CPR_AFCE              BIT(4)
90
91 static void lpss_uart_setup(struct lpss_private_data *pdata)
92 {
93         unsigned int offset;
94         u32 val;
95
96         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
97         val = readl(pdata->mmio_base + offset);
98         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
99
100         val = readl(pdata->mmio_base + LPSS_UART_CPR);
101         if (!(val & LPSS_UART_CPR_AFCE)) {
102                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
103                 val = readl(pdata->mmio_base + offset);
104                 val |= LPSS_GENERAL_UART_RTS_OVRD;
105                 writel(val, pdata->mmio_base + offset);
106         }
107 }
108
109 static void lpss_deassert_reset(struct lpss_private_data *pdata)
110 {
111         unsigned int offset;
112         u32 val;
113
114         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
115         val = readl(pdata->mmio_base + offset);
116         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
117         writel(val, pdata->mmio_base + offset);
118 }
119
120 #define LPSS_I2C_ENABLE                 0x6c
121
122 static void byt_i2c_setup(struct lpss_private_data *pdata)
123 {
124         lpss_deassert_reset(pdata);
125
126         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
127                 pdata->fixed_clk_rate = 133000000;
128
129         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
130 }
131
132 static const struct lpss_device_desc lpt_dev_desc = {
133         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
134         .prv_offset = 0x800,
135 };
136
137 static const struct lpss_device_desc lpt_i2c_dev_desc = {
138         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
139         .prv_offset = 0x800,
140 };
141
142 static const struct lpss_device_desc lpt_uart_dev_desc = {
143         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
144         .clk_con_id = "baudclk",
145         .prv_offset = 0x800,
146         .setup = lpss_uart_setup,
147 };
148
149 static const struct lpss_device_desc lpt_sdio_dev_desc = {
150         .flags = LPSS_LTR,
151         .prv_offset = 0x1000,
152         .prv_size_override = 0x1018,
153 };
154
155 static const struct lpss_device_desc byt_pwm_dev_desc = {
156         .flags = LPSS_SAVE_CTX,
157         .prv_offset = 0x800,
158 };
159
160 static const struct lpss_device_desc bsw_pwm_dev_desc = {
161         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
162         .prv_offset = 0x800,
163 };
164
165 static const struct lpss_device_desc byt_uart_dev_desc = {
166         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
167         .clk_con_id = "baudclk",
168         .prv_offset = 0x800,
169         .setup = lpss_uart_setup,
170 };
171
172 static const struct lpss_device_desc bsw_uart_dev_desc = {
173         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
174                         | LPSS_NO_D3_DELAY,
175         .clk_con_id = "baudclk",
176         .prv_offset = 0x800,
177         .setup = lpss_uart_setup,
178 };
179
180 static const struct lpss_device_desc byt_spi_dev_desc = {
181         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
182         .prv_offset = 0x400,
183 };
184
185 static const struct lpss_device_desc byt_sdio_dev_desc = {
186         .flags = LPSS_CLK,
187 };
188
189 static const struct lpss_device_desc byt_i2c_dev_desc = {
190         .flags = LPSS_CLK | LPSS_SAVE_CTX,
191         .prv_offset = 0x800,
192         .setup = byt_i2c_setup,
193 };
194
195 static const struct lpss_device_desc bsw_i2c_dev_desc = {
196         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
197         .prv_offset = 0x800,
198         .setup = byt_i2c_setup,
199 };
200
201 static struct lpss_device_desc bsw_spi_dev_desc = {
202         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
203                         | LPSS_NO_D3_DELAY,
204         .prv_offset = 0x400,
205         .setup = lpss_deassert_reset,
206 };
207
208 #else
209
210 #define LPSS_ADDR(desc) (0UL)
211
212 #endif /* CONFIG_X86_INTEL_LPSS */
213
214 static const struct acpi_device_id acpi_lpss_device_ids[] = {
215         /* Generic LPSS devices */
216         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
217
218         /* Lynxpoint LPSS devices */
219         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
220         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
221         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
222         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
223         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
224         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
225         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
226         { "INT33C7", },
227
228         /* BayTrail LPSS devices */
229         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
230         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
231         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
232         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
233         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
234         { "INT33B2", },
235         { "INT33FC", },
236
237         /* Braswell LPSS devices */
238         { "80862286", LPSS_ADDR(lpss_dma_desc) },
239         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
240         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
241         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
242         { "808622C0", LPSS_ADDR(lpss_dma_desc) },
243         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
244
245         /* Broadwell LPSS devices */
246         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
247         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
248         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
249         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
250         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
251         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
252         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
253         { "INT3437", },
254
255         /* Wildcat Point LPSS devices */
256         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
257
258         { }
259 };
260
261 #ifdef CONFIG_X86_INTEL_LPSS
262
263 static int is_memory(struct acpi_resource *res, void *not_used)
264 {
265         struct resource r;
266         return !acpi_dev_resource_memory(res, &r);
267 }
268
269 /* LPSS main clock device. */
270 static struct platform_device *lpss_clk_dev;
271
272 static inline void lpt_register_clock_device(void)
273 {
274         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
275 }
276
277 static int register_device_clock(struct acpi_device *adev,
278                                  struct lpss_private_data *pdata)
279 {
280         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
281         const char *devname = dev_name(&adev->dev);
282         struct clk *clk = ERR_PTR(-ENODEV);
283         struct lpss_clk_data *clk_data;
284         const char *parent, *clk_name;
285         void __iomem *prv_base;
286
287         if (!lpss_clk_dev)
288                 lpt_register_clock_device();
289
290         clk_data = platform_get_drvdata(lpss_clk_dev);
291         if (!clk_data)
292                 return -ENODEV;
293         clk = clk_data->clk;
294
295         if (!pdata->mmio_base
296             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
297                 return -ENODATA;
298
299         parent = clk_data->name;
300         prv_base = pdata->mmio_base + dev_desc->prv_offset;
301
302         if (pdata->fixed_clk_rate) {
303                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
304                                               pdata->fixed_clk_rate);
305                 goto out;
306         }
307
308         if (dev_desc->flags & LPSS_CLK_GATE) {
309                 clk = clk_register_gate(NULL, devname, parent, 0,
310                                         prv_base, 0, 0, NULL);
311                 parent = devname;
312         }
313
314         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
315                 /* Prevent division by zero */
316                 if (!readl(prv_base))
317                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
318
319                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
320                 if (!clk_name)
321                         return -ENOMEM;
322                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
323                                                       0, prv_base,
324                                                       1, 15, 16, 15, 0, NULL);
325                 parent = clk_name;
326
327                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
328                 if (!clk_name) {
329                         kfree(parent);
330                         return -ENOMEM;
331                 }
332                 clk = clk_register_gate(NULL, clk_name, parent,
333                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
334                                         prv_base, 31, 0, NULL);
335                 kfree(parent);
336                 kfree(clk_name);
337         }
338 out:
339         if (IS_ERR(clk))
340                 return PTR_ERR(clk);
341
342         pdata->clk = clk;
343         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
344         return 0;
345 }
346
347 static int acpi_lpss_create_device(struct acpi_device *adev,
348                                    const struct acpi_device_id *id)
349 {
350         const struct lpss_device_desc *dev_desc;
351         struct lpss_private_data *pdata;
352         struct resource_entry *rentry;
353         struct list_head resource_list;
354         struct platform_device *pdev;
355         int ret;
356
357         dev_desc = (const struct lpss_device_desc *)id->driver_data;
358         if (!dev_desc) {
359                 pdev = acpi_create_platform_device(adev);
360                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
361         }
362         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
363         if (!pdata)
364                 return -ENOMEM;
365
366         INIT_LIST_HEAD(&resource_list);
367         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
368         if (ret < 0)
369                 goto err_out;
370
371         list_for_each_entry(rentry, &resource_list, node)
372                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
373                         if (dev_desc->prv_size_override)
374                                 pdata->mmio_size = dev_desc->prv_size_override;
375                         else
376                                 pdata->mmio_size = resource_size(rentry->res);
377                         pdata->mmio_base = ioremap(rentry->res->start,
378                                                    pdata->mmio_size);
379                         break;
380                 }
381
382         acpi_dev_free_resource_list(&resource_list);
383
384         if (!pdata->mmio_base) {
385                 ret = -ENOMEM;
386                 goto err_out;
387         }
388
389         pdata->dev_desc = dev_desc;
390
391         if (dev_desc->setup)
392                 dev_desc->setup(pdata);
393
394         if (dev_desc->flags & LPSS_CLK) {
395                 ret = register_device_clock(adev, pdata);
396                 if (ret) {
397                         /* Skip the device, but continue the namespace scan. */
398                         ret = 0;
399                         goto err_out;
400                 }
401         }
402
403         /*
404          * This works around a known issue in ACPI tables where LPSS devices
405          * have _PS0 and _PS3 without _PSC (and no power resources), so
406          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
407          */
408         acpi_device_fix_up_power(adev);
409
410         adev->driver_data = pdata;
411         pdev = acpi_create_platform_device(adev);
412         if (!IS_ERR_OR_NULL(pdev)) {
413                 return 1;
414         }
415
416         ret = PTR_ERR(pdev);
417         adev->driver_data = NULL;
418
419  err_out:
420         kfree(pdata);
421         return ret;
422 }
423
424 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
425 {
426         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
427 }
428
429 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
430                              unsigned int reg)
431 {
432         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
433 }
434
435 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
436 {
437         struct acpi_device *adev;
438         struct lpss_private_data *pdata;
439         unsigned long flags;
440         int ret;
441
442         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
443         if (WARN_ON(ret))
444                 return ret;
445
446         spin_lock_irqsave(&dev->power.lock, flags);
447         if (pm_runtime_suspended(dev)) {
448                 ret = -EAGAIN;
449                 goto out;
450         }
451         pdata = acpi_driver_data(adev);
452         if (WARN_ON(!pdata || !pdata->mmio_base)) {
453                 ret = -ENODEV;
454                 goto out;
455         }
456         *val = __lpss_reg_read(pdata, reg);
457
458  out:
459         spin_unlock_irqrestore(&dev->power.lock, flags);
460         return ret;
461 }
462
463 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
464                              char *buf)
465 {
466         u32 ltr_value = 0;
467         unsigned int reg;
468         int ret;
469
470         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
471         ret = lpss_reg_read(dev, reg, &ltr_value);
472         if (ret)
473                 return ret;
474
475         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
476 }
477
478 static ssize_t lpss_ltr_mode_show(struct device *dev,
479                                   struct device_attribute *attr, char *buf)
480 {
481         u32 ltr_mode = 0;
482         char *outstr;
483         int ret;
484
485         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
486         if (ret)
487                 return ret;
488
489         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
490         return sprintf(buf, "%s\n", outstr);
491 }
492
493 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
494 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
495 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
496
497 static struct attribute *lpss_attrs[] = {
498         &dev_attr_auto_ltr.attr,
499         &dev_attr_sw_ltr.attr,
500         &dev_attr_ltr_mode.attr,
501         NULL,
502 };
503
504 static struct attribute_group lpss_attr_group = {
505         .attrs = lpss_attrs,
506         .name = "lpss_ltr",
507 };
508
509 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
510 {
511         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
512         u32 ltr_mode, ltr_val;
513
514         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
515         if (val < 0) {
516                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
517                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
518                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
519                 }
520                 return;
521         }
522         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
523         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
524                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
525                 val = LPSS_LTR_MAX_VAL;
526         } else if (val > LPSS_LTR_MAX_VAL) {
527                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
528                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
529         } else {
530                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
531         }
532         ltr_val |= val;
533         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
534         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
535                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
536                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
537         }
538 }
539
540 #ifdef CONFIG_PM
541 /**
542  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
543  * @dev: LPSS device
544  * @pdata: pointer to the private data of the LPSS device
545  *
546  * Most LPSS devices have private registers which may loose their context when
547  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
548  * prv_reg_ctx array.
549  */
550 static void acpi_lpss_save_ctx(struct device *dev,
551                                struct lpss_private_data *pdata)
552 {
553         unsigned int i;
554
555         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
556                 unsigned long offset = i * sizeof(u32);
557
558                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
559                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
560                         pdata->prv_reg_ctx[i], offset);
561         }
562 }
563
564 /**
565  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
566  * @dev: LPSS device
567  * @pdata: pointer to the private data of the LPSS device
568  *
569  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
570  */
571 static void acpi_lpss_restore_ctx(struct device *dev,
572                                   struct lpss_private_data *pdata)
573 {
574         unsigned int i;
575
576         /*
577          * The following delay is needed or the subsequent write operations may
578          * fail. The LPSS devices are actually PCI devices and the PCI spec
579          * expects 10ms delay before the device can be accessed after D3 to D0
580          * transition. However some platforms like BSW does not need this delay.
581          */
582         unsigned int delay = 10;        /* default 10ms delay */
583
584         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
585                 delay = 0;
586
587         msleep(delay);
588
589         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
590                 unsigned long offset = i * sizeof(u32);
591
592                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
593                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
594                         pdata->prv_reg_ctx[i], offset);
595         }
596 }
597
598 #ifdef CONFIG_PM_SLEEP
599 static int acpi_lpss_suspend_late(struct device *dev)
600 {
601         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
602         int ret;
603
604         ret = pm_generic_suspend_late(dev);
605         if (ret)
606                 return ret;
607
608         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
609                 acpi_lpss_save_ctx(dev, pdata);
610
611         return acpi_dev_suspend_late(dev);
612 }
613
614 static int acpi_lpss_resume_early(struct device *dev)
615 {
616         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
617         int ret;
618
619         ret = acpi_dev_resume_early(dev);
620         if (ret)
621                 return ret;
622
623         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
624                 acpi_lpss_restore_ctx(dev, pdata);
625
626         return pm_generic_resume_early(dev);
627 }
628 #endif /* CONFIG_PM_SLEEP */
629
630 static int acpi_lpss_runtime_suspend(struct device *dev)
631 {
632         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
633         int ret;
634
635         ret = pm_generic_runtime_suspend(dev);
636         if (ret)
637                 return ret;
638
639         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
640                 acpi_lpss_save_ctx(dev, pdata);
641
642         return acpi_dev_runtime_suspend(dev);
643 }
644
645 static int acpi_lpss_runtime_resume(struct device *dev)
646 {
647         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
648         int ret;
649
650         ret = acpi_dev_runtime_resume(dev);
651         if (ret)
652                 return ret;
653
654         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
655                 acpi_lpss_restore_ctx(dev, pdata);
656
657         return pm_generic_runtime_resume(dev);
658 }
659 #endif /* CONFIG_PM */
660
661 static struct dev_pm_domain acpi_lpss_pm_domain = {
662         .ops = {
663 #ifdef CONFIG_PM
664 #ifdef CONFIG_PM_SLEEP
665                 .prepare = acpi_subsys_prepare,
666                 .complete = pm_complete_with_resume_check,
667                 .suspend = acpi_subsys_suspend,
668                 .suspend_late = acpi_lpss_suspend_late,
669                 .resume_early = acpi_lpss_resume_early,
670                 .freeze = acpi_subsys_freeze,
671                 .poweroff = acpi_subsys_suspend,
672                 .poweroff_late = acpi_lpss_suspend_late,
673                 .restore_early = acpi_lpss_resume_early,
674 #endif
675                 .runtime_suspend = acpi_lpss_runtime_suspend,
676                 .runtime_resume = acpi_lpss_runtime_resume,
677 #endif
678         },
679 };
680
681 static int acpi_lpss_platform_notify(struct notifier_block *nb,
682                                      unsigned long action, void *data)
683 {
684         struct platform_device *pdev = to_platform_device(data);
685         struct lpss_private_data *pdata;
686         struct acpi_device *adev;
687         const struct acpi_device_id *id;
688
689         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
690         if (!id || !id->driver_data)
691                 return 0;
692
693         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
694                 return 0;
695
696         pdata = acpi_driver_data(adev);
697         if (!pdata)
698                 return 0;
699
700         if (pdata->mmio_base &&
701             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
702                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
703                 return 0;
704         }
705
706         switch (action) {
707         case BUS_NOTIFY_BOUND_DRIVER:
708                 pdev->dev.pm_domain = &acpi_lpss_pm_domain;
709                 break;
710         case BUS_NOTIFY_UNBOUND_DRIVER:
711                 pdev->dev.pm_domain = NULL;
712                 break;
713         case BUS_NOTIFY_ADD_DEVICE:
714                 if (pdata->dev_desc->flags & LPSS_LTR)
715                         return sysfs_create_group(&pdev->dev.kobj,
716                                                   &lpss_attr_group);
717                 break;
718         case BUS_NOTIFY_DEL_DEVICE:
719                 if (pdata->dev_desc->flags & LPSS_LTR)
720                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
721                 break;
722         default:
723                 break;
724         }
725
726         return 0;
727 }
728
729 static struct notifier_block acpi_lpss_nb = {
730         .notifier_call = acpi_lpss_platform_notify,
731 };
732
733 static void acpi_lpss_bind(struct device *dev)
734 {
735         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
736
737         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
738                 return;
739
740         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
741                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
742         else
743                 dev_err(dev, "MMIO size insufficient to access LTR\n");
744 }
745
746 static void acpi_lpss_unbind(struct device *dev)
747 {
748         dev->power.set_latency_tolerance = NULL;
749 }
750
751 static struct acpi_scan_handler lpss_handler = {
752         .ids = acpi_lpss_device_ids,
753         .attach = acpi_lpss_create_device,
754         .bind = acpi_lpss_bind,
755         .unbind = acpi_lpss_unbind,
756 };
757
758 void __init acpi_lpss_init(void)
759 {
760         if (!lpt_clk_init()) {
761                 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
762                 acpi_scan_add_handler(&lpss_handler);
763         }
764 }
765
766 #else
767
768 static struct acpi_scan_handler lpss_handler = {
769         .ids = acpi_lpss_device_ids,
770 };
771
772 void __init acpi_lpss_init(void)
773 {
774         acpi_scan_add_handler(&lpss_handler);
775 }
776
777 #endif /* CONFIG_X86_INTEL_LPSS */