2 * OMAP DPLL clock support
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
23 #include <linux/of_address.h>
24 #include <linux/clk/ti.h>
28 #define pr_fmt(fmt) "%s: " fmt, __func__
30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
31 defined(CONFIG_SOC_DRA7XX)
32 static const struct clk_ops dpll_m4xen_ck_ops = {
33 .enable = &omap3_noncore_dpll_enable,
34 .disable = &omap3_noncore_dpll_disable,
35 .recalc_rate = &omap4_dpll_regm4xen_recalc,
36 .round_rate = &omap4_dpll_regm4xen_round_rate,
37 .set_rate = &omap3_noncore_dpll_set_rate,
38 .set_parent = &omap3_noncore_dpll_set_parent,
39 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
40 .determine_rate = &omap4_dpll_regm4xen_determine_rate,
41 .get_parent = &omap2_init_dpll_parent,
44 static const struct clk_ops dpll_m4xen_ck_ops = {};
47 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
48 defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
49 defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
50 static const struct clk_ops dpll_core_ck_ops = {
51 .recalc_rate = &omap3_dpll_recalc,
52 .get_parent = &omap2_init_dpll_parent,
55 static const struct clk_ops dpll_ck_ops = {
56 .enable = &omap3_noncore_dpll_enable,
57 .disable = &omap3_noncore_dpll_disable,
58 .recalc_rate = &omap3_dpll_recalc,
59 .round_rate = &omap2_dpll_round_rate,
60 .set_rate = &omap3_noncore_dpll_set_rate,
61 .set_parent = &omap3_noncore_dpll_set_parent,
62 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
63 .determine_rate = &omap3_noncore_dpll_determine_rate,
64 .get_parent = &omap2_init_dpll_parent,
67 static const struct clk_ops dpll_no_gate_ck_ops = {
68 .recalc_rate = &omap3_dpll_recalc,
69 .get_parent = &omap2_init_dpll_parent,
70 .round_rate = &omap2_dpll_round_rate,
71 .set_rate = &omap3_noncore_dpll_set_rate,
72 .set_parent = &omap3_noncore_dpll_set_parent,
73 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
74 .determine_rate = &omap3_noncore_dpll_determine_rate,
77 static const struct clk_ops dpll_core_ck_ops = {};
78 static const struct clk_ops dpll_ck_ops = {};
79 static const struct clk_ops dpll_no_gate_ck_ops = {};
80 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
83 #ifdef CONFIG_ARCH_OMAP2
84 static const struct clk_ops omap2_dpll_core_ck_ops = {
85 .get_parent = &omap2_init_dpll_parent,
86 .recalc_rate = &omap2_dpllcore_recalc,
87 .round_rate = &omap2_dpll_round_rate,
88 .set_rate = &omap2_reprogram_dpllcore,
91 static const struct clk_ops omap2_dpll_core_ck_ops = {};
94 #ifdef CONFIG_ARCH_OMAP3
95 static const struct clk_ops omap3_dpll_core_ck_ops = {
96 .get_parent = &omap2_init_dpll_parent,
97 .recalc_rate = &omap3_dpll_recalc,
98 .round_rate = &omap2_dpll_round_rate,
101 static const struct clk_ops omap3_dpll_core_ck_ops = {};
104 #ifdef CONFIG_ARCH_OMAP3
105 static const struct clk_ops omap3_dpll_ck_ops = {
106 .enable = &omap3_noncore_dpll_enable,
107 .disable = &omap3_noncore_dpll_disable,
108 .get_parent = &omap2_init_dpll_parent,
109 .recalc_rate = &omap3_dpll_recalc,
110 .set_rate = &omap3_noncore_dpll_set_rate,
111 .set_parent = &omap3_noncore_dpll_set_parent,
112 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
113 .determine_rate = &omap3_noncore_dpll_determine_rate,
114 .round_rate = &omap2_dpll_round_rate,
117 static const struct clk_ops omap3_dpll5_ck_ops = {
118 .enable = &omap3_noncore_dpll_enable,
119 .disable = &omap3_noncore_dpll_disable,
120 .get_parent = &omap2_init_dpll_parent,
121 .recalc_rate = &omap3_dpll_recalc,
122 .set_rate = &omap3_dpll5_set_rate,
123 .set_parent = &omap3_noncore_dpll_set_parent,
124 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
125 .determine_rate = &omap3_noncore_dpll_determine_rate,
126 .round_rate = &omap2_dpll_round_rate,
129 static const struct clk_ops omap3_dpll_per_ck_ops = {
130 .enable = &omap3_noncore_dpll_enable,
131 .disable = &omap3_noncore_dpll_disable,
132 .get_parent = &omap2_init_dpll_parent,
133 .recalc_rate = &omap3_dpll_recalc,
134 .set_rate = &omap3_dpll4_set_rate,
135 .set_parent = &omap3_noncore_dpll_set_parent,
136 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
137 .determine_rate = &omap3_noncore_dpll_determine_rate,
138 .round_rate = &omap2_dpll_round_rate,
142 static const struct clk_ops dpll_x2_ck_ops = {
143 .recalc_rate = &omap3_clkoutx2_recalc,
147 * _register_dpll - low level registration of a DPLL clock
148 * @hw: hardware clock definition for the clock
149 * @node: device node for the clock
151 * Finalizes DPLL registration process. In case a failure (clk-ref or
152 * clk-bypass is missing), the clock is added to retry list and
153 * the initialization is retried on later stage.
155 static void __init _register_dpll(struct clk_hw *hw,
156 struct device_node *node)
158 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
159 struct dpll_data *dd = clk_hw->dpll_data;
162 dd->clk_ref = of_clk_get(node, 0);
163 dd->clk_bypass = of_clk_get(node, 1);
165 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
166 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
168 if (!ti_clk_retry_init(node, hw, _register_dpll))
174 /* register the clock */
175 clk = clk_register(NULL, &clk_hw->hw);
178 omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
179 of_clk_add_provider(node, of_clk_src_simple_get, clk);
180 kfree(clk_hw->hw.init->parent_names);
181 kfree(clk_hw->hw.init);
186 kfree(clk_hw->dpll_data);
187 kfree(clk_hw->hw.init->parent_names);
188 kfree(clk_hw->hw.init);
192 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
193 static void __iomem *_get_reg(u8 module, u16 offset)
196 struct clk_omap_reg *reg_setup;
198 reg_setup = (struct clk_omap_reg *)®
200 reg_setup->index = module;
201 reg_setup->offset = offset;
203 return (void __iomem *)reg;
206 struct clk *ti_clk_register_dpll(struct ti_clk *setup)
208 struct clk_hw_omap *clk_hw;
209 struct clk_init_data init = { NULL };
210 struct dpll_data *dd;
212 struct ti_clk_dpll *dpll;
213 const struct clk_ops *ops = &omap3_dpll_ck_ops;
215 struct clk *clk_bypass;
219 if (dpll->num_parents < 2)
220 return ERR_PTR(-EINVAL);
222 clk_ref = clk_get_sys(NULL, dpll->parents[0]);
223 clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
225 if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
226 return ERR_PTR(-EAGAIN);
228 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
229 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
230 if (!dd || !clk_hw) {
231 clk = ERR_PTR(-ENOMEM);
235 clk_hw->dpll_data = dd;
236 clk_hw->ops = &clkhwops_omap3_dpll;
237 clk_hw->hw.init = &init;
238 clk_hw->flags = MEMMAP_ADDRESSING;
240 init.name = setup->name;
243 init.num_parents = dpll->num_parents;
244 init.parent_names = dpll->parents;
246 dd->control_reg = _get_reg(dpll->module, dpll->control_reg);
247 dd->idlest_reg = _get_reg(dpll->module, dpll->idlest_reg);
248 dd->mult_div1_reg = _get_reg(dpll->module, dpll->mult_div1_reg);
249 dd->autoidle_reg = _get_reg(dpll->module, dpll->autoidle_reg);
251 dd->modes = dpll->modes;
252 dd->div1_mask = dpll->div1_mask;
253 dd->idlest_mask = dpll->idlest_mask;
254 dd->mult_mask = dpll->mult_mask;
255 dd->autoidle_mask = dpll->autoidle_mask;
256 dd->enable_mask = dpll->enable_mask;
257 dd->sddiv_mask = dpll->sddiv_mask;
258 dd->dco_mask = dpll->dco_mask;
259 dd->max_divider = dpll->max_divider;
260 dd->min_divider = dpll->min_divider;
261 dd->max_multiplier = dpll->max_multiplier;
262 dd->auto_recal_bit = dpll->auto_recal_bit;
263 dd->recal_en_bit = dpll->recal_en_bit;
264 dd->recal_st_bit = dpll->recal_st_bit;
266 dd->clk_ref = clk_ref;
267 dd->clk_bypass = clk_bypass;
269 if (dpll->flags & CLKF_CORE)
270 ops = &omap3_dpll_core_ck_ops;
272 if (dpll->flags & CLKF_PER)
273 ops = &omap3_dpll_per_ck_ops;
275 if (dpll->flags & CLKF_J_TYPE)
276 dd->flags |= DPLL_J_TYPE;
278 clk = clk_register(NULL, &clk_hw->hw);
290 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
291 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
292 defined(CONFIG_SOC_AM43XX)
294 * _register_dpll_x2 - Registers a DPLLx2 clock
295 * @node: device node for this clock
296 * @ops: clk_ops for this clock
297 * @hw_ops: clk_hw_ops for this clock
299 * Initializes a DPLL x 2 clock from device tree data.
301 static void _register_dpll_x2(struct device_node *node,
302 const struct clk_ops *ops,
303 const struct clk_hw_omap_ops *hw_ops)
306 struct clk_init_data init = { NULL };
307 struct clk_hw_omap *clk_hw;
308 const char *name = node->name;
309 const char *parent_name;
311 parent_name = of_clk_get_parent_name(node, 0);
313 pr_err("%s must have parent\n", node->name);
317 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
321 clk_hw->ops = hw_ops;
322 clk_hw->hw.init = &init;
326 init.parent_names = &parent_name;
327 init.num_parents = 1;
329 /* register the clock */
330 clk = clk_register(NULL, &clk_hw->hw);
335 omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
336 of_clk_add_provider(node, of_clk_src_simple_get, clk);
342 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
343 * @node: device node containing the DPLL info
344 * @ops: ops for the DPLL
345 * @ddt: DPLL data template to use
347 * Initializes a DPLL clock from device tree data.
349 static void __init of_ti_dpll_setup(struct device_node *node,
350 const struct clk_ops *ops,
351 const struct dpll_data *ddt)
353 struct clk_hw_omap *clk_hw = NULL;
354 struct clk_init_data *init = NULL;
355 const char **parent_names = NULL;
356 struct dpll_data *dd = NULL;
359 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
360 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
361 init = kzalloc(sizeof(*init), GFP_KERNEL);
362 if (!dd || !clk_hw || !init)
365 memcpy(dd, ddt, sizeof(*dd));
367 clk_hw->dpll_data = dd;
368 clk_hw->ops = &clkhwops_omap3_dpll;
369 clk_hw->hw.init = init;
370 clk_hw->flags = MEMMAP_ADDRESSING;
372 init->name = node->name;
375 init->num_parents = of_clk_get_parent_count(node);
376 if (init->num_parents < 1) {
377 pr_err("%s must have parent(s)\n", node->name);
381 parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
385 of_clk_parent_fill(node, parent_names, init->num_parents);
387 init->parent_names = parent_names;
389 dd->control_reg = ti_clk_get_reg_addr(node, 0);
392 * Special case for OMAP2 DPLL, register order is different due to
393 * missing idlest_reg, also clkhwops is different. Detected from
394 * missing idlest_mask.
396 if (!dd->idlest_mask) {
397 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
398 #ifdef CONFIG_ARCH_OMAP2
399 clk_hw->ops = &clkhwops_omap2xxx_dpll;
400 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
403 dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
404 if (IS_ERR(dd->idlest_reg))
407 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
410 if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg))
413 if (dd->autoidle_mask) {
414 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
415 if (IS_ERR(dd->autoidle_reg))
419 if (of_property_read_bool(node, "ti,low-power-stop"))
420 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
422 if (of_property_read_bool(node, "ti,low-power-bypass"))
423 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
425 if (of_property_read_bool(node, "ti,lock"))
426 dpll_mode |= 1 << DPLL_LOCKED;
429 dd->modes = dpll_mode;
431 _register_dpll(&clk_hw->hw, node);
441 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
442 defined(CONFIG_SOC_DRA7XX)
443 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
445 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
447 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
448 of_ti_omap4_dpll_x2_setup);
451 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
452 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
454 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
456 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
457 of_ti_am3_dpll_x2_setup);
460 #ifdef CONFIG_ARCH_OMAP3
461 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
463 const struct dpll_data dd = {
466 .autoidle_mask = 0x7,
467 .mult_mask = 0x7ff << 8,
469 .max_multiplier = 2047,
472 .freqsel_mask = 0xf0,
473 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
476 if ((of_machine_is_compatible("ti,omap3630") ||
477 of_machine_is_compatible("ti,omap36xx")) &&
478 !strcmp(node->name, "dpll5_ck"))
479 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
481 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
483 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
484 of_ti_omap3_dpll_setup);
486 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
488 const struct dpll_data dd = {
491 .autoidle_mask = 0x7,
492 .mult_mask = 0x7ff << 16,
493 .div1_mask = 0x7f << 8,
494 .max_multiplier = 2047,
497 .freqsel_mask = 0xf0,
500 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
502 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
503 of_ti_omap3_core_dpll_setup);
505 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
507 const struct dpll_data dd = {
508 .idlest_mask = 0x1 << 1,
509 .enable_mask = 0x7 << 16,
510 .autoidle_mask = 0x7 << 3,
511 .mult_mask = 0x7ff << 8,
513 .max_multiplier = 2047,
516 .freqsel_mask = 0xf00000,
517 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
520 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
522 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
523 of_ti_omap3_per_dpll_setup);
525 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
527 const struct dpll_data dd = {
528 .idlest_mask = 0x1 << 1,
529 .enable_mask = 0x7 << 16,
530 .autoidle_mask = 0x7 << 3,
531 .mult_mask = 0xfff << 8,
533 .max_multiplier = 4095,
536 .sddiv_mask = 0xff << 24,
537 .dco_mask = 0xe << 20,
538 .flags = DPLL_J_TYPE,
539 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
542 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
544 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
545 of_ti_omap3_per_jtype_dpll_setup);
548 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
550 const struct dpll_data dd = {
553 .autoidle_mask = 0x7,
554 .mult_mask = 0x7ff << 8,
556 .max_multiplier = 2047,
559 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
562 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
564 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
565 of_ti_omap4_dpll_setup);
567 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
569 const struct dpll_data dd = {
572 .autoidle_mask = 0x7,
573 .mult_mask = 0x7ff << 8,
575 .max_multiplier = 2047,
578 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
580 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
583 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
585 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
586 of_ti_omap5_mpu_dpll_setup);
588 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
590 const struct dpll_data dd = {
593 .autoidle_mask = 0x7,
594 .mult_mask = 0x7ff << 8,
596 .max_multiplier = 2047,
599 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
602 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
604 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
605 of_ti_omap4_core_dpll_setup);
607 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
608 defined(CONFIG_SOC_DRA7XX)
609 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
611 const struct dpll_data dd = {
614 .autoidle_mask = 0x7,
615 .mult_mask = 0x7ff << 8,
617 .max_multiplier = 2047,
621 .lpmode_mask = 1 << 10,
622 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
625 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
627 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
628 of_ti_omap4_m4xen_dpll_setup);
630 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
632 const struct dpll_data dd = {
635 .autoidle_mask = 0x7,
636 .mult_mask = 0xfff << 8,
638 .max_multiplier = 4095,
641 .sddiv_mask = 0xff << 24,
642 .flags = DPLL_J_TYPE,
643 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
646 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
648 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
649 of_ti_omap4_jtype_dpll_setup);
652 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
654 const struct dpll_data dd = {
657 .mult_mask = 0x7ff << 8,
659 .max_multiplier = 2047,
662 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
665 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
667 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
668 of_ti_am3_no_gate_dpll_setup);
670 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
672 const struct dpll_data dd = {
675 .mult_mask = 0x7ff << 8,
677 .max_multiplier = 4095,
680 .flags = DPLL_J_TYPE,
681 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
684 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
686 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
687 of_ti_am3_jtype_dpll_setup);
689 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
691 const struct dpll_data dd = {
694 .mult_mask = 0x7ff << 8,
696 .max_multiplier = 2047,
699 .flags = DPLL_J_TYPE,
700 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
703 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
705 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
706 "ti,am3-dpll-no-gate-j-type-clock",
707 of_ti_am3_no_gate_jtype_dpll_setup);
709 static void __init of_ti_am3_dpll_setup(struct device_node *node)
711 const struct dpll_data dd = {
714 .mult_mask = 0x7ff << 8,
716 .max_multiplier = 2047,
719 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
722 of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
724 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
726 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
728 const struct dpll_data dd = {
731 .mult_mask = 0x7ff << 8,
733 .max_multiplier = 2047,
736 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
739 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
741 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
742 of_ti_am3_core_dpll_setup);
744 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
746 const struct dpll_data dd = {
748 .mult_mask = 0x3ff << 12,
749 .div1_mask = 0xf << 8,
754 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
756 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
757 of_ti_omap2_core_dpll_setup);