1 /* Copyright 2014-2016 Freescale Semiconductor Inc.
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13 * derived from this software without specific prior written permission.
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17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
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36 #include <linux/netdevice.h>
37 #include <linux/if_vlan.h>
39 #include "../../fsl-mc/include/dpaa2-io.h"
40 #include "../../fsl-mc/include/dpaa2-fd.h"
41 #include "../../fsl-mc/include/dpbp.h"
42 #include "../../fsl-mc/include/dpcon.h"
46 #include "dpaa2-eth-trace.h"
48 #define DPAA2_ETH_STORE_SIZE 16
50 /* Maximum number of scatter-gather entries in an ingress frame,
51 * considering the maximum receive frame size is 64K
53 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
55 /* Maximum acceptable MTU value. It is in direct relation with the hardware
56 * enforced Max Frame Length (currently 10k).
58 #define DPAA2_ETH_MFL (10 * 1024)
59 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
60 /* Convert L3 MTU to L2 MFL */
61 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
63 /* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo
64 * frames in the Rx queues (length of the current frame is not
65 * taken into account when making the taildrop decision)
67 #define DPAA2_ETH_TAILDROP_THRESH (64 * 1024)
69 /* Buffer quota per queue. Must be large enough such that for minimum sized
70 * frames taildrop kicks in before the bpool gets depleted, so we compute
71 * how many 64B frames fit inside the taildrop threshold and add a margin
72 * to accommodate the buffer refill delay.
74 #define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64)
75 #define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256)
76 #define DPAA2_ETH_REFILL_THRESH DPAA2_ETH_MAX_FRAMES_PER_QUEUE
78 /* Maximum number of buffers that can be acquired/released through a single
81 #define DPAA2_ETH_BUFS_PER_CMD 7
83 /* Hardware requires alignment for ingress/egress buffer addresses
84 * and ingress buffer lengths.
86 #define DPAA2_ETH_RX_BUF_SIZE 2048
87 #define DPAA2_ETH_TX_BUF_ALIGN 64
88 #define DPAA2_ETH_RX_BUF_ALIGN 256
89 #define DPAA2_ETH_NEEDED_HEADROOM(p_priv) \
90 ((p_priv)->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN)
92 /* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but we need to allocate ingress
93 * buffers large enough to allow building an skb around them and also account
94 * for alignment restrictions
96 #define DPAA2_ETH_BUF_RAW_SIZE \
97 (DPAA2_ETH_RX_BUF_SIZE + \
98 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \
99 DPAA2_ETH_RX_BUF_ALIGN)
101 /* We are accommodating a skb backpointer and some S/G info
102 * in the frame's software annotation. The hardware
103 * options are either 0 or 64, so we choose the latter.
105 #define DPAA2_ETH_SWA_SIZE 64
107 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
108 struct dpaa2_eth_swa {
110 struct scatterlist *scl;
115 /* Annotation valid bits in FD FRC */
116 #define DPAA2_FD_FRC_FASV 0x8000
117 #define DPAA2_FD_FRC_FAEADV 0x4000
118 #define DPAA2_FD_FRC_FAPRV 0x2000
119 #define DPAA2_FD_FRC_FAIADV 0x1000
120 #define DPAA2_FD_FRC_FASWOV 0x0800
121 #define DPAA2_FD_FRC_FAICFDV 0x0400
123 /* Error bits in FD CTRL */
124 #define DPAA2_FD_CTRL_UFD 0x00000004
125 #define DPAA2_FD_CTRL_SBE 0x00000008
126 #define DPAA2_FD_CTRL_FSE 0x00000020
127 #define DPAA2_FD_CTRL_FAERR 0x00000040
129 #define DPAA2_FD_RX_ERR_MASK (DPAA2_FD_CTRL_SBE | \
131 #define DPAA2_FD_TX_ERR_MASK (DPAA2_FD_CTRL_UFD | \
132 DPAA2_FD_CTRL_SBE | \
133 DPAA2_FD_CTRL_FSE | \
136 /* Annotation bits in FD CTRL */
137 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */
138 #define DPAA2_FD_CTRL_PTA 0x00800000
139 #define DPAA2_FD_CTRL_PTV1 0x00400000
141 /* Frame annotation status */
149 /* Frame annotation status word is located in the first 8 bytes
150 * of the buffer's hardware annoatation area
152 #define DPAA2_FAS_OFFSET 0
153 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
155 /* Accessors for the hardware annotation fields that we use */
156 #define dpaa2_get_hwa(buf_addr) \
157 ((void *)(buf_addr) + DPAA2_ETH_SWA_SIZE)
158 #define dpaa2_get_fas(buf_addr) \
159 (struct dpaa2_fas *)(dpaa2_get_hwa(buf_addr) + DPAA2_FAS_OFFSET)
161 /* Error and status bits in the frame annotation status word */
162 /* Debug frame, otherwise supposed to be discarded */
163 #define DPAA2_FAS_DISC 0x80000000
165 #define DPAA2_FAS_MS 0x40000000
166 #define DPAA2_FAS_PTP 0x08000000
167 /* Ethernet multicast frame */
168 #define DPAA2_FAS_MC 0x04000000
169 /* Ethernet broadcast frame */
170 #define DPAA2_FAS_BC 0x02000000
171 #define DPAA2_FAS_KSE 0x00040000
172 #define DPAA2_FAS_EOFHE 0x00020000
173 #define DPAA2_FAS_MNLE 0x00010000
174 #define DPAA2_FAS_TIDE 0x00008000
175 #define DPAA2_FAS_PIEE 0x00004000
176 /* Frame length error */
177 #define DPAA2_FAS_FLE 0x00002000
178 /* Frame physical error */
179 #define DPAA2_FAS_FPE 0x00001000
180 #define DPAA2_FAS_PTE 0x00000080
181 #define DPAA2_FAS_ISP 0x00000040
182 #define DPAA2_FAS_PHE 0x00000020
183 #define DPAA2_FAS_BLE 0x00000010
184 /* L3 csum validation performed */
185 #define DPAA2_FAS_L3CV 0x00000008
187 #define DPAA2_FAS_L3CE 0x00000004
188 /* L4 csum validation performed */
189 #define DPAA2_FAS_L4CV 0x00000002
191 #define DPAA2_FAS_L4CE 0x00000001
192 /* Possible errors on the ingress path */
193 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \
207 #define DPAA2_FAS_TX_ERR_MASK (DPAA2_FAS_KSE | \
212 /* Time in milliseconds between link state updates */
213 #define DPAA2_ETH_LINK_STATE_REFRESH 1000
215 /* Number of times to retry a frame enqueue before giving up.
216 * Value determined empirically, in order to minimize the number
217 * of frames dropped on Tx
219 #define DPAA2_ETH_ENQUEUE_RETRIES 10
221 /* Driver statistics, other than those in struct rtnl_link_stats64.
222 * These are usually collected per-CPU and aggregated by ethtool.
224 struct dpaa2_eth_drv_stats {
225 __u64 tx_conf_frames;
231 /* Enqueues retried due to portal busy */
232 __u64 tx_portal_busy;
235 /* Per-FQ statistics */
236 struct dpaa2_eth_fq_stats {
237 /* Number of frames received on this queue */
241 /* Per-channel statistics */
242 struct dpaa2_eth_ch_stats {
243 /* Volatile dequeues retried due to portal busy */
244 __u64 dequeue_portal_busy;
245 /* Number of CDANs; useful to estimate avg NAPI len */
247 /* Number of frames received on queues from this channel */
253 /* Maximum number of queues associated with a DPNI */
254 #define DPAA2_ETH_MAX_RX_QUEUES 16
255 #define DPAA2_ETH_MAX_TX_QUEUES NR_CPUS
256 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
257 DPAA2_ETH_MAX_TX_QUEUES)
259 #define DPAA2_ETH_MAX_DPCONS NR_CPUS
261 enum dpaa2_eth_fq_type {
266 struct dpaa2_eth_priv;
268 struct dpaa2_eth_fq {
273 struct dpaa2_eth_channel *channel;
274 enum dpaa2_eth_fq_type type;
276 void (*consume)(struct dpaa2_eth_priv *,
277 struct dpaa2_eth_channel *,
278 const struct dpaa2_fd *,
279 struct napi_struct *);
280 struct dpaa2_eth_fq_stats stats;
283 struct dpaa2_eth_channel {
284 struct dpaa2_io_notification_ctx nctx;
285 struct fsl_mc_device *dpcon;
289 struct napi_struct napi;
290 struct dpaa2_io_store *store;
291 struct dpaa2_eth_priv *priv;
293 struct dpaa2_eth_ch_stats stats;
296 struct dpaa2_eth_hash_fields {
298 enum net_prot cls_prot;
303 /* Driver private data */
304 struct dpaa2_eth_priv {
305 struct net_device *net_dev;
308 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
311 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
313 struct dpni_attr dpni_attrs;
316 struct fsl_mc_device *dpbp_dev;
318 struct iommu_domain *iommu_domain;
321 struct fsl_mc_io *mc_io;
322 /* Cores which have an affine DPIO/DPCON.
323 * This is the cpu set on which Rx and Tx conf frames are processed
325 struct cpumask dpio_cpumask;
327 /* Standard statistics */
328 struct rtnl_link_stats64 __percpu *percpu_stats;
329 /* Extra stats, in addition to the ones known by the kernel */
330 struct dpaa2_eth_drv_stats __percpu *percpu_extras;
334 struct dpni_link_state link_state;
336 struct task_struct *poll_thread;
338 /* enabled ethtool hashing bits */
342 /* default Rx hash options, set during probing */
343 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
344 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
347 #define dpaa2_eth_hash_enabled(priv) \
348 ((priv)->dpni_attrs.num_queues > 1)
350 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
351 #define DPAA2_CLASSIFIER_DMA_SIZE 256
353 extern const struct ethtool_ops dpaa2_ethtool_ops;
354 extern const char dpaa2_eth_drv_version[];
356 static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv)
358 return priv->dpni_attrs.num_queues;
361 #endif /* __DPAA2_H */