1 /* Copyright 2014-2016 Freescale Semiconductor Inc.
2 * Copyright 2016-2017 NXP
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution.
11 * * Neither the name of Freescale Semiconductor nor the
12 * names of its contributors may be used to endorse or promote products
13 * derived from this software without specific prior written permission.
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/platform_device.h>
35 #include <linux/etherdevice.h>
36 #include <linux/of_net.h>
37 #include <linux/interrupt.h>
38 #include <linux/msi.h>
39 #include <linux/kthread.h>
40 #include <linux/iommu.h>
42 #include "../../fsl-mc/include/mc.h"
43 #include "dpaa2-eth.h"
45 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
46 * using trace events only need to #include <trace/events/sched.h>
48 #define CREATE_TRACE_POINTS
49 #include "dpaa2-eth-trace.h"
51 MODULE_LICENSE("Dual BSD/GPL");
52 MODULE_AUTHOR("Freescale Semiconductor, Inc");
53 MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver");
55 const char dpaa2_eth_drv_version[] = "0.1";
57 static void *dpaa2_iova_to_virt(struct iommu_domain *domain,
60 phys_addr_t phys_addr;
62 phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
64 return phys_to_virt(phys_addr);
67 static void validate_rx_csum(struct dpaa2_eth_priv *priv,
71 skb_checksum_none_assert(skb);
73 /* HW checksum validation is disabled, nothing to do here */
74 if (!(priv->net_dev->features & NETIF_F_RXCSUM))
77 /* Read checksum validation bits */
78 if (!((fd_status & DPAA2_FAS_L3CV) &&
79 (fd_status & DPAA2_FAS_L4CV)))
82 /* Inform the stack there's no need to compute L3/L4 csum anymore */
83 skb->ip_summed = CHECKSUM_UNNECESSARY;
86 /* Free a received FD.
87 * Not to be used for Tx conf FDs or on any other paths.
89 static void free_rx_fd(struct dpaa2_eth_priv *priv,
90 const struct dpaa2_fd *fd,
93 struct device *dev = priv->net_dev->dev.parent;
94 dma_addr_t addr = dpaa2_fd_get_addr(fd);
95 u8 fd_format = dpaa2_fd_get_format(fd);
96 struct dpaa2_sg_entry *sgt;
100 /* If single buffer frame, just free the data buffer */
101 if (fd_format == dpaa2_fd_single)
103 else if (fd_format != dpaa2_fd_sg)
104 /* We don't support any other format */
107 /* For S/G frames, we first need to free all SG entries */
108 sgt = vaddr + dpaa2_fd_get_offset(fd);
109 for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
110 addr = dpaa2_sg_get_addr(&sgt[i]);
111 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
112 dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
115 skb_free_frag(sg_vaddr);
116 if (dpaa2_sg_is_final(&sgt[i]))
121 skb_free_frag(vaddr);
124 /* Build a linear skb based on a single-buffer frame descriptor */
125 static struct sk_buff *build_linear_skb(struct dpaa2_eth_priv *priv,
126 struct dpaa2_eth_channel *ch,
127 const struct dpaa2_fd *fd,
130 struct sk_buff *skb = NULL;
131 u16 fd_offset = dpaa2_fd_get_offset(fd);
132 u32 fd_length = dpaa2_fd_get_len(fd);
136 skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_SIZE +
137 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
141 skb_reserve(skb, fd_offset);
142 skb_put(skb, fd_length);
147 /* Build a non linear (fragmented) skb based on a S/G table */
148 static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv,
149 struct dpaa2_eth_channel *ch,
150 struct dpaa2_sg_entry *sgt)
152 struct sk_buff *skb = NULL;
153 struct device *dev = priv->net_dev->dev.parent;
158 struct page *page, *head_page;
162 for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
163 struct dpaa2_sg_entry *sge = &sgt[i];
165 /* NOTE: We only support SG entries in dpaa2_sg_single format,
166 * but this is the only format we may receive from HW anyway
169 /* Get the address and length from the S/G entry */
170 sg_addr = dpaa2_sg_get_addr(sge);
171 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
172 dma_unmap_single(dev, sg_addr, DPAA2_ETH_RX_BUF_SIZE,
175 sg_length = dpaa2_sg_get_len(sge);
178 /* We build the skb around the first data buffer */
179 skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_SIZE +
180 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
181 if (unlikely(!skb)) {
182 /* We still need to subtract the buffers used
183 * by this FD from our software counter
185 while (!dpaa2_sg_is_final(&sgt[i]) &&
186 i < DPAA2_ETH_MAX_SG_ENTRIES)
191 sg_offset = dpaa2_sg_get_offset(sge);
192 skb_reserve(skb, sg_offset);
193 skb_put(skb, sg_length);
195 /* Rest of the data buffers are stored as skb frags */
196 page = virt_to_page(sg_vaddr);
197 head_page = virt_to_head_page(sg_vaddr);
199 /* Offset in page (which may be compound).
200 * Data in subsequent SG entries is stored from the
201 * beginning of the buffer, so we don't need to add the
204 page_offset = ((unsigned long)sg_vaddr &
206 (page_address(page) - page_address(head_page));
208 skb_add_rx_frag(skb, i - 1, head_page, page_offset,
209 sg_length, DPAA2_ETH_RX_BUF_SIZE);
212 if (dpaa2_sg_is_final(sge))
216 /* Count all data buffers + SG table buffer */
217 ch->buf_count -= i + 2;
222 /* Main Rx frame processing routine */
223 static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
224 struct dpaa2_eth_channel *ch,
225 const struct dpaa2_fd *fd,
226 struct napi_struct *napi)
228 dma_addr_t addr = dpaa2_fd_get_addr(fd);
229 u8 fd_format = dpaa2_fd_get_format(fd);
232 struct rtnl_link_stats64 *percpu_stats;
233 struct dpaa2_eth_drv_stats *percpu_extras;
234 struct device *dev = priv->net_dev->dev.parent;
235 struct dpaa2_fas *fas;
240 trace_dpaa2_rx_fd(priv->net_dev, fd);
242 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
243 dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_FROM_DEVICE);
245 fas = dpaa2_get_fas(vaddr);
247 buf_data = vaddr + dpaa2_fd_get_offset(fd);
250 percpu_stats = this_cpu_ptr(priv->percpu_stats);
251 percpu_extras = this_cpu_ptr(priv->percpu_extras);
253 if (fd_format == dpaa2_fd_single) {
254 skb = build_linear_skb(priv, ch, fd, vaddr);
255 } else if (fd_format == dpaa2_fd_sg) {
256 skb = build_frag_skb(priv, ch, buf_data);
257 skb_free_frag(vaddr);
258 percpu_extras->rx_sg_frames++;
259 percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
261 /* We don't support any other format */
262 goto err_frame_format;
270 /* Check if we need to validate the L4 csum */
271 if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
272 status = le32_to_cpu(fas->status);
273 validate_rx_csum(priv, status, skb);
276 skb->protocol = eth_type_trans(skb, priv->net_dev);
278 percpu_stats->rx_packets++;
279 percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
281 napi_gro_receive(napi, skb);
286 free_rx_fd(priv, fd, vaddr);
288 percpu_stats->rx_dropped++;
291 /* Consume all frames pull-dequeued into the store. This is the simplest way to
292 * make sure we don't accidentally issue another volatile dequeue which would
293 * overwrite (leak) frames already in the store.
295 * Observance of NAPI budget is not our concern, leaving that to the caller.
297 static int consume_frames(struct dpaa2_eth_channel *ch)
299 struct dpaa2_eth_priv *priv = ch->priv;
300 struct dpaa2_eth_fq *fq;
302 const struct dpaa2_fd *fd;
307 dq = dpaa2_io_store_next(ch->store, &is_last);
309 /* If we're here, we *must* have placed a
310 * volatile dequeue comnmand, so keep reading through
311 * the store until we get some sort of valid response
312 * token (either a valid frame or an "empty dequeue")
317 fd = dpaa2_dq_fd(dq);
318 fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
321 fq->consume(priv, ch, fd, &ch->napi);
328 /* Create a frame descriptor based on a fragmented skb */
329 static int build_sg_fd(struct dpaa2_eth_priv *priv,
333 struct device *dev = priv->net_dev->dev.parent;
334 void *sgt_buf = NULL;
336 int nr_frags = skb_shinfo(skb)->nr_frags;
337 struct dpaa2_sg_entry *sgt;
340 struct scatterlist *scl, *crt_scl;
343 struct dpaa2_eth_swa *swa;
344 struct dpaa2_fas *fas;
346 /* Create and map scatterlist.
347 * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
348 * to go beyond nr_frags+1.
349 * Note: We don't support chained scatterlists
351 if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1))
354 scl = kcalloc(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC);
358 sg_init_table(scl, nr_frags + 1);
359 num_sg = skb_to_sgvec(skb, scl, 0, skb->len);
360 num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
361 if (unlikely(!num_dma_bufs)) {
363 goto dma_map_sg_failed;
366 /* Prepare the HW SGT structure */
367 sgt_buf_size = priv->tx_data_offset +
368 sizeof(struct dpaa2_sg_entry) * (1 + num_dma_bufs);
369 sgt_buf = kzalloc(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN, GFP_ATOMIC);
370 if (unlikely(!sgt_buf)) {
372 goto sgt_buf_alloc_failed;
374 sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
376 /* PTA from egress side is passed as is to the confirmation side so
377 * we need to clear some fields here in order to find consistent values
378 * on TX confirmation. We are clearing FAS (Frame Annotation Status)
379 * field from the hardware annotation area
381 fas = dpaa2_get_fas(sgt_buf);
382 memset(fas, 0, DPAA2_FAS_SIZE);
384 sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
386 /* Fill in the HW SGT structure.
388 * sgt_buf is zeroed out, so the following fields are implicit
389 * in all sgt entries:
391 * - format is 'dpaa2_sg_single'
393 for_each_sg(scl, crt_scl, num_dma_bufs, i) {
394 dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl));
395 dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl));
397 dpaa2_sg_set_final(&sgt[i - 1], true);
399 /* Store the skb backpointer in the SGT buffer.
400 * Fit the scatterlist and the number of buffers alongside the
401 * skb backpointer in the software annotation area. We'll need
402 * all of them on Tx Conf.
404 swa = (struct dpaa2_eth_swa *)sgt_buf;
407 swa->num_sg = num_sg;
408 swa->num_dma_bufs = num_dma_bufs;
410 /* Separately map the SGT buffer */
411 addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
412 if (unlikely(dma_mapping_error(dev, addr))) {
414 goto dma_map_single_failed;
416 dpaa2_fd_set_offset(fd, priv->tx_data_offset);
417 dpaa2_fd_set_format(fd, dpaa2_fd_sg);
418 dpaa2_fd_set_addr(fd, addr);
419 dpaa2_fd_set_len(fd, skb->len);
420 dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL | DPAA2_FD_CTRL_PTA |
425 dma_map_single_failed:
427 sgt_buf_alloc_failed:
428 dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
434 /* Create a frame descriptor based on a linear skb */
435 static int build_single_fd(struct dpaa2_eth_priv *priv,
439 struct device *dev = priv->net_dev->dev.parent;
441 struct dpaa2_fas *fas;
442 struct sk_buff **skbh;
445 buffer_start = PTR_ALIGN(skb->data - priv->tx_data_offset -
446 DPAA2_ETH_TX_BUF_ALIGN,
447 DPAA2_ETH_TX_BUF_ALIGN);
449 /* PTA from egress side is passed as is to the confirmation side so
450 * we need to clear some fields here in order to find consistent values
451 * on TX confirmation. We are clearing FAS (Frame Annotation Status)
452 * field from the hardware annotation area
454 fas = dpaa2_get_fas(buffer_start);
455 memset(fas, 0, DPAA2_FAS_SIZE);
457 /* Store a backpointer to the skb at the beginning of the buffer
458 * (in the private data area) such that we can release it
461 skbh = (struct sk_buff **)buffer_start;
464 addr = dma_map_single(dev, buffer_start,
465 skb_tail_pointer(skb) - buffer_start,
467 if (unlikely(dma_mapping_error(dev, addr)))
470 dpaa2_fd_set_addr(fd, addr);
471 dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start));
472 dpaa2_fd_set_len(fd, skb->len);
473 dpaa2_fd_set_format(fd, dpaa2_fd_single);
474 dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL | DPAA2_FD_CTRL_PTA |
480 /* FD freeing routine on the Tx path
482 * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb
483 * back-pointed to is also freed.
484 * This can be called either from dpaa2_eth_tx_conf() or on the error path of
486 * Optionally, return the frame annotation status word (FAS), which needs
487 * to be checked if we're on the confirmation path.
489 static void free_tx_fd(const struct dpaa2_eth_priv *priv,
490 const struct dpaa2_fd *fd,
493 struct device *dev = priv->net_dev->dev.parent;
495 struct sk_buff **skbh, *skb;
496 unsigned char *buffer_start;
498 struct scatterlist *scl;
499 int num_sg, num_dma_bufs;
500 struct dpaa2_eth_swa *swa;
501 u8 fd_format = dpaa2_fd_get_format(fd);
502 struct dpaa2_fas *fas;
504 fd_addr = dpaa2_fd_get_addr(fd);
505 skbh = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
506 fas = dpaa2_get_fas(skbh);
508 if (fd_format == dpaa2_fd_single) {
510 buffer_start = (unsigned char *)skbh;
511 /* Accessing the skb buffer is safe before dma unmap, because
512 * we didn't map the actual skb shell.
514 dma_unmap_single(dev, fd_addr,
515 skb_tail_pointer(skb) - buffer_start,
517 } else if (fd_format == dpaa2_fd_sg) {
518 swa = (struct dpaa2_eth_swa *)skbh;
521 num_sg = swa->num_sg;
522 num_dma_bufs = swa->num_dma_bufs;
524 /* Unmap the scatterlist */
525 dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
528 /* Unmap the SGT buffer */
529 unmap_size = priv->tx_data_offset +
530 sizeof(struct dpaa2_sg_entry) * (1 + num_dma_bufs);
531 dma_unmap_single(dev, fd_addr, unmap_size, DMA_BIDIRECTIONAL);
533 /* Unsupported format, mark it as errored and give up */
539 /* Read the status from the Frame Annotation after we unmap the first
540 * buffer but before we free it. The caller function is responsible
541 * for checking the status value.
544 *status = le32_to_cpu(fas->status);
546 /* Free SGT buffer kmalloc'ed on tx */
547 if (fd_format != dpaa2_fd_single)
550 /* Move on with skb release */
554 static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev)
556 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
558 struct rtnl_link_stats64 *percpu_stats;
559 struct dpaa2_eth_drv_stats *percpu_extras;
560 struct dpaa2_eth_fq *fq;
564 percpu_stats = this_cpu_ptr(priv->percpu_stats);
565 percpu_extras = this_cpu_ptr(priv->percpu_extras);
567 if (unlikely(skb_headroom(skb) < DPAA2_ETH_NEEDED_HEADROOM(priv))) {
570 ns = skb_realloc_headroom(skb, DPAA2_ETH_NEEDED_HEADROOM(priv));
572 percpu_stats->tx_dropped++;
573 goto err_alloc_headroom;
579 /* We'll be holding a back-reference to the skb until Tx Confirmation;
580 * we don't want that overwritten by a concurrent Tx with a cloned skb.
582 skb = skb_unshare(skb, GFP_ATOMIC);
583 if (unlikely(!skb)) {
584 /* skb_unshare() has already freed the skb */
585 percpu_stats->tx_dropped++;
589 /* Setup the FD fields */
590 memset(&fd, 0, sizeof(fd));
592 if (skb_is_nonlinear(skb)) {
593 err = build_sg_fd(priv, skb, &fd);
594 percpu_extras->tx_sg_frames++;
595 percpu_extras->tx_sg_bytes += skb->len;
597 err = build_single_fd(priv, skb, &fd);
601 percpu_stats->tx_dropped++;
606 trace_dpaa2_tx_fd(net_dev, &fd);
608 /* TxConf FQ selection primarily based on cpu affinity; this is
609 * non-migratable context, so it's safe to call smp_processor_id().
611 queue_mapping = smp_processor_id() % dpaa2_eth_queue_count(priv);
612 fq = &priv->fq[queue_mapping];
613 for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
614 err = dpaa2_io_service_enqueue_qd(NULL, priv->tx_qdid, 0,
619 percpu_extras->tx_portal_busy += i;
620 if (unlikely(err < 0)) {
621 percpu_stats->tx_errors++;
622 /* Clean up everything, including freeing the skb */
623 free_tx_fd(priv, &fd, NULL);
625 percpu_stats->tx_packets++;
626 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fd);
638 /* Tx confirmation frame processing routine */
639 static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv,
640 struct dpaa2_eth_channel *ch,
641 const struct dpaa2_fd *fd,
642 struct napi_struct *napi __always_unused)
644 struct rtnl_link_stats64 *percpu_stats;
645 struct dpaa2_eth_drv_stats *percpu_extras;
648 bool has_fas_errors = false;
651 trace_dpaa2_tx_conf_fd(priv->net_dev, fd);
653 percpu_extras = this_cpu_ptr(priv->percpu_extras);
654 percpu_extras->tx_conf_frames++;
655 percpu_extras->tx_conf_bytes += dpaa2_fd_get_len(fd);
657 /* Check frame errors in the FD field */
658 fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
659 if (unlikely(fd_errors)) {
660 /* We only check error bits in the FAS field if corresponding
661 * FAERR bit is set in FD and the FAS field is marked as valid
663 has_fas_errors = (fd_errors & DPAA2_FD_CTRL_FAERR) &&
664 !!(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV);
666 netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
670 free_tx_fd(priv, fd, has_fas_errors ? &status : NULL);
672 if (likely(!fd_errors))
675 percpu_stats = this_cpu_ptr(priv->percpu_stats);
676 /* Tx-conf logically pertains to the egress path. */
677 percpu_stats->tx_errors++;
679 if (has_fas_errors && net_ratelimit())
680 netdev_dbg(priv->net_dev, "TX frame FAS error: 0x%08x\n",
681 status & DPAA2_FAS_TX_ERR_MASK);
684 static int set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
688 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
689 DPNI_OFF_RX_L3_CSUM, enable);
691 netdev_err(priv->net_dev,
692 "dpni_set_offload(RX_L3_CSUM) failed\n");
696 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
697 DPNI_OFF_RX_L4_CSUM, enable);
699 netdev_err(priv->net_dev,
700 "dpni_set_offload(RX_L4_CSUM) failed\n");
707 static int set_tx_csum(struct dpaa2_eth_priv *priv, bool enable)
711 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
712 DPNI_OFF_TX_L3_CSUM, enable);
714 netdev_err(priv->net_dev, "dpni_set_offload(TX_L3_CSUM) failed\n");
718 err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
719 DPNI_OFF_TX_L4_CSUM, enable);
721 netdev_err(priv->net_dev, "dpni_set_offload(TX_L4_CSUM) failed\n");
728 /* Perform a single release command to add buffers
729 * to the specified buffer pool
731 static int add_bufs(struct dpaa2_eth_priv *priv, u16 bpid)
733 struct device *dev = priv->net_dev->dev.parent;
734 u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
739 for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) {
740 /* Allocate buffer visible to WRIOP + skb shared info +
743 buf = napi_alloc_frag(DPAA2_ETH_BUF_RAW_SIZE);
747 buf = PTR_ALIGN(buf, DPAA2_ETH_RX_BUF_ALIGN);
749 addr = dma_map_single(dev, buf, DPAA2_ETH_RX_BUF_SIZE,
751 if (unlikely(dma_mapping_error(dev, addr)))
757 trace_dpaa2_eth_buf_seed(priv->net_dev,
758 buf, DPAA2_ETH_BUF_RAW_SIZE,
759 addr, DPAA2_ETH_RX_BUF_SIZE,
764 /* In case the portal is busy, retry until successful.
765 * The buffer release function would only fail if the QBMan portal
766 * was busy, which implies portal contention (i.e. more CPUs than
767 * portals, i.e. GPPs w/o affine DPIOs). For all practical purposes,
768 * there is little we can realistically do, short of giving up -
769 * in which case we'd risk depleting the buffer pool and never again
770 * receiving the Rx interrupt which would kick-start the refill logic.
771 * So just keep retrying, at the risk of being moved to ksoftirqd.
773 while (dpaa2_io_service_release(NULL, bpid, buf_array, i))
786 static int seed_pool(struct dpaa2_eth_priv *priv, u16 bpid)
791 /* This is the lazy seeding of Rx buffer pools.
792 * dpaa2_add_bufs() is also used on the Rx hotpath and calls
793 * napi_alloc_frag(). The trouble with that is that it in turn ends up
794 * calling this_cpu_ptr(), which mandates execution in atomic context.
795 * Rather than splitting up the code, do a one-off preempt disable.
798 for (j = 0; j < priv->num_channels; j++) {
799 for (i = 0; i < DPAA2_ETH_NUM_BUFS;
800 i += DPAA2_ETH_BUFS_PER_CMD) {
801 new_count = add_bufs(priv, bpid);
802 priv->channel[j]->buf_count += new_count;
804 if (new_count < DPAA2_ETH_BUFS_PER_CMD) {
816 * Drain the specified number of buffers from the DPNI's private buffer pool.
817 * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD
819 static void drain_bufs(struct dpaa2_eth_priv *priv, int count)
821 struct device *dev = priv->net_dev->dev.parent;
822 u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
827 ret = dpaa2_io_service_acquire(NULL, priv->bpid,
830 netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n");
833 for (i = 0; i < ret; i++) {
834 /* Same logic as on regular Rx path */
835 vaddr = dpaa2_iova_to_virt(priv->iommu_domain,
837 dma_unmap_single(dev, buf_array[i],
838 DPAA2_ETH_RX_BUF_SIZE,
840 skb_free_frag(vaddr);
845 static void drain_pool(struct dpaa2_eth_priv *priv)
849 drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD);
852 for (i = 0; i < priv->num_channels; i++)
853 priv->channel[i]->buf_count = 0;
856 /* Function is called from softirq context only, so we don't need to guard
857 * the access to percpu count
859 static int refill_pool(struct dpaa2_eth_priv *priv,
860 struct dpaa2_eth_channel *ch,
865 if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH))
869 new_count = add_bufs(priv, bpid);
870 if (unlikely(!new_count)) {
871 /* Out of memory; abort for now, we'll try later on */
874 ch->buf_count += new_count;
875 } while (ch->buf_count < DPAA2_ETH_NUM_BUFS);
877 if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS))
883 static int pull_channel(struct dpaa2_eth_channel *ch)
888 /* Retry while portal is busy */
890 err = dpaa2_io_service_pull_channel(NULL, ch->ch_id, ch->store);
893 } while (err == -EBUSY);
895 ch->stats.dequeue_portal_busy += dequeues;
897 ch->stats.pull_err++;
904 * Frames are dequeued from the QMan channel associated with this NAPI context.
905 * Rx, Tx confirmation and (if configured) Rx error frames all count
906 * towards the NAPI budget.
908 static int dpaa2_eth_poll(struct napi_struct *napi, int budget)
910 struct dpaa2_eth_channel *ch;
911 int cleaned = 0, store_cleaned;
912 struct dpaa2_eth_priv *priv;
915 ch = container_of(napi, struct dpaa2_eth_channel, napi);
918 while (cleaned < budget) {
919 err = pull_channel(ch);
923 /* Refill pool if appropriate */
924 refill_pool(priv, ch, priv->bpid);
926 store_cleaned = consume_frames(ch);
927 cleaned += store_cleaned;
929 /* If we have enough budget left for a full store,
930 * try a new pull dequeue, otherwise we're done here
932 if (store_cleaned == 0 ||
933 cleaned > budget - DPAA2_ETH_STORE_SIZE)
937 if (cleaned < budget) {
938 napi_complete_done(napi, cleaned);
939 /* Re-enable data available notifications */
941 err = dpaa2_io_service_rearm(NULL, &ch->nctx);
943 } while (err == -EBUSY);
946 ch->stats.frames += cleaned;
951 static void enable_ch_napi(struct dpaa2_eth_priv *priv)
953 struct dpaa2_eth_channel *ch;
956 for (i = 0; i < priv->num_channels; i++) {
957 ch = priv->channel[i];
958 napi_enable(&ch->napi);
962 static void disable_ch_napi(struct dpaa2_eth_priv *priv)
964 struct dpaa2_eth_channel *ch;
967 for (i = 0; i < priv->num_channels; i++) {
968 ch = priv->channel[i];
969 napi_disable(&ch->napi);
973 static int link_state_update(struct dpaa2_eth_priv *priv)
975 struct dpni_link_state state;
978 err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
980 netdev_err(priv->net_dev,
981 "dpni_get_link_state() failed\n");
985 /* Chech link state; speed / duplex changes are not treated yet */
986 if (priv->link_state.up == state.up)
989 priv->link_state = state;
991 netif_carrier_on(priv->net_dev);
992 netif_tx_start_all_queues(priv->net_dev);
994 netif_tx_stop_all_queues(priv->net_dev);
995 netif_carrier_off(priv->net_dev);
998 netdev_info(priv->net_dev, "Link Event: state %s\n",
999 state.up ? "up" : "down");
1004 static int dpaa2_eth_open(struct net_device *net_dev)
1006 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1009 err = seed_pool(priv, priv->bpid);
1011 /* Not much to do; the buffer pool, though not filled up,
1012 * may still contain some buffers which would enable us
1015 netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
1016 priv->dpbp_dev->obj_desc.id, priv->bpid);
1019 /* We'll only start the txqs when the link is actually ready; make sure
1020 * we don't race against the link up notification, which may come
1021 * immediately after dpni_enable();
1023 netif_tx_stop_all_queues(net_dev);
1024 enable_ch_napi(priv);
1025 /* Also, explicitly set carrier off, otherwise netif_carrier_ok() will
1026 * return true and cause 'ip link show' to report the LOWER_UP flag,
1027 * even though the link notification wasn't even received.
1029 netif_carrier_off(net_dev);
1031 err = dpni_enable(priv->mc_io, 0, priv->mc_token);
1033 netdev_err(net_dev, "dpni_enable() failed\n");
1037 /* If the DPMAC object has already processed the link up interrupt,
1038 * we have to learn the link state ourselves.
1040 err = link_state_update(priv);
1042 netdev_err(net_dev, "Can't update link state\n");
1043 goto link_state_err;
1050 disable_ch_napi(priv);
1055 /* The DPIO store must be empty when we call this,
1056 * at the end of every NAPI cycle.
1058 static u32 drain_channel(struct dpaa2_eth_priv *priv,
1059 struct dpaa2_eth_channel *ch)
1061 u32 drained = 0, total = 0;
1065 drained = consume_frames(ch);
1072 static u32 drain_ingress_frames(struct dpaa2_eth_priv *priv)
1074 struct dpaa2_eth_channel *ch;
1078 for (i = 0; i < priv->num_channels; i++) {
1079 ch = priv->channel[i];
1080 drained += drain_channel(priv, ch);
1086 static int dpaa2_eth_stop(struct net_device *net_dev)
1088 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1093 netif_tx_stop_all_queues(net_dev);
1094 netif_carrier_off(net_dev);
1096 /* Loop while dpni_disable() attempts to drain the egress FQs
1097 * and confirm them back to us.
1100 dpni_disable(priv->mc_io, 0, priv->mc_token);
1101 dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled);
1103 /* Allow the hardware some slack */
1105 } while (dpni_enabled && --retries);
1107 netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n");
1108 /* Must go on and disable NAPI nonetheless, so we don't crash at
1109 * the next "ifconfig up"
1113 /* Wait for NAPI to complete on every core and disable it.
1114 * In particular, this will also prevent NAPI from being rescheduled if
1115 * a new CDAN is serviced, effectively discarding the CDAN. We therefore
1116 * don't even need to disarm the channels, except perhaps for the case
1117 * of a huge coalescing value.
1119 disable_ch_napi(priv);
1121 /* Manually drain the Rx and TxConf queues */
1122 drained = drain_ingress_frames(priv);
1124 netdev_dbg(net_dev, "Drained %d frames.\n", drained);
1126 /* Empty the buffer pool */
1132 static int dpaa2_eth_init(struct net_device *net_dev)
1135 u64 not_supported = 0;
1136 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1137 u32 options = priv->dpni_attrs.options;
1139 /* Capabilities listing */
1140 supported |= IFF_LIVE_ADDR_CHANGE;
1142 if (options & DPNI_OPT_NO_MAC_FILTER)
1143 not_supported |= IFF_UNICAST_FLT;
1145 supported |= IFF_UNICAST_FLT;
1147 net_dev->priv_flags |= supported;
1148 net_dev->priv_flags &= ~not_supported;
1151 net_dev->features = NETIF_F_RXCSUM |
1152 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1153 NETIF_F_SG | NETIF_F_HIGHDMA |
1155 net_dev->hw_features = net_dev->features;
1160 static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr)
1162 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1163 struct device *dev = net_dev->dev.parent;
1166 err = eth_mac_addr(net_dev, addr);
1168 dev_err(dev, "eth_mac_addr() failed (%d)\n", err);
1172 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
1175 dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err);
1182 /** Fill in counters maintained by the GPP driver. These may be different from
1183 * the hardware counters obtained by ethtool.
1185 static void dpaa2_eth_get_stats(struct net_device *net_dev,
1186 struct rtnl_link_stats64 *stats)
1188 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1189 struct rtnl_link_stats64 *percpu_stats;
1191 u64 *netstats = (u64 *)stats;
1193 int num = sizeof(struct rtnl_link_stats64) / sizeof(u64);
1195 for_each_possible_cpu(i) {
1196 percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
1197 cpustats = (u64 *)percpu_stats;
1198 for (j = 0; j < num; j++)
1199 netstats[j] += cpustats[j];
1203 static int dpaa2_eth_change_mtu(struct net_device *net_dev, int mtu)
1205 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1208 /* Set the maximum Rx frame length to match the transmit side;
1209 * account for L2 headers when computing the MFL
1211 err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
1212 (u16)DPAA2_ETH_L2_MAX_FRM(mtu));
1214 netdev_err(net_dev, "dpni_set_max_frame_length() failed\n");
1222 /* Copy mac unicast addresses from @net_dev to @priv.
1223 * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1225 static void add_uc_hw_addr(const struct net_device *net_dev,
1226 struct dpaa2_eth_priv *priv)
1228 struct netdev_hw_addr *ha;
1231 netdev_for_each_uc_addr(ha, net_dev) {
1232 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1235 netdev_warn(priv->net_dev,
1236 "Could not add ucast MAC %pM to the filtering table (err %d)\n",
1241 /* Copy mac multicast addresses from @net_dev to @priv
1242 * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1244 static void add_mc_hw_addr(const struct net_device *net_dev,
1245 struct dpaa2_eth_priv *priv)
1247 struct netdev_hw_addr *ha;
1250 netdev_for_each_mc_addr(ha, net_dev) {
1251 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1254 netdev_warn(priv->net_dev,
1255 "Could not add mcast MAC %pM to the filtering table (err %d)\n",
1260 static void dpaa2_eth_set_rx_mode(struct net_device *net_dev)
1262 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1263 int uc_count = netdev_uc_count(net_dev);
1264 int mc_count = netdev_mc_count(net_dev);
1265 u8 max_mac = priv->dpni_attrs.mac_filter_entries;
1266 u32 options = priv->dpni_attrs.options;
1267 u16 mc_token = priv->mc_token;
1268 struct fsl_mc_io *mc_io = priv->mc_io;
1271 /* Basic sanity checks; these probably indicate a misconfiguration */
1272 if (options & DPNI_OPT_NO_MAC_FILTER && max_mac != 0)
1273 netdev_info(net_dev,
1274 "mac_filter_entries=%d, DPNI_OPT_NO_MAC_FILTER option must be disabled\n",
1277 /* Force promiscuous if the uc or mc counts exceed our capabilities. */
1278 if (uc_count > max_mac) {
1279 netdev_info(net_dev,
1280 "Unicast addr count reached %d, max allowed is %d; forcing promisc\n",
1284 if (mc_count + uc_count > max_mac) {
1285 netdev_info(net_dev,
1286 "Unicast + multicast addr count reached %d, max allowed is %d; forcing promisc\n",
1287 uc_count + mc_count, max_mac);
1288 goto force_mc_promisc;
1291 /* Adjust promisc settings due to flag combinations */
1292 if (net_dev->flags & IFF_PROMISC)
1294 if (net_dev->flags & IFF_ALLMULTI) {
1295 /* First, rebuild unicast filtering table. This should be done
1296 * in promisc mode, in order to avoid frame loss while we
1297 * progressively add entries to the table.
1298 * We don't know whether we had been in promisc already, and
1299 * making an MC call to find out is expensive; so set uc promisc
1302 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1304 netdev_warn(net_dev, "Can't set uc promisc\n");
1306 /* Actual uc table reconstruction. */
1307 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0);
1309 netdev_warn(net_dev, "Can't clear uc filters\n");
1310 add_uc_hw_addr(net_dev, priv);
1312 /* Finally, clear uc promisc and set mc promisc as requested. */
1313 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1315 netdev_warn(net_dev, "Can't clear uc promisc\n");
1316 goto force_mc_promisc;
1319 /* Neither unicast, nor multicast promisc will be on... eventually.
1320 * For now, rebuild mac filtering tables while forcing both of them on.
1322 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1324 netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err);
1325 err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
1327 netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err);
1329 /* Actual mac filtering tables reconstruction */
1330 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1);
1332 netdev_warn(net_dev, "Can't clear mac filters\n");
1333 add_mc_hw_addr(net_dev, priv);
1334 add_uc_hw_addr(net_dev, priv);
1336 /* Now we can clear both ucast and mcast promisc, without risking
1337 * to drop legitimate frames anymore.
1339 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1341 netdev_warn(net_dev, "Can't clear ucast promisc\n");
1342 err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0);
1344 netdev_warn(net_dev, "Can't clear mcast promisc\n");
1349 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1351 netdev_warn(net_dev, "Can't set ucast promisc\n");
1353 err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
1355 netdev_warn(net_dev, "Can't set mcast promisc\n");
1358 static int dpaa2_eth_set_features(struct net_device *net_dev,
1359 netdev_features_t features)
1361 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1362 netdev_features_t changed = features ^ net_dev->features;
1366 if (changed & NETIF_F_RXCSUM) {
1367 enable = !!(features & NETIF_F_RXCSUM);
1368 err = set_rx_csum(priv, enable);
1373 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
1374 enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
1375 err = set_tx_csum(priv, enable);
1383 static const struct net_device_ops dpaa2_eth_ops = {
1384 .ndo_open = dpaa2_eth_open,
1385 .ndo_start_xmit = dpaa2_eth_tx,
1386 .ndo_stop = dpaa2_eth_stop,
1387 .ndo_init = dpaa2_eth_init,
1388 .ndo_set_mac_address = dpaa2_eth_set_addr,
1389 .ndo_get_stats64 = dpaa2_eth_get_stats,
1390 .ndo_change_mtu = dpaa2_eth_change_mtu,
1391 .ndo_set_rx_mode = dpaa2_eth_set_rx_mode,
1392 .ndo_set_features = dpaa2_eth_set_features,
1395 static void cdan_cb(struct dpaa2_io_notification_ctx *ctx)
1397 struct dpaa2_eth_channel *ch;
1399 ch = container_of(ctx, struct dpaa2_eth_channel, nctx);
1401 /* Update NAPI statistics */
1404 napi_schedule_irqoff(&ch->napi);
1407 /* Allocate and configure a DPCON object */
1408 static struct fsl_mc_device *setup_dpcon(struct dpaa2_eth_priv *priv)
1410 struct fsl_mc_device *dpcon;
1411 struct device *dev = priv->net_dev->dev.parent;
1412 struct dpcon_attr attrs;
1415 err = fsl_mc_object_allocate(to_fsl_mc_device(dev),
1416 FSL_MC_POOL_DPCON, &dpcon);
1418 dev_info(dev, "Not enough DPCONs, will go on as-is\n");
1422 err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle);
1424 dev_err(dev, "dpcon_open() failed\n");
1428 err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle);
1430 dev_err(dev, "dpcon_reset() failed\n");
1434 err = dpcon_get_attributes(priv->mc_io, 0, dpcon->mc_handle, &attrs);
1436 dev_err(dev, "dpcon_get_attributes() failed\n");
1440 err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle);
1442 dev_err(dev, "dpcon_enable() failed\n");
1451 dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
1453 fsl_mc_object_free(dpcon);
1458 static void free_dpcon(struct dpaa2_eth_priv *priv,
1459 struct fsl_mc_device *dpcon)
1461 dpcon_disable(priv->mc_io, 0, dpcon->mc_handle);
1462 dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
1463 fsl_mc_object_free(dpcon);
1466 static struct dpaa2_eth_channel *
1467 alloc_channel(struct dpaa2_eth_priv *priv)
1469 struct dpaa2_eth_channel *channel;
1470 struct dpcon_attr attr;
1471 struct device *dev = priv->net_dev->dev.parent;
1474 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
1478 channel->dpcon = setup_dpcon(priv);
1479 if (!channel->dpcon)
1482 err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle,
1485 dev_err(dev, "dpcon_get_attributes() failed\n");
1489 channel->dpcon_id = attr.id;
1490 channel->ch_id = attr.qbman_ch_id;
1491 channel->priv = priv;
1496 free_dpcon(priv, channel->dpcon);
1502 static void free_channel(struct dpaa2_eth_priv *priv,
1503 struct dpaa2_eth_channel *channel)
1505 free_dpcon(priv, channel->dpcon);
1509 /* DPIO setup: allocate and configure QBMan channels, setup core affinity
1510 * and register data availability notifications
1512 static int setup_dpio(struct dpaa2_eth_priv *priv)
1514 struct dpaa2_io_notification_ctx *nctx;
1515 struct dpaa2_eth_channel *channel;
1516 struct dpcon_notification_cfg dpcon_notif_cfg;
1517 struct device *dev = priv->net_dev->dev.parent;
1520 /* We want the ability to spread ingress traffic (RX, TX conf) to as
1521 * many cores as possible, so we need one channel for each core
1522 * (unless there's fewer queues than cores, in which case the extra
1523 * channels would be wasted).
1524 * Allocate one channel per core and register it to the core's
1525 * affine DPIO. If not enough channels are available for all cores
1526 * or if some cores don't have an affine DPIO, there will be no
1527 * ingress frame processing on those cores.
1529 cpumask_clear(&priv->dpio_cpumask);
1530 for_each_online_cpu(i) {
1531 /* Try to allocate a channel */
1532 channel = alloc_channel(priv);
1535 "No affine channel for cpu %d and above\n", i);
1540 priv->channel[priv->num_channels] = channel;
1542 nctx = &channel->nctx;
1545 nctx->id = channel->ch_id;
1546 nctx->desired_cpu = i;
1548 /* Register the new context */
1549 err = dpaa2_io_service_register(NULL, nctx);
1551 dev_dbg(dev, "No affine DPIO for cpu %d\n", i);
1552 /* If no affine DPIO for this core, there's probably
1553 * none available for next cores either. Signal we want
1554 * to retry later, in case the DPIO devices weren't
1557 err = -EPROBE_DEFER;
1558 goto err_service_reg;
1561 /* Register DPCON notification with MC */
1562 dpcon_notif_cfg.dpio_id = nctx->dpio_id;
1563 dpcon_notif_cfg.priority = 0;
1564 dpcon_notif_cfg.user_ctx = nctx->qman64;
1565 err = dpcon_set_notification(priv->mc_io, 0,
1566 channel->dpcon->mc_handle,
1569 dev_err(dev, "dpcon_set_notification failed()\n");
1573 /* If we managed to allocate a channel and also found an affine
1574 * DPIO for this core, add it to the final mask
1576 cpumask_set_cpu(i, &priv->dpio_cpumask);
1577 priv->num_channels++;
1579 /* Stop if we already have enough channels to accommodate all
1580 * RX and TX conf queues
1582 if (priv->num_channels == dpaa2_eth_queue_count(priv))
1589 dpaa2_io_service_deregister(NULL, nctx);
1591 free_channel(priv, channel);
1593 if (cpumask_empty(&priv->dpio_cpumask)) {
1594 dev_err(dev, "No cpu with an affine DPIO/DPCON\n");
1598 dev_info(dev, "Cores %*pbl available for processing ingress traffic\n",
1599 cpumask_pr_args(&priv->dpio_cpumask));
1604 static void free_dpio(struct dpaa2_eth_priv *priv)
1607 struct dpaa2_eth_channel *ch;
1609 /* deregister CDAN notifications and free channels */
1610 for (i = 0; i < priv->num_channels; i++) {
1611 ch = priv->channel[i];
1612 dpaa2_io_service_deregister(NULL, &ch->nctx);
1613 free_channel(priv, ch);
1617 static struct dpaa2_eth_channel *get_affine_channel(struct dpaa2_eth_priv *priv,
1620 struct device *dev = priv->net_dev->dev.parent;
1623 for (i = 0; i < priv->num_channels; i++)
1624 if (priv->channel[i]->nctx.desired_cpu == cpu)
1625 return priv->channel[i];
1627 /* We should never get here. Issue a warning and return
1628 * the first channel, because it's still better than nothing
1630 dev_warn(dev, "No affine channel found for cpu %d\n", cpu);
1632 return priv->channel[0];
1635 static void set_fq_affinity(struct dpaa2_eth_priv *priv)
1637 struct device *dev = priv->net_dev->dev.parent;
1638 struct dpaa2_eth_fq *fq;
1639 int rx_cpu, txc_cpu;
1642 /* For each FQ, pick one channel/CPU to deliver frames to.
1643 * This may well change at runtime, either through irqbalance or
1644 * through direct user intervention.
1646 rx_cpu = txc_cpu = cpumask_first(&priv->dpio_cpumask);
1648 for (i = 0; i < priv->num_fqs; i++) {
1652 fq->target_cpu = rx_cpu;
1653 rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
1654 if (rx_cpu >= nr_cpu_ids)
1655 rx_cpu = cpumask_first(&priv->dpio_cpumask);
1657 case DPAA2_TX_CONF_FQ:
1658 fq->target_cpu = txc_cpu;
1659 txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask);
1660 if (txc_cpu >= nr_cpu_ids)
1661 txc_cpu = cpumask_first(&priv->dpio_cpumask);
1664 dev_err(dev, "Unknown FQ type: %d\n", fq->type);
1666 fq->channel = get_affine_channel(priv, fq->target_cpu);
1670 static void setup_fqs(struct dpaa2_eth_priv *priv)
1674 /* We have one TxConf FQ per Tx flow.
1675 * The number of Tx and Rx queues is the same.
1676 * Tx queues come first in the fq array.
1678 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
1679 priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ;
1680 priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf;
1681 priv->fq[priv->num_fqs++].flowid = (u16)i;
1684 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
1685 priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
1686 priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
1687 priv->fq[priv->num_fqs++].flowid = (u16)i;
1690 /* For each FQ, decide on which core to process incoming frames */
1691 set_fq_affinity(priv);
1694 /* Allocate and configure one buffer pool for each interface */
1695 static int setup_dpbp(struct dpaa2_eth_priv *priv)
1698 struct fsl_mc_device *dpbp_dev;
1699 struct device *dev = priv->net_dev->dev.parent;
1700 struct dpbp_attr dpbp_attrs;
1702 err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP,
1705 dev_err(dev, "DPBP device allocation failed\n");
1709 priv->dpbp_dev = dpbp_dev;
1711 err = dpbp_open(priv->mc_io, 0, priv->dpbp_dev->obj_desc.id,
1712 &dpbp_dev->mc_handle);
1714 dev_err(dev, "dpbp_open() failed\n");
1718 err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle);
1720 dev_err(dev, "dpbp_reset() failed\n");
1724 err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle);
1726 dev_err(dev, "dpbp_enable() failed\n");
1730 err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle,
1733 dev_err(dev, "dpbp_get_attributes() failed\n");
1736 priv->bpid = dpbp_attrs.bpid;
1741 dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle);
1744 dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle);
1746 fsl_mc_object_free(dpbp_dev);
1751 static void free_dpbp(struct dpaa2_eth_priv *priv)
1754 dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
1755 dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
1756 fsl_mc_object_free(priv->dpbp_dev);
1759 /* Configure the DPNI object this interface is associated with */
1760 static int setup_dpni(struct fsl_mc_device *ls_dev)
1762 struct device *dev = &ls_dev->dev;
1763 struct dpaa2_eth_priv *priv;
1764 struct net_device *net_dev;
1765 struct dpni_buffer_layout buf_layout = {0};
1768 net_dev = dev_get_drvdata(dev);
1769 priv = netdev_priv(net_dev);
1771 /* get a handle for the DPNI object */
1772 err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token);
1774 dev_err(dev, "dpni_open() failed\n");
1778 ls_dev->mc_io = priv->mc_io;
1779 ls_dev->mc_handle = priv->mc_token;
1781 err = dpni_reset(priv->mc_io, 0, priv->mc_token);
1783 dev_err(dev, "dpni_reset() failed\n");
1787 err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token,
1790 dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err);
1794 /* Configure buffer layouts */
1796 buf_layout.pass_parser_result = true;
1797 buf_layout.pass_frame_status = true;
1798 buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
1799 buf_layout.data_align = DPAA2_ETH_RX_BUF_ALIGN;
1800 buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
1801 DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
1802 DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
1803 DPNI_BUF_LAYOUT_OPT_DATA_ALIGN;
1804 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
1805 DPNI_QUEUE_RX, &buf_layout);
1807 dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
1808 goto err_buf_layout;
1812 buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
1813 DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
1814 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
1815 DPNI_QUEUE_TX, &buf_layout);
1817 dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
1818 goto err_buf_layout;
1821 /* tx-confirm buffer */
1822 buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
1823 err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
1824 DPNI_QUEUE_TX_CONFIRM, &buf_layout);
1826 dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
1827 goto err_buf_layout;
1830 /* Now that we've set our tx buffer layout, retrieve the minimum
1831 * required tx data offset.
1833 err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
1834 &priv->tx_data_offset);
1836 dev_err(dev, "dpni_get_tx_data_offset() failed\n");
1837 goto err_data_offset;
1840 if ((priv->tx_data_offset % 64) != 0)
1841 dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
1842 priv->tx_data_offset);
1844 /* Accommodate software annotation space (SWA) */
1845 priv->tx_data_offset += DPAA2_ETH_SWA_SIZE;
1853 dpni_close(priv->mc_io, 0, priv->mc_token);
1858 static void free_dpni(struct dpaa2_eth_priv *priv)
1862 err = dpni_reset(priv->mc_io, 0, priv->mc_token);
1864 netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n",
1867 dpni_close(priv->mc_io, 0, priv->mc_token);
1870 static int setup_rx_flow(struct dpaa2_eth_priv *priv,
1871 struct dpaa2_eth_fq *fq)
1873 struct device *dev = priv->net_dev->dev.parent;
1874 struct dpni_queue queue;
1875 struct dpni_queue_id qid;
1876 struct dpni_taildrop td;
1879 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
1880 DPNI_QUEUE_RX, 0, fq->flowid, &queue, &qid);
1882 dev_err(dev, "dpni_get_queue(RX) failed\n");
1886 fq->fqid = qid.fqid;
1888 queue.destination.id = fq->channel->dpcon_id;
1889 queue.destination.type = DPNI_DEST_DPCON;
1890 queue.destination.priority = 1;
1891 queue.user_context = (u64)(uintptr_t)fq;
1892 err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
1893 DPNI_QUEUE_RX, 0, fq->flowid,
1894 DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
1897 dev_err(dev, "dpni_set_queue(RX) failed\n");
1902 td.threshold = DPAA2_ETH_TAILDROP_THRESH;
1903 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token, DPNI_CP_QUEUE,
1904 DPNI_QUEUE_RX, 0, fq->flowid, &td);
1906 dev_err(dev, "dpni_set_threshold() failed\n");
1913 static int setup_tx_flow(struct dpaa2_eth_priv *priv,
1914 struct dpaa2_eth_fq *fq)
1916 struct device *dev = priv->net_dev->dev.parent;
1917 struct dpni_queue queue;
1918 struct dpni_queue_id qid;
1921 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
1922 DPNI_QUEUE_TX, 0, fq->flowid, &queue, &qid);
1924 dev_err(dev, "dpni_get_queue(TX) failed\n");
1928 fq->tx_qdbin = qid.qdbin;
1930 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
1931 DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
1934 dev_err(dev, "dpni_get_queue(TX_CONF) failed\n");
1938 fq->fqid = qid.fqid;
1940 queue.destination.id = fq->channel->dpcon_id;
1941 queue.destination.type = DPNI_DEST_DPCON;
1942 queue.destination.priority = 0;
1943 queue.user_context = (u64)(uintptr_t)fq;
1944 err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
1945 DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
1946 DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
1949 dev_err(dev, "dpni_set_queue(TX_CONF) failed\n");
1956 /* Hash key is a 5-tuple: IPsrc, IPdst, IPnextproto, L4src, L4dst */
1957 static const struct dpaa2_eth_hash_fields hash_fields[] = {
1960 .rxnfc_field = RXH_IP_SRC,
1961 .cls_prot = NET_PROT_IP,
1962 .cls_field = NH_FLD_IP_SRC,
1965 .rxnfc_field = RXH_IP_DST,
1966 .cls_prot = NET_PROT_IP,
1967 .cls_field = NH_FLD_IP_DST,
1970 .rxnfc_field = RXH_L3_PROTO,
1971 .cls_prot = NET_PROT_IP,
1972 .cls_field = NH_FLD_IP_PROTO,
1975 /* Using UDP ports, this is functionally equivalent to raw
1976 * byte pairs from L4 header.
1978 .rxnfc_field = RXH_L4_B_0_1,
1979 .cls_prot = NET_PROT_UDP,
1980 .cls_field = NH_FLD_UDP_PORT_SRC,
1983 .rxnfc_field = RXH_L4_B_2_3,
1984 .cls_prot = NET_PROT_UDP,
1985 .cls_field = NH_FLD_UDP_PORT_DST,
1990 /* Set RX hash options
1991 * flags is a combination of RXH_ bits
1993 static int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags)
1995 struct device *dev = net_dev->dev.parent;
1996 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1997 struct dpkg_profile_cfg cls_cfg;
1998 struct dpni_rx_tc_dist_cfg dist_cfg;
2003 if (!dpaa2_eth_hash_enabled(priv)) {
2004 dev_dbg(dev, "Hashing support is not enabled\n");
2008 memset(&cls_cfg, 0, sizeof(cls_cfg));
2010 for (i = 0; i < ARRAY_SIZE(hash_fields); i++) {
2011 struct dpkg_extract *key =
2012 &cls_cfg.extracts[cls_cfg.num_extracts];
2014 if (!(flags & hash_fields[i].rxnfc_field))
2017 if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) {
2018 dev_err(dev, "error adding key extraction rule, too many rules?\n");
2022 key->type = DPKG_EXTRACT_FROM_HDR;
2023 key->extract.from_hdr.prot = hash_fields[i].cls_prot;
2024 key->extract.from_hdr.type = DPKG_FULL_FIELD;
2025 key->extract.from_hdr.field = hash_fields[i].cls_field;
2026 cls_cfg.num_extracts++;
2028 priv->rx_hash_fields |= hash_fields[i].rxnfc_field;
2031 dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
2035 err = dpni_prepare_key_cfg(&cls_cfg, dma_mem);
2037 dev_err(dev, "dpni_prepare_key_cfg error %d\n", err);
2041 memset(&dist_cfg, 0, sizeof(dist_cfg));
2043 /* Prepare for setting the rx dist */
2044 dist_cfg.key_cfg_iova = dma_map_single(dev, dma_mem,
2045 DPAA2_CLASSIFIER_DMA_SIZE,
2047 if (dma_mapping_error(dev, dist_cfg.key_cfg_iova)) {
2048 dev_err(dev, "DMA mapping failed\n");
2053 dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
2054 dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
2056 err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token, 0, &dist_cfg);
2057 dma_unmap_single(dev, dist_cfg.key_cfg_iova,
2058 DPAA2_CLASSIFIER_DMA_SIZE, DMA_TO_DEVICE);
2060 dev_err(dev, "dpni_set_rx_tc_dist() error %d\n", err);
2068 /* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs,
2069 * frame queues and channels
2071 static int bind_dpni(struct dpaa2_eth_priv *priv)
2073 struct net_device *net_dev = priv->net_dev;
2074 struct device *dev = net_dev->dev.parent;
2075 struct dpni_pools_cfg pools_params;
2076 struct dpni_error_cfg err_cfg;
2080 pools_params.num_dpbp = 1;
2081 pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id;
2082 pools_params.pools[0].backup_pool = 0;
2083 pools_params.pools[0].buffer_size = DPAA2_ETH_RX_BUF_SIZE;
2084 err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
2086 dev_err(dev, "dpni_set_pools() failed\n");
2090 /* have the interface implicitly distribute traffic based on supported
2093 err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_SUPPORTED);
2095 netdev_err(net_dev, "Failed to configure hashing\n");
2097 /* Configure handling of error frames */
2098 err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
2099 err_cfg.set_frame_annotation = 1;
2100 err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
2101 err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
2104 dev_err(dev, "dpni_set_errors_behavior failed\n");
2108 /* Configure Rx and Tx conf queues to generate CDANs */
2109 for (i = 0; i < priv->num_fqs; i++) {
2110 switch (priv->fq[i].type) {
2112 err = setup_rx_flow(priv, &priv->fq[i]);
2114 case DPAA2_TX_CONF_FQ:
2115 err = setup_tx_flow(priv, &priv->fq[i]);
2118 dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
2125 err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token,
2126 DPNI_QUEUE_TX, &priv->tx_qdid);
2128 dev_err(dev, "dpni_get_qdid() failed\n");
2135 /* Allocate rings for storing incoming frame descriptors */
2136 static int alloc_rings(struct dpaa2_eth_priv *priv)
2138 struct net_device *net_dev = priv->net_dev;
2139 struct device *dev = net_dev->dev.parent;
2142 for (i = 0; i < priv->num_channels; i++) {
2143 priv->channel[i]->store =
2144 dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev);
2145 if (!priv->channel[i]->store) {
2146 netdev_err(net_dev, "dpaa2_io_store_create() failed\n");
2154 for (i = 0; i < priv->num_channels; i++) {
2155 if (!priv->channel[i]->store)
2157 dpaa2_io_store_destroy(priv->channel[i]->store);
2163 static void free_rings(struct dpaa2_eth_priv *priv)
2167 for (i = 0; i < priv->num_channels; i++)
2168 dpaa2_io_store_destroy(priv->channel[i]->store);
2171 static int set_mac_addr(struct dpaa2_eth_priv *priv)
2173 struct net_device *net_dev = priv->net_dev;
2174 struct device *dev = net_dev->dev.parent;
2175 u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN];
2178 /* Get firmware address, if any */
2179 err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr);
2181 dev_err(dev, "dpni_get_port_mac_addr() failed\n");
2185 /* Get DPNI attributes address, if any */
2186 err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
2189 dev_err(dev, "dpni_get_primary_mac_addr() failed\n");
2193 /* First check if firmware has any address configured by bootloader */
2194 if (!is_zero_ether_addr(mac_addr)) {
2195 /* If the DPMAC addr != DPNI addr, update it */
2196 if (!ether_addr_equal(mac_addr, dpni_mac_addr)) {
2197 err = dpni_set_primary_mac_addr(priv->mc_io, 0,
2201 dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
2205 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
2206 } else if (is_zero_ether_addr(dpni_mac_addr)) {
2207 /* No MAC address configured, fill in net_dev->dev_addr
2210 eth_hw_addr_random(net_dev);
2211 dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n");
2213 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
2216 dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
2220 /* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all
2221 * practical purposes, this will be our "permanent" mac address,
2222 * at least until the next reboot. This move will also permit
2223 * register_netdevice() to properly fill up net_dev->perm_addr.
2225 net_dev->addr_assign_type = NET_ADDR_PERM;
2227 /* NET_ADDR_PERM is default, all we have to do is
2228 * fill in the device addr.
2230 memcpy(net_dev->dev_addr, dpni_mac_addr, net_dev->addr_len);
2236 static int netdev_init(struct net_device *net_dev)
2238 struct device *dev = net_dev->dev.parent;
2239 struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2240 u8 bcast_addr[ETH_ALEN];
2244 net_dev->netdev_ops = &dpaa2_eth_ops;
2246 err = set_mac_addr(priv);
2250 /* Explicitly add the broadcast address to the MAC filtering table */
2251 eth_broadcast_addr(bcast_addr);
2252 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr);
2254 dev_err(dev, "dpni_add_mac_addr() failed\n");
2258 /* Reserve enough space to align buffer as per hardware requirement;
2259 * NOTE: priv->tx_data_offset MUST be initialized at this point.
2261 net_dev->needed_headroom = DPAA2_ETH_NEEDED_HEADROOM(priv);
2263 /* Set MTU limits */
2264 net_dev->min_mtu = 68;
2265 net_dev->max_mtu = DPAA2_ETH_MAX_MTU;
2267 /* Set actual number of queues in the net device */
2268 num_queues = dpaa2_eth_queue_count(priv);
2269 err = netif_set_real_num_tx_queues(net_dev, num_queues);
2271 dev_err(dev, "netif_set_real_num_tx_queues() failed\n");
2274 err = netif_set_real_num_rx_queues(net_dev, num_queues);
2276 dev_err(dev, "netif_set_real_num_rx_queues() failed\n");
2280 /* Our .ndo_init will be called herein */
2281 err = register_netdev(net_dev);
2283 dev_err(dev, "register_netdev() failed\n");
2290 static int poll_link_state(void *arg)
2292 struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg;
2295 while (!kthread_should_stop()) {
2296 err = link_state_update(priv);
2300 msleep(DPAA2_ETH_LINK_STATE_REFRESH);
2306 static irqreturn_t dpni_irq0_handler(int irq_num, void *arg)
2308 return IRQ_WAKE_THREAD;
2311 static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg)
2313 u32 status = 0, clear = 0;
2314 struct device *dev = (struct device *)arg;
2315 struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev);
2316 struct net_device *net_dev = dev_get_drvdata(dev);
2319 err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
2320 DPNI_IRQ_INDEX, &status);
2321 if (unlikely(err)) {
2322 netdev_err(net_dev, "Can't get irq status (err %d)\n", err);
2327 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
2328 clear |= DPNI_IRQ_EVENT_LINK_CHANGED;
2329 link_state_update(netdev_priv(net_dev));
2333 dpni_clear_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
2334 DPNI_IRQ_INDEX, clear);
2338 static int setup_irqs(struct fsl_mc_device *ls_dev)
2341 struct fsl_mc_device_irq *irq;
2343 err = fsl_mc_allocate_irqs(ls_dev);
2345 dev_err(&ls_dev->dev, "MC irqs allocation failed\n");
2349 irq = ls_dev->irqs[0];
2350 err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq,
2352 dpni_irq0_handler_thread,
2353 IRQF_NO_SUSPEND | IRQF_ONESHOT,
2354 dev_name(&ls_dev->dev), &ls_dev->dev);
2356 dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err);
2360 err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle,
2361 DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED);
2363 dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err);
2367 err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle,
2370 dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err);
2377 devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev);
2379 fsl_mc_free_irqs(ls_dev);
2384 static void add_ch_napi(struct dpaa2_eth_priv *priv)
2387 struct dpaa2_eth_channel *ch;
2389 for (i = 0; i < priv->num_channels; i++) {
2390 ch = priv->channel[i];
2391 /* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */
2392 netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll,
2397 static void del_ch_napi(struct dpaa2_eth_priv *priv)
2400 struct dpaa2_eth_channel *ch;
2402 for (i = 0; i < priv->num_channels; i++) {
2403 ch = priv->channel[i];
2404 netif_napi_del(&ch->napi);
2408 static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
2411 struct net_device *net_dev = NULL;
2412 struct dpaa2_eth_priv *priv = NULL;
2415 dev = &dpni_dev->dev;
2418 net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_TX_QUEUES);
2420 dev_err(dev, "alloc_etherdev_mq() failed\n");
2424 SET_NETDEV_DEV(net_dev, dev);
2425 dev_set_drvdata(dev, net_dev);
2427 priv = netdev_priv(net_dev);
2428 priv->net_dev = net_dev;
2430 priv->iommu_domain = iommu_get_domain_for_dev(dev);
2432 /* Obtain a MC portal */
2433 err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
2436 dev_err(dev, "MC portal allocation failed\n");
2437 goto err_portal_alloc;
2440 /* MC objects initialization and configuration */
2441 err = setup_dpni(dpni_dev);
2443 goto err_dpni_setup;
2445 err = setup_dpio(priv);
2447 goto err_dpio_setup;
2451 err = setup_dpbp(priv);
2453 goto err_dpbp_setup;
2455 err = bind_dpni(priv);
2459 /* Add a NAPI context for each channel */
2462 /* Percpu statistics */
2463 priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
2464 if (!priv->percpu_stats) {
2465 dev_err(dev, "alloc_percpu(percpu_stats) failed\n");
2467 goto err_alloc_percpu_stats;
2469 priv->percpu_extras = alloc_percpu(*priv->percpu_extras);
2470 if (!priv->percpu_extras) {
2471 dev_err(dev, "alloc_percpu(percpu_extras) failed\n");
2473 goto err_alloc_percpu_extras;
2476 err = netdev_init(net_dev);
2478 goto err_netdev_init;
2480 /* Configure checksum offload based on current interface flags */
2481 err = set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM));
2485 err = set_tx_csum(priv, !!(net_dev->features &
2486 (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)));
2490 err = alloc_rings(priv);
2492 goto err_alloc_rings;
2494 net_dev->ethtool_ops = &dpaa2_ethtool_ops;
2496 err = setup_irqs(dpni_dev);
2498 netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n");
2499 priv->poll_thread = kthread_run(poll_link_state, priv,
2500 "%s_poll_link", net_dev->name);
2501 if (IS_ERR(priv->poll_thread)) {
2502 netdev_err(net_dev, "Error starting polling thread\n");
2503 goto err_poll_thread;
2505 priv->do_link_poll = true;
2508 dev_info(dev, "Probed interface %s\n", net_dev->name);
2515 unregister_netdev(net_dev);
2517 free_percpu(priv->percpu_extras);
2518 err_alloc_percpu_extras:
2519 free_percpu(priv->percpu_stats);
2520 err_alloc_percpu_stats:
2529 fsl_mc_portal_free(priv->mc_io);
2531 dev_set_drvdata(dev, NULL);
2532 free_netdev(net_dev);
2537 static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev)
2540 struct net_device *net_dev;
2541 struct dpaa2_eth_priv *priv;
2544 net_dev = dev_get_drvdata(dev);
2545 priv = netdev_priv(net_dev);
2547 unregister_netdev(net_dev);
2548 dev_info(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
2550 if (priv->do_link_poll)
2551 kthread_stop(priv->poll_thread);
2553 fsl_mc_free_irqs(ls_dev);
2556 free_percpu(priv->percpu_stats);
2557 free_percpu(priv->percpu_extras);
2564 fsl_mc_portal_free(priv->mc_io);
2566 dev_set_drvdata(dev, NULL);
2567 free_netdev(net_dev);
2572 static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = {
2574 .vendor = FSL_MC_VENDOR_FREESCALE,
2579 MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table);
2581 static struct fsl_mc_driver dpaa2_eth_driver = {
2583 .name = KBUILD_MODNAME,
2584 .owner = THIS_MODULE,
2586 .probe = dpaa2_eth_probe,
2587 .remove = dpaa2_eth_remove,
2588 .match_id_table = dpaa2_eth_match_id_table
2591 module_fsl_mc_driver(dpaa2_eth_driver);