4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
27 #define pr_fmt(fmt) "%s: " fmt, __func__
29 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
31 #define div_mask(d) ((1 << ((d)->width)) - 1)
33 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
35 unsigned int maxdiv = 0;
36 const struct clk_div_table *clkt;
38 for (clkt = table; clkt->div; clkt++)
39 if (clkt->div > maxdiv)
44 static unsigned int _get_maxdiv(struct clk_divider *divider)
46 if (divider->flags & CLK_DIVIDER_ONE_BASED)
47 return div_mask(divider);
48 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
49 return 1 << div_mask(divider);
51 return _get_table_maxdiv(divider->table);
52 return div_mask(divider) + 1;
55 static unsigned int _get_table_div(const struct clk_div_table *table,
58 const struct clk_div_table *clkt;
60 for (clkt = table; clkt->div; clkt++)
66 static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
68 if (divider->flags & CLK_DIVIDER_ONE_BASED)
70 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
73 return _get_table_div(divider->table, val);
77 static unsigned int _get_table_val(const struct clk_div_table *table,
80 const struct clk_div_table *clkt;
82 for (clkt = table; clkt->div; clkt++)
88 static unsigned int _get_val(struct clk_divider *divider, u8 div)
90 if (divider->flags & CLK_DIVIDER_ONE_BASED)
92 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
95 return _get_table_val(divider->table, div);
99 static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
100 unsigned long parent_rate)
102 struct clk_divider *divider = to_clk_divider(hw);
103 unsigned int div, val;
105 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
106 val &= div_mask(divider);
108 div = _get_div(divider, val);
110 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
111 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
112 clk_hw_get_name(hw));
116 return DIV_ROUND_UP(parent_rate, div);
120 * The reverse of DIV_ROUND_UP: The maximum number which
123 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
125 static bool _is_valid_table_div(const struct clk_div_table *table,
128 const struct clk_div_table *clkt;
130 for (clkt = table; clkt->div; clkt++)
131 if (clkt->div == div)
136 static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
138 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
139 return is_power_of_2(div);
141 return _is_valid_table_div(divider->table, div);
145 static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
146 unsigned long *best_parent_rate)
148 struct clk_divider *divider = to_clk_divider(hw);
150 unsigned long parent_rate, best = 0, now, maxdiv;
151 unsigned long parent_rate_saved = *best_parent_rate;
156 maxdiv = _get_maxdiv(divider);
158 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
159 parent_rate = *best_parent_rate;
160 bestdiv = DIV_ROUND_UP(parent_rate, rate);
161 bestdiv = bestdiv == 0 ? 1 : bestdiv;
162 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
167 * The maximum divider we can use without overflowing
168 * unsigned long in rate * i below
170 maxdiv = min(ULONG_MAX / rate, maxdiv);
172 for (i = 1; i <= maxdiv; i++) {
173 if (!_is_valid_div(divider, i))
175 if (rate * i == parent_rate_saved) {
177 * It's the most ideal case if the requested rate can be
178 * divided from parent clock without needing to change
179 * parent rate, so return the divider immediately.
181 *best_parent_rate = parent_rate_saved;
184 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
185 MULT_ROUND_UP(rate, i));
186 now = DIV_ROUND_UP(parent_rate, i);
187 if (now <= rate && now > best) {
190 *best_parent_rate = parent_rate;
195 bestdiv = _get_maxdiv(divider);
197 clk_hw_round_rate(clk_hw_get_parent(hw), 1);
203 static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
204 unsigned long *prate)
207 div = ti_clk_divider_bestdiv(hw, rate, prate);
209 return DIV_ROUND_UP(*prate, div);
212 static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
213 unsigned long parent_rate)
215 struct clk_divider *divider;
216 unsigned int div, value;
222 divider = to_clk_divider(hw);
224 div = DIV_ROUND_UP(parent_rate, rate);
225 value = _get_val(divider, div);
227 if (value > div_mask(divider))
228 value = div_mask(divider);
230 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
231 val = div_mask(divider) << (divider->shift + 16);
233 val = ti_clk_ll_ops->clk_readl(divider->reg);
234 val &= ~(div_mask(divider) << divider->shift);
236 val |= value << divider->shift;
237 ti_clk_ll_ops->clk_writel(val, divider->reg);
242 const struct clk_ops ti_clk_divider_ops = {
243 .recalc_rate = ti_clk_divider_recalc_rate,
244 .round_rate = ti_clk_divider_round_rate,
245 .set_rate = ti_clk_divider_set_rate,
248 static struct clk *_register_divider(struct device *dev, const char *name,
249 const char *parent_name,
250 unsigned long flags, void __iomem *reg,
251 u8 shift, u8 width, u8 clk_divider_flags,
252 const struct clk_div_table *table)
254 struct clk_divider *div;
256 struct clk_init_data init;
258 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
259 if (width + shift > 16) {
260 pr_warn("divider value exceeds LOWORD field\n");
261 return ERR_PTR(-EINVAL);
265 /* allocate the divider */
266 div = kzalloc(sizeof(*div), GFP_KERNEL);
268 pr_err("%s: could not allocate divider clk\n", __func__);
269 return ERR_PTR(-ENOMEM);
273 init.ops = &ti_clk_divider_ops;
274 init.flags = flags | CLK_IS_BASIC;
275 init.parent_names = (parent_name ? &parent_name : NULL);
276 init.num_parents = (parent_name ? 1 : 0);
278 /* struct clk_divider assignments */
282 div->flags = clk_divider_flags;
283 div->hw.init = &init;
286 /* register the clock */
287 clk = clk_register(dev, &div->hw);
295 static struct clk_div_table *
296 _get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
299 struct clk_div_table *table;
305 if (!setup->num_dividers) {
306 /* Clk divider table not provided, determine min/max divs */
307 flags = setup->flags;
309 if (flags & CLKF_INDEX_STARTS_AT_ONE)
316 while (div < setup->max_div) {
317 if (flags & CLKF_INDEX_POWER_OF_TWO)
329 for (i = 0; i < setup->num_dividers; i++)
330 if (setup->dividers[i])
333 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
335 return ERR_PTR(-ENOMEM);
340 for (i = 0; i < setup->num_dividers; i++)
341 if (setup->dividers[i]) {
342 table[valid_div].div = setup->dividers[i];
343 table[valid_div].val = i;
348 *width = fls(*width);
353 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
355 struct clk_divider *div;
356 struct clk_omap_reg *reg;
361 div = kzalloc(sizeof(*div), GFP_KERNEL);
363 return ERR_PTR(-ENOMEM);
365 reg = (struct clk_omap_reg *)&div->reg;
366 reg->index = setup->module;
367 reg->offset = setup->reg;
369 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
370 div->flags |= CLK_DIVIDER_ONE_BASED;
372 if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
373 div->flags |= CLK_DIVIDER_POWER_OF_TWO;
375 div->table = _get_div_table_from_setup(setup, &div->width);
377 div->shift = setup->bit_shift;
382 struct clk *ti_clk_register_divider(struct ti_clk *setup)
384 struct ti_clk_divider *div;
385 struct clk_omap_reg *reg_setup;
390 struct clk_div_table *table;
395 reg_setup = (struct clk_omap_reg *)®
397 reg_setup->index = div->module;
398 reg_setup->offset = div->reg;
400 if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
401 div_flags |= CLK_DIVIDER_ONE_BASED;
403 if (div->flags & CLKF_INDEX_POWER_OF_TWO)
404 div_flags |= CLK_DIVIDER_POWER_OF_TWO;
406 if (div->flags & CLKF_SET_RATE_PARENT)
407 flags |= CLK_SET_RATE_PARENT;
409 table = _get_div_table_from_setup(div, &width);
411 return (struct clk *)table;
413 clk = _register_divider(NULL, setup->name, div->parent,
414 flags, (void __iomem *)reg, div->bit_shift,
415 width, div_flags, table);
423 static struct clk_div_table *
424 __init ti_clk_get_div_table(struct device_node *node)
426 struct clk_div_table *table;
427 const __be32 *divspec;
433 divspec = of_get_property(node, "ti,dividers", &num_div);
442 /* Determine required size for divider table */
443 for (i = 0; i < num_div; i++) {
444 of_property_read_u32_index(node, "ti,dividers", i, &val);
450 pr_err("no valid dividers for %s table\n", node->name);
451 return ERR_PTR(-EINVAL);
454 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
457 return ERR_PTR(-ENOMEM);
461 for (i = 0; i < num_div; i++) {
462 of_property_read_u32_index(node, "ti,dividers", i, &val);
464 table[valid_div].div = val;
465 table[valid_div].val = i;
473 static int _get_divider_width(struct device_node *node,
474 const struct clk_div_table *table,
483 /* Clk divider table not provided, determine min/max divs */
484 if (of_property_read_u32(node, "ti,min-div", &min_div))
487 if (of_property_read_u32(node, "ti,max-div", &max_div)) {
488 pr_err("no max-div for %s!\n", node->name);
492 /* Determine bit width for the field */
493 if (flags & CLK_DIVIDER_ONE_BASED)
498 while (div < max_div) {
499 if (flags & CLK_DIVIDER_POWER_OF_TWO)
508 while (table[div].div) {
509 val = table[div].val;
517 static int __init ti_clk_divider_populate(struct device_node *node,
518 void __iomem **reg, const struct clk_div_table **table,
519 u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
523 *reg = ti_clk_get_reg_addr(node, 0);
525 return PTR_ERR(*reg);
527 if (!of_property_read_u32(node, "ti,bit-shift", &val))
535 if (of_property_read_bool(node, "ti,index-starts-at-one"))
536 *div_flags |= CLK_DIVIDER_ONE_BASED;
538 if (of_property_read_bool(node, "ti,index-power-of-two"))
539 *div_flags |= CLK_DIVIDER_POWER_OF_TWO;
541 if (of_property_read_bool(node, "ti,set-rate-parent"))
542 *flags |= CLK_SET_RATE_PARENT;
544 *table = ti_clk_get_div_table(node);
547 return PTR_ERR(*table);
549 *width = _get_divider_width(node, *table, *div_flags);
555 * of_ti_divider_clk_setup - Setup function for simple div rate clock
556 * @node: device node for this clock
558 * Sets up a basic divider clock.
560 static void __init of_ti_divider_clk_setup(struct device_node *node)
563 const char *parent_name;
565 u8 clk_divider_flags = 0;
568 const struct clk_div_table *table = NULL;
571 parent_name = of_clk_get_parent_name(node, 0);
573 if (ti_clk_divider_populate(node, ®, &table, &flags,
574 &clk_divider_flags, &width, &shift))
577 clk = _register_divider(NULL, node->name, parent_name, flags, reg,
578 shift, width, clk_divider_flags, table);
581 of_clk_add_provider(node, of_clk_src_simple_get, clk);
582 of_ti_clk_autoidle_setup(node);
589 CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
591 static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
593 struct clk_divider *div;
596 div = kzalloc(sizeof(*div), GFP_KERNEL);
600 if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
601 &div->flags, &div->width, &div->shift) < 0)
604 if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
611 CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
612 of_ti_composite_divider_clk_setup);