display/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <drm/drm_fourcc.h>
  42
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "i915_vgpu.h"
  46 #include "intel_display_types.h"
  47 #include "intel_fbc.h"
  48 #include "intel_frontbuffer.h"
  49
  50 /*
  51  * For SKL+, the plane source size used by the hardware is based on the value we
  52  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  53  * we wrote to PIPESRC.
  54  */
  55 static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
  56                                             int *width, int *height)
  57 {
  58         if (width)
  59                 *width = cache->plane.src_w;
  60         if (height)
  61                 *height = cache->plane.src_h;
  62 }
  63
  64 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  65                                         const struct intel_fbc_state_cache *cache)
  66 {
  67         int lines;
  68
  69         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  70         if (IS_GEN(dev_priv, 7))
  71                 lines = min(lines, 2048);
  72         else if (INTEL_GEN(dev_priv) >= 8)
  73                 lines = min(lines, 2560);
  74
  75         /* Hardware needs the full buffer stride, not just the active area. */
  76         return lines * cache->fb.stride;
  77 }
  78
  79 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  80 {
  81         u32 fbc_ctl;
  82
  83         /* Disable compression */
  84         fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
  85         if ((fbc_ctl & FBC_CTL_EN) == 0)
  86                 return;
  87
  88         fbc_ctl &= ~FBC_CTL_EN;
  89         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
  90
  91         /* Wait for compressing bit to clear */
  92         if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
  93                                     FBC_STAT_COMPRESSING, 10)) {
  94                 drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n");
  95                 return;
  96         }
  97 }
  98
  99 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 100 {
 101         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 102         int cfb_pitch;
 103         int i;
 104         u32 fbc_ctl;
 105
 106         /* Note: fbc.threshold == 1 for i8xx */
 107         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 108         if (params->fb.stride < cfb_pitch)
 109                 cfb_pitch = params->fb.stride;
 110
 111         /* FBC_CTL wants 32B or 64B units */
 112         if (IS_GEN(dev_priv, 2))
 113                 cfb_pitch = (cfb_pitch / 32) - 1;
 114         else
 115                 cfb_pitch = (cfb_pitch / 64) - 1;
 116
 117         /* Clear old tags */
 118         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 119                 intel_de_write(dev_priv, FBC_TAG(i), 0);
 120
 121         if (IS_GEN(dev_priv, 4)) {
 122                 u32 fbc_ctl2;
 123
 124                 /* Set it up... */
 125                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM;
 126                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 127                 if (params->fence_id >= 0)
 128                         fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 129                 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
 130                 intel_de_write(dev_priv, FBC_FENCE_OFF,
 131                                params->fence_y_offset);
 132         }
 133
 134         /* enable it... */
 135         fbc_ctl = FBC_CTL_INTERVAL(params->interval);
 136         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 137         if (IS_I945GM(dev_priv))
 138                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 139         fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff);
 140         if (params->fence_id >= 0)
 141                 fbc_ctl |= FBC_CTL_FENCENO(params->fence_id);
 142         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
 143 }
 144
 145 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 146 {
 147         return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN;
 148 }
 149
 150 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 151 {
 152         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 153         u32 dpfc_ctl;
 154
 155         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 156         if (params->fb.format->cpp[0] == 2)
 157                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 158         else
 159                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 160
 161         if (params->fence_id >= 0) {
 162                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
 163                 intel_de_write(dev_priv, DPFC_FENCE_YOFF,
 164                                params->fence_y_offset);
 165         } else {
 166                 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
 167         }
 168
 169         /* enable it... */
 170         intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 171 }
 172
 173 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 174 {
 175         u32 dpfc_ctl;
 176
 177         /* Disable compression */
 178         dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL);
 179         if (dpfc_ctl & DPFC_CTL_EN) {
 180                 dpfc_ctl &= ~DPFC_CTL_EN;
 181                 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl);
 182         }
 183 }
 184
 185 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 186 {
 187         return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
 188 }
 189
 190 static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
 191 {
 192         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 193         enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
 194
 195         spin_lock_irq(&dev_priv->uncore.lock);
 196         intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
 197                           intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
 198         spin_unlock_irq(&dev_priv->uncore.lock);
 199 }
 200
 201 static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
 202 {
 203         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 204         enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
 205
 206         spin_lock_irq(&dev_priv->uncore.lock);
 207         intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
 208                           intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
 209         spin_unlock_irq(&dev_priv->uncore.lock);
 210 }
 211
 212 /* This function forces a CFB recompression through the nuke operation. */
 213 static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
 214 {
 215         struct intel_fbc *fbc = &dev_priv->fbc;
 216
 217         trace_intel_fbc_nuke(fbc->crtc);
 218
 219         intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
 220         intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
 221 }
 222
 223 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 224 {
 225         if (INTEL_GEN(dev_priv) >= 6)
 226                 snb_fbc_recompress(dev_priv);
 227         else if (INTEL_GEN(dev_priv) >= 4)
 228                 i965_fbc_recompress(dev_priv);
 229         else
 230                 i8xx_fbc_recompress(dev_priv);
 231 }
 232
 233 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 234 {
 235         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 236         u32 dpfc_ctl;
 237         int threshold = dev_priv->fbc.threshold;
 238
 239         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 240         if (params->fb.format->cpp[0] == 2)
 241                 threshold++;
 242
 243         switch (threshold) {
 244         case 4:
 245         case 3:
 246                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 247                 break;
 248         case 2:
 249                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 250                 break;
 251         case 1:
 252                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 253                 break;
 254         }
 255
 256         if (params->fence_id >= 0) {
 257                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 258                 if (IS_GEN(dev_priv, 5))
 259                         dpfc_ctl |= params->fence_id;
 260                 if (IS_GEN(dev_priv, 6)) {
 261                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 262                                        SNB_CPU_FENCE_ENABLE | params->fence_id);
 263                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 264                                        params->fence_y_offset);
 265                 }
 266         } else {
 267                 if (IS_GEN(dev_priv, 6)) {
 268                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 269                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 270                 }
 271         }
 272
 273         intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
 274                        params->fence_y_offset);
 275         /* enable it... */
 276         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 277
 278         intel_fbc_recompress(dev_priv);
 279 }
 280
 281 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 282 {
 283         u32 dpfc_ctl;
 284
 285         /* Disable compression */
 286         dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
 287         if (dpfc_ctl & DPFC_CTL_EN) {
 288                 dpfc_ctl &= ~DPFC_CTL_EN;
 289                 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl);
 290         }
 291 }
 292
 293 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 294 {
 295         return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 296 }
 297
 298 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 299 {
 300         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 301         u32 dpfc_ctl;
 302         int threshold = dev_priv->fbc.threshold;
 303
 304         /* Display WA #0529: skl, kbl, bxt. */
 305         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
 306                 u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
 307
 308                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 309
 310                 if (params->gen9_wa_cfb_stride)
 311                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 312
 313                 intel_de_write(dev_priv, CHICKEN_MISC_4, val);
 314         }
 315
 316         dpfc_ctl = 0;
 317         if (IS_IVYBRIDGE(dev_priv))
 318                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 319
 320         if (params->fb.format->cpp[0] == 2)
 321                 threshold++;
 322
 323         switch (threshold) {
 324         case 4:
 325         case 3:
 326                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 327                 break;
 328         case 2:
 329                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 330                 break;
 331         case 1:
 332                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 333                 break;
 334         }
 335
 336         if (params->fence_id >= 0) {
 337                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 338                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 339                                SNB_CPU_FENCE_ENABLE | params->fence_id);
 340                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 341                                params->fence_y_offset);
 342         } else if (dev_priv->ggtt.num_fences) {
 343                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 344                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 345         }
 346
 347         if (dev_priv->fbc.false_color)
 348                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 349
 350         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 351
 352         intel_fbc_recompress(dev_priv);
 353 }
 354
 355 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 356 {
 357         if (INTEL_GEN(dev_priv) >= 5)
 358                 return ilk_fbc_is_active(dev_priv);
 359         else if (IS_GM45(dev_priv))
 360                 return g4x_fbc_is_active(dev_priv);
 361         else
 362                 return i8xx_fbc_is_active(dev_priv);
 363 }
 364
 365 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 366 {
 367         struct intel_fbc *fbc = &dev_priv->fbc;
 368
 369         trace_intel_fbc_activate(fbc->crtc);
 370
 371         fbc->active = true;
 372         fbc->activated = true;
 373
 374         if (INTEL_GEN(dev_priv) >= 7)
 375                 gen7_fbc_activate(dev_priv);
 376         else if (INTEL_GEN(dev_priv) >= 5)
 377                 ilk_fbc_activate(dev_priv);
 378         else if (IS_GM45(dev_priv))
 379                 g4x_fbc_activate(dev_priv);
 380         else
 381                 i8xx_fbc_activate(dev_priv);
 382 }
 383
 384 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 385 {
 386         struct intel_fbc *fbc = &dev_priv->fbc;
 387
 388         trace_intel_fbc_deactivate(fbc->crtc);
 389
 390         fbc->active = false;
 391
 392         if (INTEL_GEN(dev_priv) >= 5)
 393                 ilk_fbc_deactivate(dev_priv);
 394         else if (IS_GM45(dev_priv))
 395                 g4x_fbc_deactivate(dev_priv);
 396         else
 397                 i8xx_fbc_deactivate(dev_priv);
 398 }
 399
 400 /**
 401  * intel_fbc_is_active - Is FBC active?
 402  * @dev_priv: i915 device instance
 403  *
 404  * This function is used to verify the current state of FBC.
 405  *
 406  * FIXME: This should be tracked in the plane config eventually
 407  * instead of queried at runtime for most callers.
 408  */
 409 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 410 {
 411         return dev_priv->fbc.active;
 412 }
 413
 414 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 415                                  const char *reason)
 416 {
 417         struct intel_fbc *fbc = &dev_priv->fbc;
 418
 419         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
 420
 421         if (fbc->active)
 422                 intel_fbc_hw_deactivate(dev_priv);
 423
 424         fbc->no_fbc_reason = reason;
 425 }
 426
 427 static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
 428 {
 429         if (INTEL_GEN(i915) >= 5 || IS_G4X(i915))
 430                 return BIT_ULL(28);
 431         else
 432                 return BIT_ULL(32);
 433 }
 434
 435 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 436                                       struct drm_mm_node *node,
 437                                       unsigned int size,
 438                                       unsigned int fb_cpp)
 439 {
 440         int compression_threshold = 1;
 441         int ret;
 442         u64 end;
 443
 444         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 445          * reserved range size, so it always assumes the maximum (8mb) is used.
 446          * If we enable FBC using a CFB on that memory range we'll get FIFO
 447          * underruns, even if that range is not reserved by the BIOS. */
 448         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 449                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 450         else
 451                 end = U64_MAX;
 452
 453         end = min(end, intel_fbc_cfb_base_max(dev_priv));
 454
 455         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 456          * code changes, this code needs to change as well.
 457          *
 458          * The enable_fbc code will attempt to use one of our 2 compression
 459          * thresholds, therefore, in that case, we only have 1 resort.
 460          */
 461
 462         /* Try to over-allocate to reduce reallocations and fragmentation. */
 463         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 464                                                    4096, 0, end);
 465         if (ret == 0)
 466                 return compression_threshold;
 467
 468 again:
 469         /* HW's ability to limit the CFB is 1:4 */
 470         if (compression_threshold > 4 ||
 471             (fb_cpp == 2 && compression_threshold == 2))
 472                 return 0;
 473
 474         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 475                                                    4096, 0, end);
 476         if (ret && INTEL_GEN(dev_priv) <= 4) {
 477                 return 0;
 478         } else if (ret) {
 479                 compression_threshold <<= 1;
 480                 goto again;
 481         } else {
 482                 return compression_threshold;
 483         }
 484 }
 485
 486 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
 487                                unsigned int size, unsigned int fb_cpp)
 488 {
 489         struct intel_fbc *fbc = &dev_priv->fbc;
 490         struct drm_mm_node *compressed_llb;
 491         int ret;
 492
 493         drm_WARN_ON(&dev_priv->drm,
 494                     drm_mm_node_allocated(&fbc->compressed_fb));
 495
 496         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 497                                          size, fb_cpp);
 498         if (!ret)
 499                 goto err_llb;
 500         else if (ret > 1) {
 501                 drm_info_once(&dev_priv->drm,
 502                               "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 503         }
 504
 505         fbc->threshold = ret;
 506
 507         if (INTEL_GEN(dev_priv) >= 5)
 508                 intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
 509                                fbc->compressed_fb.start);
 510         else if (IS_GM45(dev_priv)) {
 511                 intel_de_write(dev_priv, DPFC_CB_BASE,
 512                                fbc->compressed_fb.start);
 513         } else {
 514                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 515                 if (!compressed_llb)
 516                         goto err_fb;
 517
 518                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 519                                                   4096, 4096);
 520                 if (ret)
 521                         goto err_fb;
 522
 523                 fbc->compressed_llb = compressed_llb;
 524
 525                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 526                                                  fbc->compressed_fb.start,
 527                                                  U32_MAX));
 528                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 529                                                  fbc->compressed_llb->start,
 530                                                  U32_MAX));
 531                 intel_de_write(dev_priv, FBC_CFB_BASE,
 532                                dev_priv->dsm.start + fbc->compressed_fb.start);
 533                 intel_de_write(dev_priv, FBC_LL_BASE,
 534                                dev_priv->dsm.start + compressed_llb->start);
 535         }
 536
 537         drm_dbg_kms(&dev_priv->drm,
 538                     "reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 539                     fbc->compressed_fb.size, fbc->threshold);
 540
 541         return 0;
 542
 543 err_fb:
 544         kfree(compressed_llb);
 545         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 546 err_llb:
 547         if (drm_mm_initialized(&dev_priv->mm.stolen))
 548                 drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 549         return -ENOSPC;
 550 }
 551
 552 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 553 {
 554         struct intel_fbc *fbc = &dev_priv->fbc;
 555
 556         if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
 557                 return;
 558
 559         if (!drm_mm_node_allocated(&fbc->compressed_fb))
 560                 return;
 561
 562         if (fbc->compressed_llb) {
 563                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 564                 kfree(fbc->compressed_llb);
 565         }
 566
 567         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 568 }
 569
 570 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 571 {
 572         struct intel_fbc *fbc = &dev_priv->fbc;
 573
 574         if (!HAS_FBC(dev_priv))
 575                 return;
 576
 577         mutex_lock(&fbc->lock);
 578         __intel_fbc_cleanup_cfb(dev_priv);
 579         mutex_unlock(&fbc->lock);
 580 }
 581
 582 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 583                             u64 modifier, unsigned int stride)
 584 {
 585         /* This should have been caught earlier. */
 586         if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0))
 587                 return false;
 588
 589         /* Below are the additional FBC restrictions. */
 590         if (stride < 512)
 591                 return false;
 592
 593         if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
 594                 return stride == 4096 || stride == 8192;
 595
 596         if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
 597                 return false;
 598
 599         /* Display WA #1105: skl,bxt,kbl,cfl,glk */
 600         if (IS_GEN(dev_priv, 9) &&
 601             modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
 602                 return false;
 603
 604         if (stride > 16384)
 605                 return false;
 606
 607         return true;
 608 }
 609
 610 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 611                                   u32 pixel_format)
 612 {
 613         switch (pixel_format) {
 614         case DRM_FORMAT_XRGB8888:
 615         case DRM_FORMAT_XBGR8888:
 616                 return true;
 617         case DRM_FORMAT_XRGB1555:
 618         case DRM_FORMAT_RGB565:
 619                 /* 16bpp not supported on gen2 */
 620                 if (IS_GEN(dev_priv, 2))
 621                         return false;
 622                 /* WaFbcOnly1to1Ratio:ctg */
 623                 if (IS_G4X(dev_priv))
 624                         return false;
 625                 return true;
 626         default:
 627                 return false;
 628         }
 629 }
 630
 631 static bool rotation_is_valid(struct drm_i915_private *dev_priv,
 632                               u32 pixel_format, unsigned int rotation)
 633 {
 634         if (INTEL_GEN(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
 635             drm_rotation_90_or_270(rotation))
 636                 return false;
 637         else if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 638                  rotation != DRM_MODE_ROTATE_0)
 639                 return false;
 640
 641         return true;
 642 }
 643
 644 /*
 645  * For some reason, the hardware tracking starts looking at whatever we
 646  * programmed as the display plane base address register. It does not look at
 647  * the X and Y offset registers. That's why we include the src x/y offsets
 648  * instead of just looking at the plane size.
 649  */
 650 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 651 {
 652         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 653         struct intel_fbc *fbc = &dev_priv->fbc;
 654         unsigned int effective_w, effective_h, max_w, max_h;
 655
 656         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 657                 max_w = 5120;
 658                 max_h = 4096;
 659         } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 660                 max_w = 4096;
 661                 max_h = 4096;
 662         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 663                 max_w = 4096;
 664                 max_h = 2048;
 665         } else {
 666                 max_w = 2048;
 667                 max_h = 1536;
 668         }
 669
 670         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 671                                         &effective_h);
 672         effective_w += fbc->state_cache.plane.adjusted_x;
 673         effective_h += fbc->state_cache.plane.adjusted_y;
 674
 675         return effective_w <= max_w && effective_h <= max_h;
 676 }
 677
 678 static bool tiling_is_valid(struct drm_i915_private *dev_priv,
 679                             uint64_t modifier)
 680 {
 681         switch (modifier) {
 682         case DRM_FORMAT_MOD_LINEAR:
 683                 if (INTEL_GEN(dev_priv) >= 9)
 684                         return true;
 685                 return false;
 686         case I915_FORMAT_MOD_X_TILED:
 687         case I915_FORMAT_MOD_Y_TILED:
 688                 return true;
 689         default:
 690                 return false;
 691         }
 692 }
 693
 694 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 695                                          const struct intel_crtc_state *crtc_state,
 696                                          const struct intel_plane_state *plane_state)
 697 {
 698         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 699         struct intel_fbc *fbc = &dev_priv->fbc;
 700         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 701         struct drm_framebuffer *fb = plane_state->hw.fb;
 702
 703         cache->plane.visible = plane_state->uapi.visible;
 704         if (!cache->plane.visible)
 705                 return;
 706
 707         cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
 708         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 709                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 710
 711         cache->plane.rotation = plane_state->hw.rotation;
 712         /*
 713          * Src coordinates are already rotated by 270 degrees for
 714          * the 90/270 degree plane rotation cases (to match the
 715          * GTT mapping), hence no need to account for rotation here.
 716          */
 717         cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 718         cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 719         cache->plane.adjusted_x = plane_state->color_plane[0].x;
 720         cache->plane.adjusted_y = plane_state->color_plane[0].y;
 721
 722         cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 723
 724         cache->fb.format = fb->format;
 725         cache->fb.modifier = fb->modifier;
 726
 727         /* FIXME is this correct? */
 728         cache->fb.stride = plane_state->color_plane[0].stride;
 729         if (drm_rotation_90_or_270(plane_state->hw.rotation))
 730                 cache->fb.stride *= fb->format->cpp[0];
 731
 732         /* FBC1 compression interval: arbitrary choice of 1 second */
 733         cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
 734
 735         cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
 736
 737         drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
 738                     !plane_state->vma->fence);
 739
 740         if (plane_state->flags & PLANE_HAS_FENCE &&
 741             plane_state->vma->fence)
 742                 cache->fence_id = plane_state->vma->fence->id;
 743         else
 744                 cache->fence_id = -1;
 745 }
 746
 747 static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
 748 {
 749         struct intel_fbc *fbc = &dev_priv->fbc;
 750
 751         return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 752                 fbc->compressed_fb.size * fbc->threshold;
 753 }
 754
 755 static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
 756 {
 757         struct intel_fbc *fbc = &dev_priv->fbc;
 758         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 759
 760         if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) &&
 761             cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
 762                 return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
 763         else
 764                 return 0;
 765 }
 766
 767 static bool intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private *dev_priv)
 768 {
 769         struct intel_fbc *fbc = &dev_priv->fbc;
 770
 771         return fbc->params.gen9_wa_cfb_stride != intel_fbc_gen9_wa_cfb_stride(dev_priv);
 772 }
 773
 774 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 775 {
 776         struct intel_fbc *fbc = &dev_priv->fbc;
 777
 778         if (intel_vgpu_active(dev_priv)) {
 779                 fbc->no_fbc_reason = "VGPU is active";
 780                 return false;
 781         }
 782
 783         if (!dev_priv->params.enable_fbc) {
 784                 fbc->no_fbc_reason = "disabled per module param or by default";
 785                 return false;
 786         }
 787
 788         if (fbc->underrun_detected) {
 789                 fbc->no_fbc_reason = "underrun detected";
 790                 return false;
 791         }
 792
 793         return true;
 794 }
 795
 796 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 797 {
 798         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 799         struct intel_fbc *fbc = &dev_priv->fbc;
 800         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 801
 802         if (!intel_fbc_can_enable(dev_priv))
 803                 return false;
 804
 805         if (!cache->plane.visible) {
 806                 fbc->no_fbc_reason = "primary plane not visible";
 807                 return false;
 808         }
 809
 810         /* We don't need to use a state cache here since this information is
 811          * global for all CRTC.
 812          */
 813         if (fbc->underrun_detected) {
 814                 fbc->no_fbc_reason = "underrun detected";
 815                 return false;
 816         }
 817
 818         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 819                 fbc->no_fbc_reason = "incompatible mode";
 820                 return false;
 821         }
 822
 823         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 824                 fbc->no_fbc_reason = "mode too large for compression";
 825                 return false;
 826         }
 827
 828         /* The use of a CPU fence is one of two ways to detect writes by the
 829          * CPU to the scanout and trigger updates to the FBC.
 830          *
 831          * The other method is by software tracking (see
 832          * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
 833          * the current compressed buffer and recompress it.
 834          *
 835          * Note that is possible for a tiled surface to be unmappable (and
 836          * so have no fence associated with it) due to aperture constraints
 837          * at the time of pinning.
 838          *
 839          * FIXME with 90/270 degree rotation we should use the fence on
 840          * the normal GTT view (the rotated view doesn't even have a
 841          * fence). Would need changes to the FBC fence Y offset as well.
 842          * For now this will effectively disable FBC with 90/270 degree
 843          * rotation.
 844          */
 845         if (INTEL_GEN(dev_priv) < 9 && cache->fence_id < 0) {
 846                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 847                 return false;
 848         }
 849
 850         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 851                 fbc->no_fbc_reason = "pixel format is invalid";
 852                 return false;
 853         }
 854
 855         if (!rotation_is_valid(dev_priv, cache->fb.format->format,
 856                                cache->plane.rotation)) {
 857                 fbc->no_fbc_reason = "rotation unsupported";
 858                 return false;
 859         }
 860
 861         if (!tiling_is_valid(dev_priv, cache->fb.modifier)) {
 862                 fbc->no_fbc_reason = "tiling unsupported";
 863                 return false;
 864         }
 865
 866         if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
 867                 fbc->no_fbc_reason = "framebuffer stride not supported";
 868                 return false;
 869         }
 870
 871         if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 872             cache->fb.format->has_alpha) {
 873                 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 874                 return false;
 875         }
 876
 877         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 878         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 879             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 880                 fbc->no_fbc_reason = "pixel rate is too big";
 881                 return false;
 882         }
 883
 884         /* It is possible for the required CFB size change without a
 885          * crtc->disable + crtc->enable since it is possible to change the
 886          * stride without triggering a full modeset. Since we try to
 887          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 888          * if this happens, but if we exceed the current CFB size we'll have to
 889          * disable FBC. Notice that it would be possible to disable FBC, wait
 890          * for a frame, free the stolen node, then try to reenable FBC in case
 891          * we didn't get any invalidate/deactivate calls, but this would require
 892          * a lot of tracking just for a specific case. If we conclude it's an
 893          * important case, we can implement it later. */
 894         if (intel_fbc_cfb_size_changed(dev_priv)) {
 895                 fbc->no_fbc_reason = "CFB requirements changed";
 896                 return false;
 897         }
 898
 899         /*
 900          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 901          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 902          * and screen flicker.
 903          */
 904         if (INTEL_GEN(dev_priv) >= 9 &&
 905             (fbc->state_cache.plane.adjusted_y & 3)) {
 906                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 907                 return false;
 908         }
 909
 910         return true;
 911 }
 912
 913 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 914                                      struct intel_fbc_reg_params *params)
 915 {
 916         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 917         struct intel_fbc *fbc = &dev_priv->fbc;
 918         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 919
 920         /* Since all our fields are integer types, use memset here so the
 921          * comparison function can rely on memcmp because the padding will be
 922          * zero. */
 923         memset(params, 0, sizeof(*params));
 924
 925         params->fence_id = cache->fence_id;
 926         params->fence_y_offset = cache->fence_y_offset;
 927
 928         params->interval = cache->interval;
 929
 930         params->crtc.pipe = crtc->pipe;
 931         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 932
 933         params->fb.format = cache->fb.format;
 934         params->fb.modifier = cache->fb.modifier;
 935         params->fb.stride = cache->fb.stride;
 936
 937         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 938
 939         params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
 940
 941         params->plane_visible = cache->plane.visible;
 942 }
 943
 944 static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
 945 {
 946         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 947         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 948         const struct intel_fbc *fbc = &dev_priv->fbc;
 949         const struct intel_fbc_state_cache *cache = &fbc->state_cache;
 950         const struct intel_fbc_reg_params *params = &fbc->params;
 951
 952         if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
 953                 return false;
 954
 955         if (!params->plane_visible)
 956                 return false;
 957
 958         if (!intel_fbc_can_activate(crtc))
 959                 return false;
 960
 961         if (params->fb.format != cache->fb.format)
 962                 return false;
 963
 964         if (params->fb.modifier != cache->fb.modifier)
 965                 return false;
 966
 967         if (params->fb.stride != cache->fb.stride)
 968                 return false;
 969
 970         if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
 971                 return false;
 972
 973         if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
 974                 return false;
 975
 976         return true;
 977 }
 978
 979 bool intel_fbc_pre_update(struct intel_atomic_state *state,
 980                           struct intel_crtc *crtc)
 981 {
 982         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 983         const struct intel_crtc_state *crtc_state =
 984                 intel_atomic_get_new_crtc_state(state, crtc);
 985         const struct intel_plane_state *plane_state =
 986                 intel_atomic_get_new_plane_state(state, plane);
 987         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 988         struct intel_fbc *fbc = &dev_priv->fbc;
 989         const char *reason = "update pending";
 990         bool need_vblank_wait = false;
 991
 992         if (!plane->has_fbc || !plane_state)
 993                 return need_vblank_wait;
 994
 995         mutex_lock(&fbc->lock);
 996
 997         if (fbc->crtc != crtc)
 998                 goto unlock;
 999
1000         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1001         fbc->flip_pending = true;
1002
1003         if (!intel_fbc_can_flip_nuke(crtc_state)) {
1004                 intel_fbc_deactivate(dev_priv, reason);
1005
1006                 /*
1007                  * Display WA #1198: glk+
1008                  * Need an extra vblank wait between FBC disable and most plane
1009                  * updates. Bspec says this is only needed for plane disable, but
1010                  * that is not true. Touching most plane registers will cause the
1011                  * corruption to appear. Also SKL/derivatives do not seem to be
1012                  * affected.
1013                  *
1014                  * TODO: could optimize this a bit by sampling the frame
1015                  * counter when we disable FBC (if it was already done earlier)
1016                  * and skipping the extra vblank wait before the plane update
1017                  * if at least one frame has already passed.
1018                  */
1019                 if (fbc->activated &&
1020                     (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
1021                         need_vblank_wait = true;
1022                 fbc->activated = false;
1023         }
1024 unlock:
1025         mutex_unlock(&fbc->lock);
1026
1027         return need_vblank_wait;
1028 }
1029
1030 /**
1031  * __intel_fbc_disable - disable FBC
1032  * @dev_priv: i915 device instance
1033  *
1034  * This is the low level function that actually disables FBC. Callers should
1035  * grab the FBC lock.
1036  */
1037 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1038 {
1039         struct intel_fbc *fbc = &dev_priv->fbc;
1040         struct intel_crtc *crtc = fbc->crtc;
1041
1042         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1043         drm_WARN_ON(&dev_priv->drm, !fbc->crtc);
1044         drm_WARN_ON(&dev_priv->drm, fbc->active);
1045
1046         drm_dbg_kms(&dev_priv->drm, "Disabling FBC on pipe %c\n",
1047                     pipe_name(crtc->pipe));
1048
1049         __intel_fbc_cleanup_cfb(dev_priv);
1050
1051         fbc->crtc = NULL;
1052 }
1053
1054 static void __intel_fbc_post_update(struct intel_crtc *crtc)
1055 {
1056         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1057         struct intel_fbc *fbc = &dev_priv->fbc;
1058
1059         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1060
1061         if (fbc->crtc != crtc)
1062                 return;
1063
1064         fbc->flip_pending = false;
1065
1066         if (!dev_priv->params.enable_fbc) {
1067                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
1068                 __intel_fbc_disable(dev_priv);
1069
1070                 return;
1071         }
1072
1073         intel_fbc_get_reg_params(crtc, &fbc->params);
1074
1075         if (!intel_fbc_can_activate(crtc))
1076                 return;
1077
1078         if (!fbc->busy_bits)
1079                 intel_fbc_hw_activate(dev_priv);
1080         else
1081                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1082 }
1083
1084 void intel_fbc_post_update(struct intel_atomic_state *state,
1085                            struct intel_crtc *crtc)
1086 {
1087         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1088         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1089         const struct intel_plane_state *plane_state =
1090                 intel_atomic_get_new_plane_state(state, plane);
1091         struct intel_fbc *fbc = &dev_priv->fbc;
1092
1093         if (!plane->has_fbc || !plane_state)
1094                 return;
1095
1096         mutex_lock(&fbc->lock);
1097         __intel_fbc_post_update(crtc);
1098         mutex_unlock(&fbc->lock);
1099 }
1100
1101 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1102 {
1103         if (fbc->crtc)
1104                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1105         else
1106                 return fbc->possible_framebuffer_bits;
1107 }
1108
1109 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1110                           unsigned int frontbuffer_bits,
1111                           enum fb_op_origin origin)
1112 {
1113         struct intel_fbc *fbc = &dev_priv->fbc;
1114
1115         if (!HAS_FBC(dev_priv))
1116                 return;
1117
1118         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1119                 return;
1120
1121         mutex_lock(&fbc->lock);
1122
1123         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1124
1125         if (fbc->crtc && fbc->busy_bits)
1126                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1127
1128         mutex_unlock(&fbc->lock);
1129 }
1130
1131 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1132                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1133 {
1134         struct intel_fbc *fbc = &dev_priv->fbc;
1135
1136         if (!HAS_FBC(dev_priv))
1137                 return;
1138
1139         /*
1140          * GTT tracking does not nuke the entire cfb
1141          * so don't clear busy_bits set for some other
1142          * reason.
1143          */
1144         if (origin == ORIGIN_GTT)
1145                 return;
1146
1147         mutex_lock(&fbc->lock);
1148
1149         fbc->busy_bits &= ~frontbuffer_bits;
1150
1151         if (origin == ORIGIN_FLIP)
1152                 goto out;
1153
1154         if (!fbc->busy_bits && fbc->crtc &&
1155             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1156                 if (fbc->active)
1157                         intel_fbc_recompress(dev_priv);
1158                 else if (!fbc->flip_pending)
1159                         __intel_fbc_post_update(fbc->crtc);
1160         }
1161
1162 out:
1163         mutex_unlock(&fbc->lock);
1164 }
1165
1166 /**
1167  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1168  * @dev_priv: i915 device instance
1169  * @state: the atomic state structure
1170  *
1171  * This function looks at the proposed state for CRTCs and planes, then chooses
1172  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1173  * true.
1174  *
1175  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1176  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1177  */
1178 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1179                            struct intel_atomic_state *state)
1180 {
1181         struct intel_fbc *fbc = &dev_priv->fbc;
1182         struct intel_plane *plane;
1183         struct intel_plane_state *plane_state;
1184         bool crtc_chosen = false;
1185         int i;
1186
1187         mutex_lock(&fbc->lock);
1188
1189         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1190         if (fbc->crtc &&
1191             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1192                 goto out;
1193
1194         if (!intel_fbc_can_enable(dev_priv))
1195                 goto out;
1196
1197         /* Simply choose the first CRTC that is compatible and has a visible
1198          * plane. We could go for fancier schemes such as checking the plane
1199          * size, but this would just affect the few platforms that don't tie FBC
1200          * to pipe or plane A. */
1201         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1202                 struct intel_crtc_state *crtc_state;
1203                 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1204
1205                 if (!plane->has_fbc)
1206                         continue;
1207
1208                 if (!plane_state->uapi.visible)
1209                         continue;
1210
1211                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1212
1213                 crtc_state->enable_fbc = true;
1214                 crtc_chosen = true;
1215                 break;
1216         }
1217
1218         if (!crtc_chosen)
1219                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1220
1221 out:
1222         mutex_unlock(&fbc->lock);
1223 }
1224
1225 /**
1226  * intel_fbc_enable: tries to enable FBC on the CRTC
1227  * @crtc: the CRTC
1228  * @state: corresponding &drm_crtc_state for @crtc
1229  *
1230  * This function checks if the given CRTC was chosen for FBC, then enables it if
1231  * possible. Notice that it doesn't activate FBC. It is valid to call
1232  * intel_fbc_enable multiple times for the same pipe without an
1233  * intel_fbc_disable in the middle, as long as it is deactivated.
1234  */
1235 void intel_fbc_enable(struct intel_atomic_state *state,
1236                       struct intel_crtc *crtc)
1237 {
1238         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1239         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1240         const struct intel_crtc_state *crtc_state =
1241                 intel_atomic_get_new_crtc_state(state, crtc);
1242         const struct intel_plane_state *plane_state =
1243                 intel_atomic_get_new_plane_state(state, plane);
1244         struct intel_fbc *fbc = &dev_priv->fbc;
1245         struct intel_fbc_state_cache *cache = &fbc->state_cache;
1246
1247         if (!plane->has_fbc || !plane_state)
1248                 return;
1249
1250         mutex_lock(&fbc->lock);
1251
1252         if (fbc->crtc) {
1253                 if (fbc->crtc != crtc ||
1254                     (!intel_fbc_cfb_size_changed(dev_priv) &&
1255                      !intel_fbc_gen9_wa_cfb_stride_changed(dev_priv)))
1256                         goto out;
1257
1258                 __intel_fbc_disable(dev_priv);
1259         }
1260
1261         drm_WARN_ON(&dev_priv->drm, fbc->active);
1262
1263         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1264
1265         /* FIXME crtc_state->enable_fbc lies :( */
1266         if (!cache->plane.visible)
1267                 goto out;
1268
1269         if (intel_fbc_alloc_cfb(dev_priv,
1270                                 intel_fbc_calculate_cfb_size(dev_priv, cache),
1271                                 plane_state->hw.fb->format->cpp[0])) {
1272                 cache->plane.visible = false;
1273                 fbc->no_fbc_reason = "not enough stolen memory";
1274                 goto out;
1275         }
1276
1277         cache->gen9_wa_cfb_stride = intel_fbc_gen9_wa_cfb_stride(dev_priv);
1278
1279         drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
1280                     pipe_name(crtc->pipe));
1281         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1282
1283         fbc->crtc = crtc;
1284 out:
1285         mutex_unlock(&fbc->lock);
1286 }
1287
1288 /**
1289  * intel_fbc_disable - disable FBC if it's associated with crtc
1290  * @crtc: the CRTC
1291  *
1292  * This function disables FBC if it's associated with the provided CRTC.
1293  */
1294 void intel_fbc_disable(struct intel_crtc *crtc)
1295 {
1296         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1297         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1298         struct intel_fbc *fbc = &dev_priv->fbc;
1299
1300         if (!plane->has_fbc)
1301                 return;
1302
1303         mutex_lock(&fbc->lock);
1304         if (fbc->crtc == crtc)
1305                 __intel_fbc_disable(dev_priv);
1306         mutex_unlock(&fbc->lock);
1307 }
1308
1309 /**
1310  * intel_fbc_global_disable - globally disable FBC
1311  * @dev_priv: i915 device instance
1312  *
1313  * This function disables FBC regardless of which CRTC is associated with it.
1314  */
1315 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1316 {
1317         struct intel_fbc *fbc = &dev_priv->fbc;
1318
1319         if (!HAS_FBC(dev_priv))
1320                 return;
1321
1322         mutex_lock(&fbc->lock);
1323         if (fbc->crtc) {
1324                 drm_WARN_ON(&dev_priv->drm, fbc->crtc->active);
1325                 __intel_fbc_disable(dev_priv);
1326         }
1327         mutex_unlock(&fbc->lock);
1328 }
1329
1330 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1331 {
1332         struct drm_i915_private *dev_priv =
1333                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1334         struct intel_fbc *fbc = &dev_priv->fbc;
1335
1336         mutex_lock(&fbc->lock);
1337
1338         /* Maybe we were scheduled twice. */
1339         if (fbc->underrun_detected || !fbc->crtc)
1340                 goto out;
1341
1342         drm_dbg_kms(&dev_priv->drm, "Disabling FBC due to FIFO underrun.\n");
1343         fbc->underrun_detected = true;
1344
1345         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1346 out:
1347         mutex_unlock(&fbc->lock);
1348 }
1349
1350 /*
1351  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1352  * @dev_priv: i915 device instance
1353  *
1354  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1355  * want to re-enable FBC after an underrun to increase test coverage.
1356  */
1357 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1358 {
1359         int ret;
1360
1361         cancel_work_sync(&dev_priv->fbc.underrun_work);
1362
1363         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1364         if (ret)
1365                 return ret;
1366
1367         if (dev_priv->fbc.underrun_detected) {
1368                 drm_dbg_kms(&dev_priv->drm,
1369                             "Re-allowing FBC after fifo underrun\n");
1370                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1371         }
1372
1373         dev_priv->fbc.underrun_detected = false;
1374         mutex_unlock(&dev_priv->fbc.lock);
1375
1376         return 0;
1377 }
1378
1379 /**
1380  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1381  * @dev_priv: i915 device instance
1382  *
1383  * Without FBC, most underruns are harmless and don't really cause too many
1384  * problems, except for an annoying message on dmesg. With FBC, underruns can
1385  * become black screens or even worse, especially when paired with bad
1386  * watermarks. So in order for us to be on the safe side, completely disable FBC
1387  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1388  * already suggests that watermarks may be bad, so try to be as safe as
1389  * possible.
1390  *
1391  * This function is called from the IRQ handler.
1392  */
1393 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1394 {
1395         struct intel_fbc *fbc = &dev_priv->fbc;
1396
1397         if (!HAS_FBC(dev_priv))
1398                 return;
1399
1400         /* There's no guarantee that underrun_detected won't be set to true
1401          * right after this check and before the work is scheduled, but that's
1402          * not a problem since we'll check it again under the work function
1403          * while FBC is locked. This check here is just to prevent us from
1404          * unnecessarily scheduling the work, and it relies on the fact that we
1405          * never switch underrun_detect back to false after it's true. */
1406         if (READ_ONCE(fbc->underrun_detected))
1407                 return;
1408
1409         schedule_work(&fbc->underrun_work);
1410 }
1411
1412 /*
1413  * The DDX driver changes its behavior depending on the value it reads from
1414  * i915.enable_fbc, so sanitize it by translating the default value into either
1415  * 0 or 1 in order to allow it to know what's going on.
1416  *
1417  * Notice that this is done at driver initialization and we still allow user
1418  * space to change the value during runtime without sanitizing it again. IGT
1419  * relies on being able to change i915.enable_fbc at runtime.
1420  */
1421 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1422 {
1423         if (dev_priv->params.enable_fbc >= 0)
1424                 return !!dev_priv->params.enable_fbc;
1425
1426         if (!HAS_FBC(dev_priv))
1427                 return 0;
1428
1429         /*
1430          * Fbc is causing random underruns in CI execution on TGL platforms.
1431          * Disabling the same while the problem is being debugged and analyzed.
1432          */
1433         if (IS_TIGERLAKE(dev_priv))
1434                 return 0;
1435
1436         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1437                 return 1;
1438
1439         return 0;
1440 }
1441
1442 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1443 {
1444         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1445         if (intel_vtd_active() &&
1446             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1447                 drm_info(&dev_priv->drm,
1448                          "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1449                 return true;
1450         }
1451
1452         return false;
1453 }
1454
1455 /**
1456  * intel_fbc_init - Initialize FBC
1457  * @dev_priv: the i915 device
1458  *
1459  * This function might be called during PM init process.
1460  */
1461 void intel_fbc_init(struct drm_i915_private *dev_priv)
1462 {
1463         struct intel_fbc *fbc = &dev_priv->fbc;
1464
1465         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1466         mutex_init(&fbc->lock);
1467         fbc->active = false;
1468
1469         if (!drm_mm_initialized(&dev_priv->mm.stolen))
1470                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1471
1472         if (need_fbc_vtd_wa(dev_priv))
1473                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1474
1475         dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1476         drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n",
1477                     dev_priv->params.enable_fbc);
1478
1479         if (!HAS_FBC(dev_priv)) {
1480                 fbc->no_fbc_reason = "unsupported by this chipset";
1481                 return;
1482         }
1483
1484         /* We still don't have any sort of hardware state readout for FBC, so
1485          * deactivate it in case the BIOS activated it to make sure software
1486          * matches the hardware state. */
1487         if (intel_fbc_hw_is_active(dev_priv))
1488                 intel_fbc_hw_deactivate(dev_priv);
1489 }