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25 #ifndef _INTEL_DPLL_MGR_H_
26 #define _INTEL_DPLL_MGR_H_
28 #include <linux/types.h>
30 #include "intel_display.h"
31 #include "intel_wakeref.h"
33 /*FIXME: Move this to a more appropriate place. */
34 #define abs_diff(a, b) ({ \
35 typeof(a) __a = (a); \
36 typeof(b) __b = (b); \
37 (void) (&__a == &__b); \
38 __a > __b ? (__a - __b) : (__b - __a); })
41 struct drm_i915_private;
42 struct intel_atomic_state;
44 struct intel_crtc_state;
46 struct intel_shared_dpll;
49 * enum intel_dpll_id - possible DPLL ids
51 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
55 * @DPLL_ID_PRIVATE: non-shared dpll in use
60 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
62 DPLL_ID_PCH_PLL_A = 0,
64 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
66 DPLL_ID_PCH_PLL_B = 1,
70 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
74 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
78 * @DPLL_ID_SPLL: HSW and BDW SPLL
82 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
84 DPLL_ID_LCPLL_810 = 3,
86 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
88 DPLL_ID_LCPLL_1350 = 4,
90 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
92 DPLL_ID_LCPLL_2700 = 5,
96 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
98 DPLL_ID_SKL_DPLL0 = 0,
100 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
102 DPLL_ID_SKL_DPLL1 = 1,
104 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
106 DPLL_ID_SKL_DPLL2 = 2,
108 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
110 DPLL_ID_SKL_DPLL3 = 3,
114 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
116 DPLL_ID_ICL_DPLL0 = 0,
118 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
120 DPLL_ID_ICL_DPLL1 = 1,
122 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
124 DPLL_ID_EHL_DPLL4 = 2,
126 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
128 DPLL_ID_ICL_TBTPLL = 2,
130 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
131 * TGL TC PLL 1 port 1 (TC1)
133 DPLL_ID_ICL_MGPLL1 = 3,
135 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
136 * TGL TC PLL 1 port 2 (TC2)
138 DPLL_ID_ICL_MGPLL2 = 4,
140 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
141 * TGL TC PLL 1 port 3 (TC3)
143 DPLL_ID_ICL_MGPLL3 = 5,
145 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
146 * TGL TC PLL 1 port 4 (TC4)
148 DPLL_ID_ICL_MGPLL4 = 6,
150 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
152 DPLL_ID_TGL_MGPLL5 = 7,
154 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
156 DPLL_ID_TGL_MGPLL6 = 8,
159 #define I915_NUM_PLLS 9
161 enum icl_port_dpll_id {
162 ICL_PORT_DPLL_DEFAULT,
163 ICL_PORT_DPLL_MG_PHY,
168 struct intel_dpll_hw_state {
181 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
182 * lower part of ctrl1 and they get shifted into position when writing
183 * the register. This allows us to easily compare the state to share
187 /* HDMI only, 0 when used for DP */
192 /* CNL also uses cfgcr1 */
195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
198 * ICL uses the following, already defined:
199 * u32 cfgcr0, cfgcr1;
202 u32 mg_clktop2_coreclkctl1;
203 u32 mg_clktop2_hsclkctl;
207 u32 mg_pll_frac_lock;
210 u32 mg_pll_tdc_coldst_bias;
211 u32 mg_pll_bias_mask;
212 u32 mg_pll_tdc_coldst_bias_mask;
216 * struct intel_shared_dpll_state - hold the DPLL atomic state
218 * This structure holds an atomic state for the DPLL, that can represent
219 * either its current state (in struct &intel_shared_dpll) or a desired
220 * future state which would be applied by an atomic mode set (stored in
221 * a struct &intel_atomic_state).
223 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
225 struct intel_shared_dpll_state {
227 * @crtc_mask: mask of CRTC using this DPLL, active or not
232 * @hw_state: hardware configuration for the DPLL stored in
233 * struct &intel_dpll_hw_state.
235 struct intel_dpll_hw_state hw_state;
239 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
241 struct intel_shared_dpll_funcs {
245 * Optional hook to perform operations prior to enabling the PLL.
246 * Called from intel_prepare_shared_dpll() function unless the PLL
247 * is already enabled.
249 void (*prepare)(struct drm_i915_private *dev_priv,
250 struct intel_shared_dpll *pll);
255 * Hook for enabling the pll, called from intel_enable_shared_dpll()
256 * if the pll is not already enabled.
258 void (*enable)(struct drm_i915_private *dev_priv,
259 struct intel_shared_dpll *pll);
264 * Hook for disabling the pll, called from intel_disable_shared_dpll()
265 * only when it is safe to disable the pll, i.e., there are no more
266 * tracked users for it.
268 void (*disable)(struct drm_i915_private *dev_priv,
269 struct intel_shared_dpll *pll);
274 * Hook for reading the values currently programmed to the DPLL
275 * registers. This is used for initial hw state readout and state
276 * verification after a mode set.
278 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
279 struct intel_shared_dpll *pll,
280 struct intel_dpll_hw_state *hw_state);
285 * Hook for calculating the pll's output frequency based on its
288 int (*get_freq)(struct drm_i915_private *i915,
289 const struct intel_shared_dpll *pll);
293 * struct dpll_info - display PLL platform specific info
297 * @name: DPLL name; used for logging
302 * @funcs: platform specific hooks
304 const struct intel_shared_dpll_funcs *funcs;
307 * @id: unique indentifier for this DPLL; should match the index in the
308 * dev_priv->shared_dplls array
310 enum intel_dpll_id id;
312 #define INTEL_DPLL_ALWAYS_ON (1 << 0)
316 * INTEL_DPLL_ALWAYS_ON
317 * Inform the state checker that the DPLL is kept enabled even if
318 * not in use by any CRTC.
324 * struct intel_shared_dpll - display PLL with tracked state and users
326 struct intel_shared_dpll {
330 * Store the state for the pll, including its hw state
331 * and CRTCs using it.
333 struct intel_shared_dpll_state state;
336 * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL
338 unsigned active_mask;
341 * @on: is the PLL actually active? Disabled during modeset
346 * @info: platform specific info
348 const struct dpll_info *info;
351 * @wakeref: In some platforms a device-level runtime pm reference may
352 * need to be grabbed to disable DC states while this DPLL is enabled
354 intel_wakeref_t wakeref;
362 /* shared dpll functions */
363 struct intel_shared_dpll *
364 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
365 enum intel_dpll_id id);
367 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
368 struct intel_shared_dpll *pll);
369 void assert_shared_dpll(struct drm_i915_private *dev_priv,
370 struct intel_shared_dpll *pll,
372 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
373 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
374 bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
375 struct intel_crtc *crtc,
376 struct intel_encoder *encoder);
377 void intel_release_shared_dplls(struct intel_atomic_state *state,
378 struct intel_crtc *crtc);
379 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
380 enum icl_port_dpll_id port_dpll_id);
381 void intel_update_active_dpll(struct intel_atomic_state *state,
382 struct intel_crtc *crtc,
383 struct intel_encoder *encoder);
384 int intel_dpll_get_freq(struct drm_i915_private *i915,
385 const struct intel_shared_dpll *pll);
386 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
387 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
388 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
389 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
390 void intel_shared_dpll_init(struct drm_device *dev);
391 void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
392 void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
394 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
395 const struct intel_dpll_hw_state *hw_state);
396 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
397 bool intel_dpll_is_combophy(enum intel_dpll_id id);
399 #endif /* _INTEL_DPLL_MGR_H_ */