display/intel_dp_link_training.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_display_types.h"
  25 #include "intel_dp.h"
  26 #include "intel_dp_link_training.h"
  27
  28 static void
  29 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
  30 {
  31
  32         DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
  33                       link_status[0], link_status[1], link_status[2],
  34                       link_status[3], link_status[4], link_status[5]);
  35 }
  36
  37 static u8 dp_voltage_max(u8 preemph)
  38 {
  39         switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
  40         case DP_TRAIN_PRE_EMPH_LEVEL_0:
  41                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
  42         case DP_TRAIN_PRE_EMPH_LEVEL_1:
  43                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
  44         case DP_TRAIN_PRE_EMPH_LEVEL_2:
  45                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
  46         case DP_TRAIN_PRE_EMPH_LEVEL_3:
  47         default:
  48                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
  49         }
  50 }
  51
  52 void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
  53                                const u8 link_status[DP_LINK_STATUS_SIZE])
  54 {
  55         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
  56         u8 v = 0;
  57         u8 p = 0;
  58         int lane;
  59         u8 voltage_max;
  60         u8 preemph_max;
  61
  62         for (lane = 0; lane < intel_dp->lane_count; lane++) {
  63                 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
  64                 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
  65         }
  66
  67         preemph_max = intel_dp->preemph_max(intel_dp);
  68         drm_WARN_ON_ONCE(&i915->drm,
  69                          preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
  70                          preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
  71
  72         if (p >= preemph_max)
  73                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  74
  75         v = min(v, dp_voltage_max(p));
  76
  77         voltage_max = intel_dp->voltage_max(intel_dp);
  78         drm_WARN_ON_ONCE(&i915->drm,
  79                          voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
  80                          voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
  81
  82         if (v >= voltage_max)
  83                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  84
  85         for (lane = 0; lane < 4; lane++)
  86                 intel_dp->train_set[lane] = v | p;
  87 }
  88
  89 static bool
  90 intel_dp_set_link_train(struct intel_dp *intel_dp,
  91                         u8 dp_train_pat)
  92 {
  93         u8 buf[sizeof(intel_dp->train_set) + 1];
  94         int ret, len;
  95
  96         intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
  97
  98         buf[0] = dp_train_pat;
  99         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
 100             DP_TRAINING_PATTERN_DISABLE) {
 101                 /* don't write DP_TRAINING_LANEx_SET on disable */
 102                 len = 1;
 103         } else {
 104                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
 105                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
 106                 len = intel_dp->lane_count + 1;
 107         }
 108
 109         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
 110                                 buf, len);
 111
 112         return ret == len;
 113 }
 114
 115 static bool
 116 intel_dp_reset_link_train(struct intel_dp *intel_dp,
 117                         u8 dp_train_pat)
 118 {
 119         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 120         intel_dp_set_signal_levels(intel_dp);
 121         return intel_dp_set_link_train(intel_dp, dp_train_pat);
 122 }
 123
 124 static bool
 125 intel_dp_update_link_train(struct intel_dp *intel_dp)
 126 {
 127         int ret;
 128
 129         intel_dp_set_signal_levels(intel_dp);
 130
 131         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
 132                                 intel_dp->train_set, intel_dp->lane_count);
 133
 134         return ret == intel_dp->lane_count;
 135 }
 136
 137 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
 138 {
 139         int lane;
 140
 141         for (lane = 0; lane < intel_dp->lane_count; lane++)
 142                 if ((intel_dp->train_set[lane] &
 143                      DP_TRAIN_MAX_SWING_REACHED) == 0)
 144                         return false;
 145
 146         return true;
 147 }
 148
 149 /* Enable corresponding port and start training pattern 1 */
 150 static bool
 151 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 152 {
 153         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 154         u8 voltage;
 155         int voltage_tries, cr_tries, max_cr_tries;
 156         bool max_vswing_reached = false;
 157         u8 link_config[2];
 158         u8 link_bw, rate_select;
 159
 160         if (intel_dp->prepare_link_retrain)
 161                 intel_dp->prepare_link_retrain(intel_dp);
 162
 163         intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
 164                               &link_bw, &rate_select);
 165
 166         /*
 167          * WaEdpLinkRateDataReload
 168          *
 169          * Parade PS8461E MUX (used on varius TGL+ laptops) needs
 170          * to snoop the link rates reported by the sink when we
 171          * use LINK_RATE_SET in order to operate in jitter cleaning
 172          * mode (as opposed to redriver mode). Unfortunately it
 173          * loses track of the snooped link rates when powered down,
 174          * so we need to make it re-snoop often. Without this high
 175          * link rates are not stable.
 176          */
 177         if (!link_bw) {
 178                 struct intel_connector *connector = intel_dp->attached_connector;
 179                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 180
 181                 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Reloading eDP link rates\n",
 182                             connector->base.base.id, connector->base.name);
 183
 184                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
 185                                  sink_rates, sizeof(sink_rates));
 186         }
 187
 188         if (link_bw)
 189                 drm_dbg_kms(&i915->drm,
 190                             "Using LINK_BW_SET value %02x\n", link_bw);
 191         else
 192                 drm_dbg_kms(&i915->drm,
 193                             "Using LINK_RATE_SET value %02x\n", rate_select);
 194
 195         /* Write the link configuration data */
 196         link_config[0] = link_bw;
 197         link_config[1] = intel_dp->lane_count;
 198         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 199                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 200         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 201
 202         /* eDP 1.4 rate select method. */
 203         if (!link_bw)
 204                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 205                                   &rate_select, 1);
 206
 207         link_config[0] = 0;
 208         link_config[1] = DP_SET_ANSI_8B10B;
 209         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 210
 211         intel_dp->DP |= DP_PORT_EN;
 212
 213         /* clock recovery */
 214         if (!intel_dp_reset_link_train(intel_dp,
 215                                        DP_TRAINING_PATTERN_1 |
 216                                        DP_LINK_SCRAMBLING_DISABLE)) {
 217                 drm_err(&i915->drm, "failed to enable link training\n");
 218                 return false;
 219         }
 220
 221         /*
 222          * The DP 1.4 spec defines the max clock recovery retries value
 223          * as 10 but for pre-DP 1.4 devices we set a very tolerant
 224          * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
 225          * x 5 identical voltage retries). Since the previous specs didn't
 226          * define a limit and created the possibility of an infinite loop
 227          * we want to prevent any sync from triggering that corner case.
 228          */
 229         if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 230                 max_cr_tries = 10;
 231         else
 232                 max_cr_tries = 80;
 233
 234         voltage_tries = 1;
 235         for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 236                 u8 link_status[DP_LINK_STATUS_SIZE];
 237
 238                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
 239
 240                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 241                         drm_err(&i915->drm, "failed to get link status\n");
 242                         return false;
 243                 }
 244
 245                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 246                         drm_dbg_kms(&i915->drm, "clock recovery OK\n");
 247                         return true;
 248                 }
 249
 250                 if (voltage_tries == 5) {
 251                         drm_dbg_kms(&i915->drm,
 252                                     "Same voltage tried 5 times\n");
 253                         return false;
 254                 }
 255
 256                 if (max_vswing_reached) {
 257                         drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
 258                         return false;
 259                 }
 260
 261                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 262
 263                 /* Update training set as requested by target */
 264                 intel_dp_get_adjust_train(intel_dp, link_status);
 265                 if (!intel_dp_update_link_train(intel_dp)) {
 266                         drm_err(&i915->drm,
 267                                 "failed to update link training\n");
 268                         return false;
 269                 }
 270
 271                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
 272                     voltage)
 273                         ++voltage_tries;
 274                 else
 275                         voltage_tries = 1;
 276
 277                 if (intel_dp_link_max_vswing_reached(intel_dp))
 278                         max_vswing_reached = true;
 279
 280         }
 281         drm_err(&i915->drm,
 282                 "Failed clock recovery %d times, giving up!\n", max_cr_tries);
 283         return false;
 284 }
 285
 286 /*
 287  * Pick training pattern for channel equalization. Training pattern 4 for HBR3
 288  * or for 1.4 devices that support it, training Pattern 3 for HBR2
 289  * or 1.2 devices that support it, Training Pattern 2 otherwise.
 290  */
 291 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 292 {
 293         bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 294
 295         /*
 296          * Intel platforms that support HBR3 also support TPS4. It is mandatory
 297          * for all downstream devices that support HBR3. There are no known eDP
 298          * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
 299          * specification.
 300          */
 301         source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
 302         sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
 303         if (source_tps4 && sink_tps4) {
 304                 return DP_TRAINING_PATTERN_4;
 305         } else if (intel_dp->link_rate == 810000) {
 306                 if (!source_tps4)
 307                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 308                                     "8.1 Gbps link rate without source HBR3/TPS4 support\n");
 309                 if (!sink_tps4)
 310                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 311                                     "8.1 Gbps link rate without sink TPS4 support\n");
 312         }
 313         /*
 314          * Intel platforms that support HBR2 also support TPS3. TPS3 support is
 315          * also mandatory for downstream devices that support HBR2. However, not
 316          * all sinks follow the spec.
 317          */
 318         source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
 319         sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
 320         if (source_tps3 && sink_tps3) {
 321                 return  DP_TRAINING_PATTERN_3;
 322         } else if (intel_dp->link_rate >= 540000) {
 323                 if (!source_tps3)
 324                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 325                                     ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
 326                 if (!sink_tps3)
 327                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 328                                     ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
 329         }
 330
 331         return DP_TRAINING_PATTERN_2;
 332 }
 333
 334 static bool
 335 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 336 {
 337         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 338         int tries;
 339         u32 training_pattern;
 340         u8 link_status[DP_LINK_STATUS_SIZE];
 341         bool channel_eq = false;
 342
 343         training_pattern = intel_dp_training_pattern(intel_dp);
 344         /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 345         if (training_pattern != DP_TRAINING_PATTERN_4)
 346                 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 347
 348         /* channel equalization */
 349         if (!intel_dp_set_link_train(intel_dp,
 350                                      training_pattern)) {
 351                 drm_err(&i915->drm, "failed to start channel equalization\n");
 352                 return false;
 353         }
 354
 355         for (tries = 0; tries < 5; tries++) {
 356
 357                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
 358                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
 359                         drm_err(&i915->drm,
 360                                 "failed to get link status\n");
 361                         break;
 362                 }
 363
 364                 /* Make sure clock is still ok */
 365                 if (!drm_dp_clock_recovery_ok(link_status,
 366                                               intel_dp->lane_count)) {
 367                         intel_dp_dump_link_status(link_status);
 368                         drm_dbg_kms(&i915->drm,
 369                                     "Clock recovery check failed, cannot "
 370                                     "continue channel equalization\n");
 371                         break;
 372                 }
 373
 374                 if (drm_dp_channel_eq_ok(link_status,
 375                                          intel_dp->lane_count)) {
 376                         channel_eq = true;
 377                         drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
 378                                     "successful\n");
 379                         break;
 380                 }
 381
 382                 /* Update training set as requested by target */
 383                 intel_dp_get_adjust_train(intel_dp, link_status);
 384                 if (!intel_dp_update_link_train(intel_dp)) {
 385                         drm_err(&i915->drm,
 386                                 "failed to update link training\n");
 387                         break;
 388                 }
 389         }
 390
 391         /* Try 5 times, else fail and try at lower BW */
 392         if (tries == 5) {
 393                 intel_dp_dump_link_status(link_status);
 394                 drm_dbg_kms(&i915->drm,
 395                             "Channel equalization failed 5 times\n");
 396         }
 397
 398         intel_dp_set_idle_link_train(intel_dp);
 399
 400         return channel_eq;
 401
 402 }
 403
 404 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
 405 {
 406         intel_dp->link_trained = true;
 407
 408         intel_dp_set_link_train(intel_dp,
 409                                 DP_TRAINING_PATTERN_DISABLE);
 410 }
 411
 412 void
 413 intel_dp_start_link_train(struct intel_dp *intel_dp)
 414 {
 415         struct intel_connector *intel_connector = intel_dp->attached_connector;
 416
 417         if (!intel_dp_link_training_clock_recovery(intel_dp))
 418                 goto failure_handling;
 419         if (!intel_dp_link_training_channel_equalization(intel_dp))
 420                 goto failure_handling;
 421
 422         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 423                     "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
 424                     intel_connector->base.base.id,
 425                     intel_connector->base.name,
 426                     intel_dp->link_rate, intel_dp->lane_count);
 427         return;
 428
 429  failure_handling:
 430         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 431                     "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
 432                     intel_connector->base.base.id,
 433                     intel_connector->base.name,
 434                     intel_dp->link_rate, intel_dp->lane_count);
 435
 436         if (intel_dp->hobl_active) {
 437                 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 438                             "Link Training failed with HOBL active, not enabling it from now on");
 439                 intel_dp->hobl_failed = true;
 440         } else if (intel_dp_get_link_train_fallback_values(intel_dp,
 441                                                            intel_dp->link_rate,
 442                                                            intel_dp->lane_count)) {
 443                 return;
 444         }
 445
 446         /* Schedule a Hotplug Uevent to userspace to start modeset */
 447         schedule_work(&intel_connector->modeset_retry_work);
 448 }