display/intel_display_power.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_DISPLAY_POWER_H__
   7 #define __INTEL_DISPLAY_POWER_H__
   8
   9 #include "intel_display.h"
  10 #include "intel_runtime_pm.h"
  11 #include "i915_reg.h"
  12
  13 struct drm_i915_private;
  14 struct intel_encoder;
  15
  16 enum intel_display_power_domain {
  17         POWER_DOMAIN_DISPLAY_CORE,
  18         POWER_DOMAIN_PIPE_A,
  19         POWER_DOMAIN_PIPE_B,
  20         POWER_DOMAIN_PIPE_C,
  21         POWER_DOMAIN_PIPE_D,
  22         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
  23         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
  24         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
  25         POWER_DOMAIN_PIPE_D_PANEL_FITTER,
  26         POWER_DOMAIN_TRANSCODER_A,
  27         POWER_DOMAIN_TRANSCODER_B,
  28         POWER_DOMAIN_TRANSCODER_C,
  29         POWER_DOMAIN_TRANSCODER_D,
  30         POWER_DOMAIN_TRANSCODER_EDP,
  31         /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
  32         POWER_DOMAIN_TRANSCODER_VDSC_PW2,
  33         POWER_DOMAIN_TRANSCODER_DSI_A,
  34         POWER_DOMAIN_TRANSCODER_DSI_C,
  35         POWER_DOMAIN_PORT_DDI_A_LANES,
  36         POWER_DOMAIN_PORT_DDI_B_LANES,
  37         POWER_DOMAIN_PORT_DDI_C_LANES,
  38         POWER_DOMAIN_PORT_DDI_D_LANES,
  39         POWER_DOMAIN_PORT_DDI_E_LANES,
  40         POWER_DOMAIN_PORT_DDI_F_LANES,
  41         POWER_DOMAIN_PORT_DDI_G_LANES,
  42         POWER_DOMAIN_PORT_DDI_H_LANES,
  43         POWER_DOMAIN_PORT_DDI_I_LANES,
  44         POWER_DOMAIN_PORT_DDI_A_IO,
  45         POWER_DOMAIN_PORT_DDI_B_IO,
  46         POWER_DOMAIN_PORT_DDI_C_IO,
  47         POWER_DOMAIN_PORT_DDI_D_IO,
  48         POWER_DOMAIN_PORT_DDI_E_IO,
  49         POWER_DOMAIN_PORT_DDI_F_IO,
  50         POWER_DOMAIN_PORT_DDI_G_IO,
  51         POWER_DOMAIN_PORT_DDI_H_IO,
  52         POWER_DOMAIN_PORT_DDI_I_IO,
  53         POWER_DOMAIN_PORT_DSI,
  54         POWER_DOMAIN_PORT_CRT,
  55         POWER_DOMAIN_PORT_OTHER,
  56         POWER_DOMAIN_VGA,
  57         POWER_DOMAIN_AUDIO,
  58         POWER_DOMAIN_AUX_A,
  59         POWER_DOMAIN_AUX_B,
  60         POWER_DOMAIN_AUX_C,
  61         POWER_DOMAIN_AUX_D,
  62         POWER_DOMAIN_AUX_E,
  63         POWER_DOMAIN_AUX_F,
  64         POWER_DOMAIN_AUX_G,
  65         POWER_DOMAIN_AUX_H,
  66         POWER_DOMAIN_AUX_I,
  67         POWER_DOMAIN_AUX_IO_A,
  68         POWER_DOMAIN_AUX_C_TBT,
  69         POWER_DOMAIN_AUX_D_TBT,
  70         POWER_DOMAIN_AUX_E_TBT,
  71         POWER_DOMAIN_AUX_F_TBT,
  72         POWER_DOMAIN_AUX_G_TBT,
  73         POWER_DOMAIN_AUX_H_TBT,
  74         POWER_DOMAIN_AUX_I_TBT,
  75         POWER_DOMAIN_GMBUS,
  76         POWER_DOMAIN_MODESET,
  77         POWER_DOMAIN_GT_IRQ,
  78         POWER_DOMAIN_DPLL_DC_OFF,
  79         POWER_DOMAIN_TC_COLD_OFF,
  80         POWER_DOMAIN_INIT,
  81
  82         POWER_DOMAIN_NUM,
  83 };
  84
  85 /*
  86  * i915_power_well_id:
  87  *
  88  * IDs used to look up power wells. Power wells accessed directly bypassing
  89  * the power domains framework must be assigned a unique ID. The rest of power
  90  * wells must be assigned DISP_PW_ID_NONE.
  91  */
  92 enum i915_power_well_id {
  93         DISP_PW_ID_NONE,
  94
  95         VLV_DISP_PW_DISP2D,
  96         BXT_DISP_PW_DPIO_CMN_A,
  97         VLV_DISP_PW_DPIO_CMN_BC,
  98         GLK_DISP_PW_DPIO_CMN_C,
  99         CHV_DISP_PW_DPIO_CMN_D,
 100         HSW_DISP_PW_GLOBAL,
 101         SKL_DISP_PW_MISC_IO,
 102         SKL_DISP_PW_1,
 103         SKL_DISP_PW_2,
 104         ICL_DISP_PW_3,
 105         SKL_DISP_DC_OFF,
 106 };
 107
 108 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 109 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 110                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 111 #define POWER_DOMAIN_TRANSCODER(tran) \
 112         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 113          (tran) + POWER_DOMAIN_TRANSCODER_A)
 114
 115 struct i915_power_well;
 116
 117 struct i915_power_well_ops {
 118         /*
 119          * Synchronize the well's hw state to match the current sw state, for
 120          * example enable/disable it based on the current refcount. Called
 121          * during driver init and resume time, possibly after first calling
 122          * the enable/disable handlers.
 123          */
 124         void (*sync_hw)(struct drm_i915_private *dev_priv,
 125                         struct i915_power_well *power_well);
 126         /*
 127          * Enable the well and resources that depend on it (for example
 128          * interrupts located on the well). Called after the 0->1 refcount
 129          * transition.
 130          */
 131         void (*enable)(struct drm_i915_private *dev_priv,
 132                        struct i915_power_well *power_well);
 133         /*
 134          * Disable the well and resources that depend on it. Called after
 135          * the 1->0 refcount transition.
 136          */
 137         void (*disable)(struct drm_i915_private *dev_priv,
 138                         struct i915_power_well *power_well);
 139         /* Returns the hw enabled state. */
 140         bool (*is_enabled)(struct drm_i915_private *dev_priv,
 141                            struct i915_power_well *power_well);
 142 };
 143
 144 struct i915_power_well_regs {
 145         i915_reg_t bios;
 146         i915_reg_t driver;
 147         i915_reg_t kvmr;
 148         i915_reg_t debug;
 149 };
 150
 151 /* Power well structure for haswell */
 152 struct i915_power_well_desc {
 153         const char *name;
 154         bool always_on;
 155         u64 domains;
 156         /* unique identifier for this power well */
 157         enum i915_power_well_id id;
 158         /*
 159          * Arbitraty data associated with this power well. Platform and power
 160          * well specific.
 161          */
 162         union {
 163                 struct {
 164                         /*
 165                          * request/status flag index in the PUNIT power well
 166                          * control/status registers.
 167                          */
 168                         u8 idx;
 169                 } vlv;
 170                 struct {
 171                         enum dpio_phy phy;
 172                 } bxt;
 173                 struct {
 174                         const struct i915_power_well_regs *regs;
 175                         /*
 176                          * request/status flag index in the power well
 177                          * constrol/status registers.
 178                          */
 179                         u8 idx;
 180                         /* Mask of pipes whose IRQ logic is backed by the pw */
 181                         u8 irq_pipe_mask;
 182                         /* The pw is backing the VGA functionality */
 183                         bool has_vga:1;
 184                         bool has_fuses:1;
 185                         /*
 186                          * The pw is for an ICL+ TypeC PHY port in
 187                          * Thunderbolt mode.
 188                          */
 189                         bool is_tc_tbt:1;
 190                 } hsw;
 191         };
 192         const struct i915_power_well_ops *ops;
 193 };
 194
 195 struct i915_power_well {
 196         const struct i915_power_well_desc *desc;
 197         /* power well enable/disable usage count */
 198         int count;
 199         /* cached hw enabled state */
 200         bool hw_enabled;
 201 };
 202
 203 struct i915_power_domains {
 204         /*
 205          * Power wells needed for initialization at driver init and suspend
 206          * time are on. They are kept on until after the first modeset.
 207          */
 208         bool initializing;
 209         bool display_core_suspended;
 210         int power_well_count;
 211
 212         intel_wakeref_t wakeref;
 213
 214         struct mutex lock;
 215         int domain_use_count[POWER_DOMAIN_NUM];
 216
 217         struct delayed_work async_put_work;
 218         intel_wakeref_t async_put_wakeref;
 219         u64 async_put_domains[2];
 220
 221         struct i915_power_well *power_wells;
 222 };
 223
 224 #define for_each_power_domain(domain, mask)                             \
 225         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 226                 for_each_if(BIT_ULL(domain) & (mask))
 227
 228 #define for_each_power_well(__dev_priv, __power_well)                           \
 229         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
 230              (__power_well) - (__dev_priv)->power_domains.power_wells < \
 231                 (__dev_priv)->power_domains.power_well_count;           \
 232              (__power_well)++)
 233
 234 #define for_each_power_well_reverse(__dev_priv, __power_well)                   \
 235         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
 236                               (__dev_priv)->power_domains.power_well_count - 1; \
 237              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
 238              (__power_well)--)
 239
 240 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
 241         for_each_power_well(__dev_priv, __power_well)                           \
 242                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 243
 244 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
 245         for_each_power_well_reverse(__dev_priv, __power_well)                   \
 246                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 247
 248 int intel_power_domains_init(struct drm_i915_private *dev_priv);
 249 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 250 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 251 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
 252 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 253 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 254 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
 255                                  enum i915_drm_suspend_mode);
 256 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
 257
 258 void intel_display_power_suspend_late(struct drm_i915_private *i915);
 259 void intel_display_power_resume_early(struct drm_i915_private *i915);
 260 void intel_display_power_suspend(struct drm_i915_private *i915);
 261 void intel_display_power_resume(struct drm_i915_private *i915);
 262 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
 263                                              u32 state);
 264
 265 const char *
 266 intel_display_power_domain_str(enum intel_display_power_domain domain);
 267
 268 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 269                                     enum intel_display_power_domain domain);
 270 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
 271                                          enum i915_power_well_id power_well_id);
 272 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 273                                       enum intel_display_power_domain domain);
 274 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
 275                                         enum intel_display_power_domain domain);
 276 intel_wakeref_t
 277 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 278                                    enum intel_display_power_domain domain);
 279 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 280                                        enum intel_display_power_domain domain);
 281 void __intel_display_power_put_async(struct drm_i915_private *i915,
 282                                      enum intel_display_power_domain domain,
 283                                      intel_wakeref_t wakeref);
 284 void intel_display_power_flush_work(struct drm_i915_private *i915);
 285 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 286 void intel_display_power_put(struct drm_i915_private *dev_priv,
 287                              enum intel_display_power_domain domain,
 288                              intel_wakeref_t wakeref);
 289 static inline void
 290 intel_display_power_put_async(struct drm_i915_private *i915,
 291                               enum intel_display_power_domain domain,
 292                               intel_wakeref_t wakeref)
 293 {
 294         __intel_display_power_put_async(i915, domain, wakeref);
 295 }
 296 #else
 297 static inline void
 298 intel_display_power_put(struct drm_i915_private *i915,
 299                         enum intel_display_power_domain domain,
 300                         intel_wakeref_t wakeref)
 301 {
 302         intel_display_power_put_unchecked(i915, domain);
 303 }
 304
 305 static inline void
 306 intel_display_power_put_async(struct drm_i915_private *i915,
 307                               enum intel_display_power_domain domain,
 308                               intel_wakeref_t wakeref)
 309 {
 310         __intel_display_power_put_async(i915, domain, -1);
 311 }
 312 #endif
 313
 314 enum dbuf_slice {
 315         DBUF_S1,
 316         DBUF_S2,
 317         I915_MAX_DBUF_SLICES
 318 };
 319
 320 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
 321                              u8 req_slices);
 322
 323 #define with_intel_display_power(i915, domain, wf) \
 324         for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
 325              intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
 326
 327 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 328                              bool override, unsigned int mask);
 329 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 330                           enum dpio_channel ch, bool override);
 331
 332 #endif /* __INTEL_DISPLAY_POWER_H__ */