2 * Copyright © 2006-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/time.h>
26 #include "intel_atomic.h"
28 #include "intel_cdclk.h"
29 #include "intel_display_types.h"
30 #include "intel_sideband.h"
35 * The display engine uses several different clocks to do its work. There
36 * are two main clocks involved that aren't directly related to the actual
37 * pixel clock or any symbol/bit clock of the actual output port. These
38 * are the core display clock (CDCLK) and RAWCLK.
40 * CDCLK clocks most of the display pipe logic, and thus its frequency
41 * must be high enough to support the rate at which pixels are flowing
42 * through the pipes. Downscaling must also be accounted as that increases
43 * the effective pixel rate.
45 * On several platforms the CDCLK frequency can be changed dynamically
46 * to minimize power consumption for a given display configuration.
47 * Typically changes to the CDCLK frequency require all the display pipes
48 * to be shut down while the frequency is being changed.
50 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
51 * DMC will not change the active CDCLK frequency however, so that part
52 * will still be performed by the driver directly.
54 * RAWCLK is a fixed frequency clock, often used by various auxiliary
55 * blocks such as AUX CH or backlight PWM. Hence the only thing we
56 * really need to know about RAWCLK is its frequency so that various
57 * dividers can be programmed correctly.
60 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
61 struct intel_cdclk_config *cdclk_config)
63 cdclk_config->cdclk = 133333;
66 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
67 struct intel_cdclk_config *cdclk_config)
69 cdclk_config->cdclk = 200000;
72 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
73 struct intel_cdclk_config *cdclk_config)
75 cdclk_config->cdclk = 266667;
78 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
79 struct intel_cdclk_config *cdclk_config)
81 cdclk_config->cdclk = 333333;
84 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
85 struct intel_cdclk_config *cdclk_config)
87 cdclk_config->cdclk = 400000;
90 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
91 struct intel_cdclk_config *cdclk_config)
93 cdclk_config->cdclk = 450000;
96 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
97 struct intel_cdclk_config *cdclk_config)
99 struct pci_dev *pdev = dev_priv->drm.pdev;
103 * 852GM/852GMV only supports 133 MHz and the HPLLCC
104 * encoding is different :(
105 * FIXME is this the right way to detect 852GM/852GMV?
107 if (pdev->revision == 0x1) {
108 cdclk_config->cdclk = 133333;
112 pci_bus_read_config_word(pdev->bus,
113 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
115 /* Assume that the hardware is in the high speed state. This
116 * should be the default.
118 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
119 case GC_CLOCK_133_200:
120 case GC_CLOCK_133_200_2:
121 case GC_CLOCK_100_200:
122 cdclk_config->cdclk = 200000;
124 case GC_CLOCK_166_250:
125 cdclk_config->cdclk = 250000;
127 case GC_CLOCK_100_133:
128 cdclk_config->cdclk = 133333;
130 case GC_CLOCK_133_266:
131 case GC_CLOCK_133_266_2:
132 case GC_CLOCK_166_266:
133 cdclk_config->cdclk = 266667;
138 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
139 struct intel_cdclk_config *cdclk_config)
141 struct pci_dev *pdev = dev_priv->drm.pdev;
144 pci_read_config_word(pdev, GCFGC, &gcfgc);
146 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
147 cdclk_config->cdclk = 133333;
151 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
152 case GC_DISPLAY_CLOCK_333_320_MHZ:
153 cdclk_config->cdclk = 333333;
156 case GC_DISPLAY_CLOCK_190_200_MHZ:
157 cdclk_config->cdclk = 190000;
162 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
163 struct intel_cdclk_config *cdclk_config)
165 struct pci_dev *pdev = dev_priv->drm.pdev;
168 pci_read_config_word(pdev, GCFGC, &gcfgc);
170 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
171 cdclk_config->cdclk = 133333;
175 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
176 case GC_DISPLAY_CLOCK_333_320_MHZ:
177 cdclk_config->cdclk = 320000;
180 case GC_DISPLAY_CLOCK_190_200_MHZ:
181 cdclk_config->cdclk = 200000;
186 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
188 static const unsigned int blb_vco[8] = {
195 static const unsigned int pnv_vco[8] = {
202 static const unsigned int cl_vco[8] = {
211 static const unsigned int elk_vco[8] = {
217 static const unsigned int ctg_vco[8] = {
225 const unsigned int *vco_table;
229 /* FIXME other chipsets? */
230 if (IS_GM45(dev_priv))
232 else if (IS_G45(dev_priv))
234 else if (IS_I965GM(dev_priv))
236 else if (IS_PINEVIEW(dev_priv))
238 else if (IS_G33(dev_priv))
243 tmp = intel_de_read(dev_priv,
244 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
246 vco = vco_table[tmp & 0x7];
248 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
251 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
256 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
257 struct intel_cdclk_config *cdclk_config)
259 struct pci_dev *pdev = dev_priv->drm.pdev;
260 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
261 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
262 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
263 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
265 unsigned int cdclk_sel;
268 cdclk_config->vco = intel_hpll_vco(dev_priv);
270 pci_read_config_word(pdev, GCFGC, &tmp);
272 cdclk_sel = (tmp >> 4) & 0x7;
274 if (cdclk_sel >= ARRAY_SIZE(div_3200))
277 switch (cdclk_config->vco) {
279 div_table = div_3200;
282 div_table = div_4000;
285 div_table = div_4800;
288 div_table = div_5333;
294 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
295 div_table[cdclk_sel]);
299 drm_err(&dev_priv->drm,
300 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
301 cdclk_config->vco, tmp);
302 cdclk_config->cdclk = 190476;
305 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
306 struct intel_cdclk_config *cdclk_config)
308 struct pci_dev *pdev = dev_priv->drm.pdev;
311 pci_read_config_word(pdev, GCFGC, &gcfgc);
313 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
314 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
315 cdclk_config->cdclk = 266667;
317 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
318 cdclk_config->cdclk = 333333;
320 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
321 cdclk_config->cdclk = 444444;
323 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
324 cdclk_config->cdclk = 200000;
327 drm_err(&dev_priv->drm,
328 "Unknown pnv display core clock 0x%04x\n", gcfgc);
330 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
331 cdclk_config->cdclk = 133333;
333 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
334 cdclk_config->cdclk = 166667;
339 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
340 struct intel_cdclk_config *cdclk_config)
342 struct pci_dev *pdev = dev_priv->drm.pdev;
343 static const u8 div_3200[] = { 16, 10, 8 };
344 static const u8 div_4000[] = { 20, 12, 10 };
345 static const u8 div_5333[] = { 24, 16, 14 };
347 unsigned int cdclk_sel;
350 cdclk_config->vco = intel_hpll_vco(dev_priv);
352 pci_read_config_word(pdev, GCFGC, &tmp);
354 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
356 if (cdclk_sel >= ARRAY_SIZE(div_3200))
359 switch (cdclk_config->vco) {
361 div_table = div_3200;
364 div_table = div_4000;
367 div_table = div_5333;
373 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
374 div_table[cdclk_sel]);
378 drm_err(&dev_priv->drm,
379 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
380 cdclk_config->vco, tmp);
381 cdclk_config->cdclk = 200000;
384 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
385 struct intel_cdclk_config *cdclk_config)
387 struct pci_dev *pdev = dev_priv->drm.pdev;
388 unsigned int cdclk_sel;
391 cdclk_config->vco = intel_hpll_vco(dev_priv);
393 pci_read_config_word(pdev, GCFGC, &tmp);
395 cdclk_sel = (tmp >> 12) & 0x1;
397 switch (cdclk_config->vco) {
401 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
404 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
407 drm_err(&dev_priv->drm,
408 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
409 cdclk_config->vco, tmp);
410 cdclk_config->cdclk = 222222;
415 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
416 struct intel_cdclk_config *cdclk_config)
418 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
419 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
421 if (lcpll & LCPLL_CD_SOURCE_FCLK)
422 cdclk_config->cdclk = 800000;
423 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
424 cdclk_config->cdclk = 450000;
425 else if (freq == LCPLL_CLK_FREQ_450)
426 cdclk_config->cdclk = 450000;
427 else if (IS_HSW_ULT(dev_priv))
428 cdclk_config->cdclk = 337500;
430 cdclk_config->cdclk = 540000;
433 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
435 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
439 * We seem to get an unstable or solid color picture at 200MHz.
440 * Not sure what's wrong. For now use 200MHz only when all pipes
443 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
445 else if (min_cdclk > 266667)
447 else if (min_cdclk > 0)
453 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
455 if (IS_VALLEYVIEW(dev_priv)) {
456 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
458 else if (cdclk >= 266667)
464 * Specs are full of misinformation, but testing on actual
465 * hardware has shown that we just need to write the desired
466 * CCK divider into the Punit register.
468 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
472 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
473 struct intel_cdclk_config *cdclk_config)
477 vlv_iosf_sb_get(dev_priv,
478 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
480 cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
481 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
482 CCK_DISPLAY_CLOCK_CONTROL,
485 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
487 vlv_iosf_sb_put(dev_priv,
488 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
490 if (IS_VALLEYVIEW(dev_priv))
491 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
494 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
495 DSPFREQGUAR_SHIFT_CHV;
498 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
500 unsigned int credits, default_credits;
502 if (IS_CHERRYVIEW(dev_priv))
503 default_credits = PFI_CREDIT(12);
505 default_credits = PFI_CREDIT(8);
507 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
508 /* CHV suggested value is 31 or 63 */
509 if (IS_CHERRYVIEW(dev_priv))
510 credits = PFI_CREDIT_63;
512 credits = PFI_CREDIT(15);
514 credits = default_credits;
518 * WA - write default credits before re-programming
519 * FIXME: should we also set the resend bit here?
521 intel_de_write(dev_priv, GCI_CONTROL,
522 VGA_FAST_MODE_DISABLE | default_credits);
524 intel_de_write(dev_priv, GCI_CONTROL,
525 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
528 * FIXME is this guaranteed to clear
529 * immediately or should we poll for it?
531 drm_WARN_ON(&dev_priv->drm,
532 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
535 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
536 const struct intel_cdclk_config *cdclk_config,
539 int cdclk = cdclk_config->cdclk;
540 u32 val, cmd = cdclk_config->voltage_level;
541 intel_wakeref_t wakeref;
555 /* There are cases where we can end up here with power domains
556 * off and a CDCLK frequency other than the minimum, like when
557 * issuing a modeset without actually changing any display after
558 * a system suspend. So grab the display core domain, which covers
559 * the HW blocks needed for the following programming.
561 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
563 vlv_iosf_sb_get(dev_priv,
564 BIT(VLV_IOSF_SB_CCK) |
565 BIT(VLV_IOSF_SB_BUNIT) |
566 BIT(VLV_IOSF_SB_PUNIT));
568 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
569 val &= ~DSPFREQGUAR_MASK;
570 val |= (cmd << DSPFREQGUAR_SHIFT);
571 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
572 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
573 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
575 drm_err(&dev_priv->drm,
576 "timed out waiting for CDclk change\n");
579 if (cdclk == 400000) {
582 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
585 /* adjust cdclk divider */
586 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
587 val &= ~CCK_FREQUENCY_VALUES;
589 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
591 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
592 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
594 drm_err(&dev_priv->drm,
595 "timed out waiting for CDclk change\n");
598 /* adjust self-refresh exit latency value */
599 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
603 * For high bandwidth configs, we set a higher latency in the bunit
604 * so that the core display fetch happens in time to avoid underruns.
607 val |= 4500 / 250; /* 4.5 usec */
609 val |= 3000 / 250; /* 3.0 usec */
610 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
612 vlv_iosf_sb_put(dev_priv,
613 BIT(VLV_IOSF_SB_CCK) |
614 BIT(VLV_IOSF_SB_BUNIT) |
615 BIT(VLV_IOSF_SB_PUNIT));
617 intel_update_cdclk(dev_priv);
619 vlv_program_pfi_credits(dev_priv);
621 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
624 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
625 const struct intel_cdclk_config *cdclk_config,
628 int cdclk = cdclk_config->cdclk;
629 u32 val, cmd = cdclk_config->voltage_level;
630 intel_wakeref_t wakeref;
643 /* There are cases where we can end up here with power domains
644 * off and a CDCLK frequency other than the minimum, like when
645 * issuing a modeset without actually changing any display after
646 * a system suspend. So grab the display core domain, which covers
647 * the HW blocks needed for the following programming.
649 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
651 vlv_punit_get(dev_priv);
652 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
653 val &= ~DSPFREQGUAR_MASK_CHV;
654 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
655 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
656 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
657 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
659 drm_err(&dev_priv->drm,
660 "timed out waiting for CDclk change\n");
663 vlv_punit_put(dev_priv);
665 intel_update_cdclk(dev_priv);
667 vlv_program_pfi_credits(dev_priv);
669 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
672 static int bdw_calc_cdclk(int min_cdclk)
674 if (min_cdclk > 540000)
676 else if (min_cdclk > 450000)
678 else if (min_cdclk > 337500)
684 static u8 bdw_calc_voltage_level(int cdclk)
699 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
700 struct intel_cdclk_config *cdclk_config)
702 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
703 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
705 if (lcpll & LCPLL_CD_SOURCE_FCLK)
706 cdclk_config->cdclk = 800000;
707 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
708 cdclk_config->cdclk = 450000;
709 else if (freq == LCPLL_CLK_FREQ_450)
710 cdclk_config->cdclk = 450000;
711 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
712 cdclk_config->cdclk = 540000;
713 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
714 cdclk_config->cdclk = 337500;
716 cdclk_config->cdclk = 675000;
719 * Can't read this out :( Let's assume it's
720 * at least what the CDCLK frequency requires.
722 cdclk_config->voltage_level =
723 bdw_calc_voltage_level(cdclk_config->cdclk);
726 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
727 const struct intel_cdclk_config *cdclk_config,
730 int cdclk = cdclk_config->cdclk;
734 if (drm_WARN(&dev_priv->drm,
735 (intel_de_read(dev_priv, LCPLL_CTL) &
736 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
737 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
738 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
739 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
740 "trying to change cdclk frequency with cdclk not enabled\n"))
743 ret = sandybridge_pcode_write(dev_priv,
744 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
746 drm_err(&dev_priv->drm,
747 "failed to inform pcode about cdclk change\n");
751 val = intel_de_read(dev_priv, LCPLL_CTL);
752 val |= LCPLL_CD_SOURCE_FCLK;
753 intel_de_write(dev_priv, LCPLL_CTL, val);
756 * According to the spec, it should be enough to poll for this 1 us.
757 * However, extensive testing shows that this can take longer.
759 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
760 LCPLL_CD_SOURCE_FCLK_DONE, 100))
761 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
763 val = intel_de_read(dev_priv, LCPLL_CTL);
764 val &= ~LCPLL_CLK_FREQ_MASK;
771 val |= LCPLL_CLK_FREQ_337_5_BDW;
774 val |= LCPLL_CLK_FREQ_450;
777 val |= LCPLL_CLK_FREQ_54O_BDW;
780 val |= LCPLL_CLK_FREQ_675_BDW;
784 intel_de_write(dev_priv, LCPLL_CTL, val);
786 val = intel_de_read(dev_priv, LCPLL_CTL);
787 val &= ~LCPLL_CD_SOURCE_FCLK;
788 intel_de_write(dev_priv, LCPLL_CTL, val);
790 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
791 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
792 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
794 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
795 cdclk_config->voltage_level);
797 intel_de_write(dev_priv, CDCLK_FREQ,
798 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
800 intel_update_cdclk(dev_priv);
803 static int skl_calc_cdclk(int min_cdclk, int vco)
805 if (vco == 8640000) {
806 if (min_cdclk > 540000)
808 else if (min_cdclk > 432000)
810 else if (min_cdclk > 308571)
815 if (min_cdclk > 540000)
817 else if (min_cdclk > 450000)
819 else if (min_cdclk > 337500)
826 static u8 skl_calc_voltage_level(int cdclk)
830 else if (cdclk > 450000)
832 else if (cdclk > 337500)
838 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
839 struct intel_cdclk_config *cdclk_config)
843 cdclk_config->ref = 24000;
844 cdclk_config->vco = 0;
846 val = intel_de_read(dev_priv, LCPLL1_CTL);
847 if ((val & LCPLL_PLL_ENABLE) == 0)
850 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
853 val = intel_de_read(dev_priv, DPLL_CTRL1);
855 if (drm_WARN_ON(&dev_priv->drm,
856 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
857 DPLL_CTRL1_SSC(SKL_DPLL0) |
858 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
859 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
862 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
863 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
864 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
865 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
866 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
867 cdclk_config->vco = 8100000;
869 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
870 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
871 cdclk_config->vco = 8640000;
874 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
879 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
880 struct intel_cdclk_config *cdclk_config)
884 skl_dpll0_update(dev_priv, cdclk_config);
886 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
888 if (cdclk_config->vco == 0)
891 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
893 if (cdclk_config->vco == 8640000) {
894 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
895 case CDCLK_FREQ_450_432:
896 cdclk_config->cdclk = 432000;
898 case CDCLK_FREQ_337_308:
899 cdclk_config->cdclk = 308571;
902 cdclk_config->cdclk = 540000;
904 case CDCLK_FREQ_675_617:
905 cdclk_config->cdclk = 617143;
908 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
912 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
913 case CDCLK_FREQ_450_432:
914 cdclk_config->cdclk = 450000;
916 case CDCLK_FREQ_337_308:
917 cdclk_config->cdclk = 337500;
920 cdclk_config->cdclk = 540000;
922 case CDCLK_FREQ_675_617:
923 cdclk_config->cdclk = 675000;
926 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
933 * Can't read this out :( Let's assume it's
934 * at least what the CDCLK frequency requires.
936 cdclk_config->voltage_level =
937 skl_calc_voltage_level(cdclk_config->cdclk);
940 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
941 static int skl_cdclk_decimal(int cdclk)
943 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
946 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
949 bool changed = dev_priv->skl_preferred_vco_freq != vco;
951 dev_priv->skl_preferred_vco_freq = vco;
954 intel_update_max_cdclk(dev_priv);
957 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
961 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
964 * We always enable DPLL0 with the lowest link rate possible, but still
965 * taking into account the VCO required to operate the eDP panel at the
966 * desired frequency. The usual DP link rates operate with a VCO of
967 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
968 * The modeset code is responsible for the selection of the exact link
969 * rate later on, with the constraint of choosing a frequency that
972 val = intel_de_read(dev_priv, DPLL_CTRL1);
974 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
975 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
976 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
978 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
981 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
984 intel_de_write(dev_priv, DPLL_CTRL1, val);
985 intel_de_posting_read(dev_priv, DPLL_CTRL1);
987 intel_de_write(dev_priv, LCPLL1_CTL,
988 intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE);
990 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
991 drm_err(&dev_priv->drm, "DPLL0 not locked\n");
993 dev_priv->cdclk.hw.vco = vco;
995 /* We'll want to keep using the current vco from now on. */
996 skl_set_preferred_cdclk_vco(dev_priv, vco);
999 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
1001 intel_de_write(dev_priv, LCPLL1_CTL,
1002 intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
1003 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1004 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
1006 dev_priv->cdclk.hw.vco = 0;
1009 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
1010 const struct intel_cdclk_config *cdclk_config,
1013 int cdclk = cdclk_config->cdclk;
1014 int vco = cdclk_config->vco;
1015 u32 freq_select, cdclk_ctl;
1019 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1020 * unsupported on SKL. In theory this should never happen since only
1021 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1022 * supported on SKL either, see the above WA. WARN whenever trying to
1023 * use the corresponding VCO freq as that always leads to using the
1024 * minimum 308MHz CDCLK.
1026 drm_WARN_ON_ONCE(&dev_priv->drm,
1027 IS_SKYLAKE(dev_priv) && vco == 8640000);
1029 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1030 SKL_CDCLK_PREPARE_FOR_CHANGE,
1031 SKL_CDCLK_READY_FOR_CHANGE,
1032 SKL_CDCLK_READY_FOR_CHANGE, 3);
1034 drm_err(&dev_priv->drm,
1035 "Failed to inform PCU about cdclk change (%d)\n", ret);
1039 /* Choose frequency for this cdclk */
1042 drm_WARN_ON(&dev_priv->drm,
1043 cdclk != dev_priv->cdclk.hw.bypass);
1044 drm_WARN_ON(&dev_priv->drm, vco != 0);
1048 freq_select = CDCLK_FREQ_337_308;
1052 freq_select = CDCLK_FREQ_450_432;
1055 freq_select = CDCLK_FREQ_540;
1059 freq_select = CDCLK_FREQ_675_617;
1063 if (dev_priv->cdclk.hw.vco != 0 &&
1064 dev_priv->cdclk.hw.vco != vco)
1065 skl_dpll0_disable(dev_priv);
1067 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
1069 if (dev_priv->cdclk.hw.vco != vco) {
1070 /* Wa Display #1183: skl,kbl,cfl */
1071 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1072 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1073 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1076 /* Wa Display #1183: skl,kbl,cfl */
1077 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1078 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1079 intel_de_posting_read(dev_priv, CDCLK_CTL);
1081 if (dev_priv->cdclk.hw.vco != vco)
1082 skl_dpll0_enable(dev_priv, vco);
1084 /* Wa Display #1183: skl,kbl,cfl */
1085 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1086 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1088 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1089 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1091 /* Wa Display #1183: skl,kbl,cfl */
1092 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1093 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1094 intel_de_posting_read(dev_priv, CDCLK_CTL);
1096 /* inform PCU of the change */
1097 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1098 cdclk_config->voltage_level);
1100 intel_update_cdclk(dev_priv);
1103 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1105 u32 cdctl, expected;
1108 * check if the pre-os initialized the display
1109 * There is SWF18 scratchpad register defined which is set by the
1110 * pre-os which can be used by the OS drivers to check the status
1112 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1115 intel_update_cdclk(dev_priv);
1116 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1118 /* Is PLL enabled and locked ? */
1119 if (dev_priv->cdclk.hw.vco == 0 ||
1120 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1123 /* DPLL okay; verify the cdclock
1125 * Noticed in some instances that the freq selection is correct but
1126 * decimal part is programmed wrong from BIOS where pre-os does not
1127 * enable display. Verify the same as well.
1129 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1130 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1131 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1132 if (cdctl == expected)
1133 /* All well; nothing to sanitize */
1137 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1139 /* force cdclk programming */
1140 dev_priv->cdclk.hw.cdclk = 0;
1141 /* force full PLL disable + enable */
1142 dev_priv->cdclk.hw.vco = -1;
1145 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
1147 struct intel_cdclk_config cdclk_config;
1149 skl_sanitize_cdclk(dev_priv);
1151 if (dev_priv->cdclk.hw.cdclk != 0 &&
1152 dev_priv->cdclk.hw.vco != 0) {
1154 * Use the current vco as our initial
1155 * guess as to what the preferred vco is.
1157 if (dev_priv->skl_preferred_vco_freq == 0)
1158 skl_set_preferred_cdclk_vco(dev_priv,
1159 dev_priv->cdclk.hw.vco);
1163 cdclk_config = dev_priv->cdclk.hw;
1165 cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
1166 if (cdclk_config.vco == 0)
1167 cdclk_config.vco = 8100000;
1168 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1169 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1171 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1174 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1176 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
1178 cdclk_config.cdclk = cdclk_config.bypass;
1179 cdclk_config.vco = 0;
1180 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1182 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1185 static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1186 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1187 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1188 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1189 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1190 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1194 static const struct intel_cdclk_vals glk_cdclk_table[] = {
1195 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1196 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1197 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1201 static const struct intel_cdclk_vals cnl_cdclk_table[] = {
1202 { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
1203 { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
1204 { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
1206 { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
1207 { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
1208 { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
1212 static const struct intel_cdclk_vals icl_cdclk_table[] = {
1213 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1214 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1215 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1216 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1217 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1218 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1220 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1221 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1222 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1223 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1224 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1225 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1227 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1228 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1229 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1230 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1231 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1232 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1236 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
1238 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1241 for (i = 0; table[i].refclk; i++)
1242 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1243 table[i].cdclk >= min_cdclk)
1244 return table[i].cdclk;
1246 drm_WARN(&dev_priv->drm, 1,
1247 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1248 min_cdclk, dev_priv->cdclk.hw.ref);
1252 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1254 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1257 if (cdclk == dev_priv->cdclk.hw.bypass)
1260 for (i = 0; table[i].refclk; i++)
1261 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1262 table[i].cdclk == cdclk)
1263 return dev_priv->cdclk.hw.ref * table[i].ratio;
1265 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1266 cdclk, dev_priv->cdclk.hw.ref);
1270 static u8 bxt_calc_voltage_level(int cdclk)
1272 return DIV_ROUND_UP(cdclk, 25000);
1275 static u8 cnl_calc_voltage_level(int cdclk)
1279 else if (cdclk > 168000)
1285 static u8 icl_calc_voltage_level(int cdclk)
1289 else if (cdclk > 312000)
1295 static u8 ehl_calc_voltage_level(int cdclk)
1299 else if (cdclk > 312000)
1301 else if (cdclk > 180000)
1307 static u8 tgl_calc_voltage_level(int cdclk)
1311 else if (cdclk > 326400)
1313 else if (cdclk > 312000)
1319 static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
1320 struct intel_cdclk_config *cdclk_config)
1322 if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1323 cdclk_config->ref = 24000;
1325 cdclk_config->ref = 19200;
1328 static void icl_readout_refclk(struct drm_i915_private *dev_priv,
1329 struct intel_cdclk_config *cdclk_config)
1331 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1337 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1338 cdclk_config->ref = 24000;
1340 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1341 cdclk_config->ref = 19200;
1343 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1344 cdclk_config->ref = 38400;
1349 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
1350 struct intel_cdclk_config *cdclk_config)
1354 if (INTEL_GEN(dev_priv) >= 11)
1355 icl_readout_refclk(dev_priv, cdclk_config);
1356 else if (IS_CANNONLAKE(dev_priv))
1357 cnl_readout_refclk(dev_priv, cdclk_config);
1359 cdclk_config->ref = 19200;
1361 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1362 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1363 (val & BXT_DE_PLL_LOCK) == 0) {
1365 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1366 * setting it to zero is a way to signal that.
1368 cdclk_config->vco = 0;
1373 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
1374 * it in a separate PLL control register.
1376 if (INTEL_GEN(dev_priv) >= 10)
1377 ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
1379 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1381 cdclk_config->vco = ratio * cdclk_config->ref;
1384 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1385 struct intel_cdclk_config *cdclk_config)
1390 bxt_de_pll_readout(dev_priv, cdclk_config);
1392 if (INTEL_GEN(dev_priv) >= 12)
1393 cdclk_config->bypass = cdclk_config->ref / 2;
1394 else if (INTEL_GEN(dev_priv) >= 11)
1395 cdclk_config->bypass = 50000;
1397 cdclk_config->bypass = cdclk_config->ref;
1399 if (cdclk_config->vco == 0) {
1400 cdclk_config->cdclk = cdclk_config->bypass;
1404 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1407 case BXT_CDCLK_CD2X_DIV_SEL_1:
1410 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1411 drm_WARN(&dev_priv->drm,
1412 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
1413 "Unsupported divider\n");
1416 case BXT_CDCLK_CD2X_DIV_SEL_2:
1419 case BXT_CDCLK_CD2X_DIV_SEL_4:
1420 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,
1421 "Unsupported divider\n");
1425 MISSING_CASE(divider);
1429 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1433 * Can't read this out :( Let's assume it's
1434 * at least what the CDCLK frequency requires.
1436 cdclk_config->voltage_level =
1437 dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
1440 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1442 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
1445 if (intel_de_wait_for_clear(dev_priv,
1446 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1447 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
1449 dev_priv->cdclk.hw.vco = 0;
1452 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1454 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1457 val = intel_de_read(dev_priv, BXT_DE_PLL_CTL);
1458 val &= ~BXT_DE_PLL_RATIO_MASK;
1459 val |= BXT_DE_PLL_RATIO(ratio);
1460 intel_de_write(dev_priv, BXT_DE_PLL_CTL, val);
1462 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1465 if (intel_de_wait_for_set(dev_priv,
1466 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1467 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
1469 dev_priv->cdclk.hw.vco = vco;
1472 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1476 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1477 val &= ~BXT_DE_PLL_PLL_ENABLE;
1478 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1481 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1482 drm_err(&dev_priv->drm,
1483 "timeout waiting for CDCLK PLL unlock\n");
1485 dev_priv->cdclk.hw.vco = 0;
1488 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1490 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1493 val = CNL_CDCLK_PLL_RATIO(ratio);
1494 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1496 val |= BXT_DE_PLL_PLL_ENABLE;
1497 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1500 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1501 drm_err(&dev_priv->drm,
1502 "timeout waiting for CDCLK PLL lock\n");
1504 dev_priv->cdclk.hw.vco = vco;
1507 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1509 if (INTEL_GEN(dev_priv) >= 12) {
1510 if (pipe == INVALID_PIPE)
1511 return TGL_CDCLK_CD2X_PIPE_NONE;
1513 return TGL_CDCLK_CD2X_PIPE(pipe);
1514 } else if (INTEL_GEN(dev_priv) >= 11) {
1515 if (pipe == INVALID_PIPE)
1516 return ICL_CDCLK_CD2X_PIPE_NONE;
1518 return ICL_CDCLK_CD2X_PIPE(pipe);
1520 if (pipe == INVALID_PIPE)
1521 return BXT_CDCLK_CD2X_PIPE_NONE;
1523 return BXT_CDCLK_CD2X_PIPE(pipe);
1527 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1528 const struct intel_cdclk_config *cdclk_config,
1531 int cdclk = cdclk_config->cdclk;
1532 int vco = cdclk_config->vco;
1536 /* Inform power controller of upcoming frequency change. */
1537 if (INTEL_GEN(dev_priv) >= 10)
1538 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1539 SKL_CDCLK_PREPARE_FOR_CHANGE,
1540 SKL_CDCLK_READY_FOR_CHANGE,
1541 SKL_CDCLK_READY_FOR_CHANGE, 3);
1544 * BSpec requires us to wait up to 150usec, but that leads to
1545 * timeouts; the 2ms used here is based on experiment.
1547 ret = sandybridge_pcode_write_timeout(dev_priv,
1548 HSW_PCODE_DE_WRITE_FREQ_REQ,
1549 0x80000000, 150, 2);
1552 drm_err(&dev_priv->drm,
1553 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
1558 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1559 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1561 drm_WARN_ON(&dev_priv->drm,
1562 cdclk != dev_priv->cdclk.hw.bypass);
1563 drm_WARN_ON(&dev_priv->drm, vco != 0);
1566 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1569 drm_WARN(&dev_priv->drm,
1570 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
1571 "Unsupported divider\n");
1572 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1575 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1578 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,
1579 "Unsupported divider\n");
1580 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1584 if (INTEL_GEN(dev_priv) >= 10) {
1585 if (dev_priv->cdclk.hw.vco != 0 &&
1586 dev_priv->cdclk.hw.vco != vco)
1587 cnl_cdclk_pll_disable(dev_priv);
1589 if (dev_priv->cdclk.hw.vco != vco)
1590 cnl_cdclk_pll_enable(dev_priv, vco);
1593 if (dev_priv->cdclk.hw.vco != 0 &&
1594 dev_priv->cdclk.hw.vco != vco)
1595 bxt_de_pll_disable(dev_priv);
1597 if (dev_priv->cdclk.hw.vco != vco)
1598 bxt_de_pll_enable(dev_priv, vco);
1601 val = divider | skl_cdclk_decimal(cdclk) |
1602 bxt_cdclk_cd2x_pipe(dev_priv, pipe);
1605 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1608 if (IS_GEN9_LP(dev_priv) && cdclk >= 500000)
1609 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1610 intel_de_write(dev_priv, CDCLK_CTL, val);
1612 if (pipe != INVALID_PIPE)
1613 intel_wait_for_vblank(dev_priv, pipe);
1615 if (INTEL_GEN(dev_priv) >= 10) {
1616 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1617 cdclk_config->voltage_level);
1620 * The timeout isn't specified, the 2ms used here is based on
1622 * FIXME: Waiting for the request completion could be delayed
1623 * until the next PCODE request based on BSpec.
1625 ret = sandybridge_pcode_write_timeout(dev_priv,
1626 HSW_PCODE_DE_WRITE_FREQ_REQ,
1627 cdclk_config->voltage_level,
1632 drm_err(&dev_priv->drm,
1633 "PCode CDCLK freq set failed, (err %d, freq %d)\n",
1638 intel_update_cdclk(dev_priv);
1640 if (INTEL_GEN(dev_priv) >= 10)
1642 * Can't read out the voltage level :(
1643 * Let's just assume everything is as expected.
1645 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
1648 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1650 u32 cdctl, expected;
1653 intel_update_cdclk(dev_priv);
1654 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1656 if (dev_priv->cdclk.hw.vco == 0 ||
1657 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1660 /* DPLL okay; verify the cdclock
1662 * Some BIOS versions leave an incorrect decimal frequency value and
1663 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1664 * so sanitize this register.
1666 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1668 * Let's ignore the pipe field, since BIOS could have configured the
1669 * dividers both synching to an active pipe, or asynchronously
1672 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
1674 /* Make sure this is a legal cdclk value for the platform */
1675 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
1676 if (cdclk != dev_priv->cdclk.hw.cdclk)
1679 /* Make sure the VCO is correct for the cdclk */
1680 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
1681 if (vco != dev_priv->cdclk.hw.vco)
1684 expected = skl_cdclk_decimal(cdclk);
1686 /* Figure out what CD2X divider we should be using for this cdclk */
1687 switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco,
1688 dev_priv->cdclk.hw.cdclk)) {
1690 expected |= BXT_CDCLK_CD2X_DIV_SEL_1;
1693 expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5;
1696 expected |= BXT_CDCLK_CD2X_DIV_SEL_2;
1699 expected |= BXT_CDCLK_CD2X_DIV_SEL_4;
1706 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1709 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000)
1710 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1712 if (cdctl == expected)
1713 /* All well; nothing to sanitize */
1717 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1719 /* force cdclk programming */
1720 dev_priv->cdclk.hw.cdclk = 0;
1722 /* force full PLL disable + enable */
1723 dev_priv->cdclk.hw.vco = -1;
1726 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
1728 struct intel_cdclk_config cdclk_config;
1730 bxt_sanitize_cdclk(dev_priv);
1732 if (dev_priv->cdclk.hw.cdclk != 0 &&
1733 dev_priv->cdclk.hw.vco != 0)
1736 cdclk_config = dev_priv->cdclk.hw;
1740 * - The initial CDCLK needs to be read from VBT.
1741 * Need to make this change after VBT has changes for BXT.
1743 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
1744 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
1745 cdclk_config.voltage_level =
1746 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
1748 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1751 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1753 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
1755 cdclk_config.cdclk = cdclk_config.bypass;
1756 cdclk_config.vco = 0;
1757 cdclk_config.voltage_level =
1758 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
1760 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1764 * intel_cdclk_init_hw - Initialize CDCLK hardware
1765 * @i915: i915 device
1767 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
1768 * sanitizing the state of the hardware if needed. This is generally done only
1769 * during the display core initialization sequence, after which the DMC will
1770 * take care of turning CDCLK off/on as needed.
1772 void intel_cdclk_init_hw(struct drm_i915_private *i915)
1774 if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
1775 bxt_cdclk_init_hw(i915);
1776 else if (IS_GEN9_BC(i915))
1777 skl_cdclk_init_hw(i915);
1781 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
1782 * @i915: i915 device
1784 * Uninitialize CDCLK. This is done only during the display core
1785 * uninitialization sequence.
1787 void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
1789 if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
1790 bxt_cdclk_uninit_hw(i915);
1791 else if (IS_GEN9_BC(i915))
1792 skl_cdclk_uninit_hw(i915);
1796 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
1797 * configurations requires a modeset on all pipes
1798 * @a: first CDCLK configuration
1799 * @b: second CDCLK configuration
1802 * True if changing between the two CDCLK configurations
1803 * requires all pipes to be off, false if not.
1805 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
1806 const struct intel_cdclk_config *b)
1808 return a->cdclk != b->cdclk ||
1814 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
1815 * configurations requires only a cd2x divider update
1816 * @dev_priv: i915 device
1817 * @a: first CDCLK configuration
1818 * @b: second CDCLK configuration
1821 * True if changing between the two CDCLK configurations
1822 * can be done with just a cd2x divider update, false if not.
1824 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
1825 const struct intel_cdclk_config *a,
1826 const struct intel_cdclk_config *b)
1828 /* Older hw doesn't have the capability */
1829 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
1832 return a->cdclk != b->cdclk &&
1838 * intel_cdclk_changed - Determine if two CDCLK configurations are different
1839 * @a: first CDCLK configuration
1840 * @b: second CDCLK configuration
1843 * True if the CDCLK configurations don't match, false if they do.
1845 static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
1846 const struct intel_cdclk_config *b)
1848 return intel_cdclk_needs_modeset(a, b) ||
1849 a->voltage_level != b->voltage_level;
1852 void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
1853 const char *context)
1855 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
1856 context, cdclk_config->cdclk, cdclk_config->vco,
1857 cdclk_config->ref, cdclk_config->bypass,
1858 cdclk_config->voltage_level);
1862 * intel_set_cdclk - Push the CDCLK configuration to the hardware
1863 * @dev_priv: i915 device
1864 * @cdclk_config: new CDCLK configuration
1865 * @pipe: pipe with which to synchronize the update
1867 * Program the hardware based on the passed in CDCLK state,
1870 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
1871 const struct intel_cdclk_config *cdclk_config,
1874 struct intel_encoder *encoder;
1876 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
1879 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
1882 intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
1885 * Lock aux/gmbus while we change cdclk in case those
1886 * functions use cdclk. Not all platforms/ports do,
1887 * but we'll lock them all for simplicity.
1889 mutex_lock(&dev_priv->gmbus_mutex);
1890 for_each_intel_dp(&dev_priv->drm, encoder) {
1891 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1893 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
1894 &dev_priv->gmbus_mutex);
1897 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
1899 for_each_intel_dp(&dev_priv->drm, encoder) {
1900 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1902 mutex_unlock(&intel_dp->aux.hw_mutex);
1904 mutex_unlock(&dev_priv->gmbus_mutex);
1906 if (drm_WARN(&dev_priv->drm,
1907 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
1908 "cdclk state doesn't match!\n")) {
1909 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
1910 intel_dump_cdclk_config(cdclk_config, "[sw state]");
1915 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
1916 * @state: intel atomic state
1918 * Program the hardware before updating the HW plane state based on the
1919 * new CDCLK state, if necessary.
1922 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
1924 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1925 const struct intel_cdclk_state *old_cdclk_state =
1926 intel_atomic_get_old_cdclk_state(state);
1927 const struct intel_cdclk_state *new_cdclk_state =
1928 intel_atomic_get_new_cdclk_state(state);
1929 enum pipe pipe = new_cdclk_state->pipe;
1931 if (!intel_cdclk_changed(&old_cdclk_state->actual,
1932 &new_cdclk_state->actual))
1935 if (pipe == INVALID_PIPE ||
1936 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
1937 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
1939 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
1944 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
1945 * @state: intel atomic state
1947 * Program the hardware after updating the HW plane state based on the
1948 * new CDCLK state, if necessary.
1951 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
1953 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1954 const struct intel_cdclk_state *old_cdclk_state =
1955 intel_atomic_get_old_cdclk_state(state);
1956 const struct intel_cdclk_state *new_cdclk_state =
1957 intel_atomic_get_new_cdclk_state(state);
1958 enum pipe pipe = new_cdclk_state->pipe;
1960 if (!intel_cdclk_changed(&old_cdclk_state->actual,
1961 &new_cdclk_state->actual))
1964 if (pipe != INVALID_PIPE &&
1965 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
1966 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
1968 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
1972 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
1974 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1975 int pixel_rate = crtc_state->pixel_rate;
1977 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1978 return DIV_ROUND_UP(pixel_rate, 2);
1979 else if (IS_GEN(dev_priv, 9) ||
1980 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1982 else if (IS_CHERRYVIEW(dev_priv))
1983 return DIV_ROUND_UP(pixel_rate * 100, 95);
1984 else if (crtc_state->double_wide)
1985 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
1987 return DIV_ROUND_UP(pixel_rate * 100, 90);
1990 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
1992 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1994 struct intel_plane *plane;
1997 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1998 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
2003 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2005 struct drm_i915_private *dev_priv =
2006 to_i915(crtc_state->uapi.crtc->dev);
2009 if (!crtc_state->hw.enable)
2012 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2014 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2015 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2016 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2018 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2019 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2020 * there may be audio corruption or screen corruption." This cdclk
2021 * restriction for GLK is 316.8 MHz.
2023 if (intel_crtc_has_dp_encoder(crtc_state) &&
2024 crtc_state->has_audio &&
2025 crtc_state->port_clock >= 540000 &&
2026 crtc_state->lane_count == 4) {
2027 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2028 /* Display WA #1145: glk,cnl */
2029 min_cdclk = max(316800, min_cdclk);
2030 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
2031 /* Display WA #1144: skl,bxt */
2032 min_cdclk = max(432000, min_cdclk);
2037 * According to BSpec, "The CD clock frequency must be at least twice
2038 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2040 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
2041 min_cdclk = max(2 * 96000, min_cdclk);
2044 * "For DP audio configuration, cdclk frequency shall be set to
2045 * meet the following requirements:
2046 * DP Link Frequency(MHz) | Cdclk frequency(MHz)
2047 * 270 | 320 or higher
2048 * 162 | 200 or higher"
2050 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2051 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2052 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2055 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2058 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2059 IS_VALLEYVIEW(dev_priv))
2060 min_cdclk = max(320000, min_cdclk);
2063 * On Geminilake once the CDCLK gets as low as 79200
2064 * picture gets unstable, despite that values are
2065 * correct for DSI PLL and DE PLL.
2067 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2068 IS_GEMINILAKE(dev_priv))
2069 min_cdclk = max(158400, min_cdclk);
2071 /* Account for additional needs from the planes */
2072 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2075 * HACK. Currently for TGL platforms we calculate
2076 * min_cdclk initially based on pixel_rate divided
2077 * by 2, accounting for also plane requirements,
2078 * however in some cases the lowest possible CDCLK
2079 * doesn't work and causing the underruns.
2080 * Explicitly stating here that this seems to be currently
2081 * rather a Hack, than final solution.
2083 if (IS_TIGERLAKE(dev_priv)) {
2085 * Clamp to max_cdclk_freq in case pixel rate is higher,
2086 * in order not to break an 8K, but still leave W/A at place.
2088 min_cdclk = max_t(int, min_cdclk,
2089 min_t(int, crtc_state->pixel_rate,
2090 dev_priv->max_cdclk_freq));
2093 if (min_cdclk > dev_priv->max_cdclk_freq) {
2094 drm_dbg_kms(&dev_priv->drm,
2095 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2096 min_cdclk, dev_priv->max_cdclk_freq);
2103 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
2105 struct intel_atomic_state *state = cdclk_state->base.state;
2106 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2107 struct intel_bw_state *bw_state = NULL;
2108 struct intel_crtc *crtc;
2109 struct intel_crtc_state *crtc_state;
2113 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2116 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2120 bw_state = intel_atomic_get_bw_state(state);
2121 if (IS_ERR(bw_state))
2122 return PTR_ERR(bw_state);
2124 if (cdclk_state->min_cdclk[i] == min_cdclk)
2127 cdclk_state->min_cdclk[i] = min_cdclk;
2129 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2134 min_cdclk = cdclk_state->force_min_cdclk;
2135 for_each_pipe(dev_priv, pipe) {
2136 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
2141 min_cdclk = max(bw_state->min_cdclk, min_cdclk);
2148 * Account for port clock min voltage level requirements.
2149 * This only really does something on CNL+ but can be
2150 * called on earlier platforms as well.
2152 * Note that this functions assumes that 0 is
2153 * the lowest voltage value, and higher values
2154 * correspond to increasingly higher voltages.
2156 * Should that relationship no longer hold on
2157 * future platforms this code will need to be
2160 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
2162 struct intel_atomic_state *state = cdclk_state->base.state;
2163 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2164 struct intel_crtc *crtc;
2165 struct intel_crtc_state *crtc_state;
2166 u8 min_voltage_level;
2170 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2173 if (crtc_state->hw.enable)
2174 min_voltage_level = crtc_state->min_voltage_level;
2176 min_voltage_level = 0;
2178 if (cdclk_state->min_voltage_level[i] == min_voltage_level)
2181 cdclk_state->min_voltage_level[i] = min_voltage_level;
2183 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2188 min_voltage_level = 0;
2189 for_each_pipe(dev_priv, pipe)
2190 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
2193 return min_voltage_level;
2196 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2198 struct intel_atomic_state *state = cdclk_state->base.state;
2199 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2200 int min_cdclk, cdclk;
2202 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2206 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2208 cdclk_state->logical.cdclk = cdclk;
2209 cdclk_state->logical.voltage_level =
2210 vlv_calc_voltage_level(dev_priv, cdclk);
2212 if (!cdclk_state->active_pipes) {
2213 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2215 cdclk_state->actual.cdclk = cdclk;
2216 cdclk_state->actual.voltage_level =
2217 vlv_calc_voltage_level(dev_priv, cdclk);
2219 cdclk_state->actual = cdclk_state->logical;
2225 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2227 int min_cdclk, cdclk;
2229 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2234 * FIXME should also account for plane ratio
2235 * once 64bpp pixel formats are supported.
2237 cdclk = bdw_calc_cdclk(min_cdclk);
2239 cdclk_state->logical.cdclk = cdclk;
2240 cdclk_state->logical.voltage_level =
2241 bdw_calc_voltage_level(cdclk);
2243 if (!cdclk_state->active_pipes) {
2244 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2246 cdclk_state->actual.cdclk = cdclk;
2247 cdclk_state->actual.voltage_level =
2248 bdw_calc_voltage_level(cdclk);
2250 cdclk_state->actual = cdclk_state->logical;
2256 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
2258 struct intel_atomic_state *state = cdclk_state->base.state;
2259 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2260 struct intel_crtc *crtc;
2261 struct intel_crtc_state *crtc_state;
2264 vco = cdclk_state->logical.vco;
2266 vco = dev_priv->skl_preferred_vco_freq;
2268 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2269 if (!crtc_state->hw.enable)
2272 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2276 * DPLL0 VCO may need to be adjusted to get the correct
2277 * clock for eDP. This will affect cdclk as well.
2279 switch (crtc_state->port_clock / 2) {
2293 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2295 int min_cdclk, cdclk, vco;
2297 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2301 vco = skl_dpll0_vco(cdclk_state);
2304 * FIXME should also account for plane ratio
2305 * once 64bpp pixel formats are supported.
2307 cdclk = skl_calc_cdclk(min_cdclk, vco);
2309 cdclk_state->logical.vco = vco;
2310 cdclk_state->logical.cdclk = cdclk;
2311 cdclk_state->logical.voltage_level =
2312 skl_calc_voltage_level(cdclk);
2314 if (!cdclk_state->active_pipes) {
2315 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
2317 cdclk_state->actual.vco = vco;
2318 cdclk_state->actual.cdclk = cdclk;
2319 cdclk_state->actual.voltage_level =
2320 skl_calc_voltage_level(cdclk);
2322 cdclk_state->actual = cdclk_state->logical;
2328 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2330 struct intel_atomic_state *state = cdclk_state->base.state;
2331 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2332 int min_cdclk, min_voltage_level, cdclk, vco;
2334 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2338 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
2339 if (min_voltage_level < 0)
2340 return min_voltage_level;
2342 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
2343 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2345 cdclk_state->logical.vco = vco;
2346 cdclk_state->logical.cdclk = cdclk;
2347 cdclk_state->logical.voltage_level =
2348 max_t(int, min_voltage_level,
2349 dev_priv->display.calc_voltage_level(cdclk));
2351 if (!cdclk_state->active_pipes) {
2352 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2353 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2355 cdclk_state->actual.vco = vco;
2356 cdclk_state->actual.cdclk = cdclk;
2357 cdclk_state->actual.voltage_level =
2358 dev_priv->display.calc_voltage_level(cdclk);
2360 cdclk_state->actual = cdclk_state->logical;
2366 static int intel_modeset_all_pipes(struct intel_atomic_state *state)
2368 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2369 struct intel_crtc *crtc;
2372 * Add all pipes to the state, and force
2373 * a modeset on all the active ones.
2375 for_each_intel_crtc(&dev_priv->drm, crtc) {
2376 struct intel_crtc_state *crtc_state;
2379 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
2380 if (IS_ERR(crtc_state))
2381 return PTR_ERR(crtc_state);
2383 if (!crtc_state->hw.active ||
2384 drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
2387 crtc_state->uapi.mode_changed = true;
2389 ret = drm_atomic_add_affected_connectors(&state->base,
2394 ret = drm_atomic_add_affected_planes(&state->base,
2399 crtc_state->update_planes |= crtc_state->active_planes;
2405 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2410 * We can't change the cdclk frequency, but we still want to
2411 * check that the required minimum frequency doesn't exceed
2412 * the actual cdclk frequency.
2414 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2421 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
2423 struct intel_cdclk_state *cdclk_state;
2425 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
2429 cdclk_state->pipe = INVALID_PIPE;
2431 return &cdclk_state->base;
2434 static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
2435 struct intel_global_state *state)
2440 static const struct intel_global_state_funcs intel_cdclk_funcs = {
2441 .atomic_duplicate_state = intel_cdclk_duplicate_state,
2442 .atomic_destroy_state = intel_cdclk_destroy_state,
2445 struct intel_cdclk_state *
2446 intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
2448 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2449 struct intel_global_state *cdclk_state;
2451 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
2452 if (IS_ERR(cdclk_state))
2453 return ERR_CAST(cdclk_state);
2455 return to_intel_cdclk_state(cdclk_state);
2458 int intel_cdclk_init(struct drm_i915_private *dev_priv)
2460 struct intel_cdclk_state *cdclk_state;
2462 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
2466 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
2467 &cdclk_state->base, &intel_cdclk_funcs);
2472 int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
2474 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2475 const struct intel_cdclk_state *old_cdclk_state;
2476 struct intel_cdclk_state *new_cdclk_state;
2480 new_cdclk_state = intel_atomic_get_cdclk_state(state);
2481 if (IS_ERR(new_cdclk_state))
2482 return PTR_ERR(new_cdclk_state);
2484 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
2486 new_cdclk_state->active_pipes =
2487 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
2489 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
2493 if (intel_cdclk_changed(&old_cdclk_state->actual,
2494 &new_cdclk_state->actual)) {
2496 * Also serialize commits across all crtcs
2497 * if the actual hw needs to be poked.
2499 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
2502 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
2503 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
2504 intel_cdclk_changed(&old_cdclk_state->logical,
2505 &new_cdclk_state->logical)) {
2506 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
2513 if (is_power_of_2(new_cdclk_state->active_pipes) &&
2514 intel_cdclk_can_cd2x_update(dev_priv,
2515 &old_cdclk_state->actual,
2516 &new_cdclk_state->actual)) {
2517 struct intel_crtc *crtc;
2518 struct intel_crtc_state *crtc_state;
2520 pipe = ilog2(new_cdclk_state->active_pipes);
2521 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
2523 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
2524 if (IS_ERR(crtc_state))
2525 return PTR_ERR(crtc_state);
2527 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
2528 pipe = INVALID_PIPE;
2530 pipe = INVALID_PIPE;
2533 if (pipe != INVALID_PIPE) {
2534 new_cdclk_state->pipe = pipe;
2536 drm_dbg_kms(&dev_priv->drm,
2537 "Can change cdclk with pipe %c active\n",
2539 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
2540 &new_cdclk_state->actual)) {
2541 /* All pipes must be switched off while we change the cdclk. */
2542 ret = intel_modeset_all_pipes(state);
2546 new_cdclk_state->pipe = INVALID_PIPE;
2548 drm_dbg_kms(&dev_priv->drm,
2549 "Modeset required for cdclk change\n");
2552 drm_dbg_kms(&dev_priv->drm,
2553 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
2554 new_cdclk_state->logical.cdclk,
2555 new_cdclk_state->actual.cdclk);
2556 drm_dbg_kms(&dev_priv->drm,
2557 "New voltage level calculated to be logical %u, actual %u\n",
2558 new_cdclk_state->logical.voltage_level,
2559 new_cdclk_state->actual.voltage_level);
2564 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2566 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2568 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2569 return 2 * max_cdclk_freq;
2570 else if (IS_GEN(dev_priv, 9) ||
2571 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2572 return max_cdclk_freq;
2573 else if (IS_CHERRYVIEW(dev_priv))
2574 return max_cdclk_freq*95/100;
2575 else if (INTEL_GEN(dev_priv) < 4)
2576 return 2*max_cdclk_freq*90/100;
2578 return max_cdclk_freq*90/100;
2582 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2583 * @dev_priv: i915 device
2585 * Determine the maximum CDCLK frequency the platform supports, and also
2586 * derive the maximum dot clock frequency the maximum CDCLK frequency
2589 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2591 if (IS_ELKHARTLAKE(dev_priv)) {
2592 if (dev_priv->cdclk.hw.ref == 24000)
2593 dev_priv->max_cdclk_freq = 552000;
2595 dev_priv->max_cdclk_freq = 556800;
2596 } else if (INTEL_GEN(dev_priv) >= 11) {
2597 if (dev_priv->cdclk.hw.ref == 24000)
2598 dev_priv->max_cdclk_freq = 648000;
2600 dev_priv->max_cdclk_freq = 652800;
2601 } else if (IS_CANNONLAKE(dev_priv)) {
2602 dev_priv->max_cdclk_freq = 528000;
2603 } else if (IS_GEN9_BC(dev_priv)) {
2604 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2607 vco = dev_priv->skl_preferred_vco_freq;
2608 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
2611 * Use the lower (vco 8640) cdclk values as a
2612 * first guess. skl_calc_cdclk() will correct it
2613 * if the preferred vco is 8100 instead.
2615 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2617 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2619 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2624 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2625 } else if (IS_GEMINILAKE(dev_priv)) {
2626 dev_priv->max_cdclk_freq = 316800;
2627 } else if (IS_BROXTON(dev_priv)) {
2628 dev_priv->max_cdclk_freq = 624000;
2629 } else if (IS_BROADWELL(dev_priv)) {
2631 * FIXME with extra cooling we can allow
2632 * 540 MHz for ULX and 675 Mhz for ULT.
2633 * How can we know if extra cooling is
2634 * available? PCI ID, VTB, something else?
2636 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
2637 dev_priv->max_cdclk_freq = 450000;
2638 else if (IS_BDW_ULX(dev_priv))
2639 dev_priv->max_cdclk_freq = 450000;
2640 else if (IS_BDW_ULT(dev_priv))
2641 dev_priv->max_cdclk_freq = 540000;
2643 dev_priv->max_cdclk_freq = 675000;
2644 } else if (IS_CHERRYVIEW(dev_priv)) {
2645 dev_priv->max_cdclk_freq = 320000;
2646 } else if (IS_VALLEYVIEW(dev_priv)) {
2647 dev_priv->max_cdclk_freq = 400000;
2649 /* otherwise assume cdclk is fixed */
2650 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2653 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2655 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
2656 dev_priv->max_cdclk_freq);
2658 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
2659 dev_priv->max_dotclk_freq);
2663 * intel_update_cdclk - Determine the current CDCLK frequency
2664 * @dev_priv: i915 device
2666 * Determine the current CDCLK frequency.
2668 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2670 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2673 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2674 * Programmng [sic] note: bit[9:2] should be programmed to the number
2675 * of cdclk that generates 4MHz reference clock freq which is used to
2676 * generate GMBus clock. This will vary with the cdclk freq.
2678 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2679 intel_de_write(dev_priv, GMBUSFREQ_VLV,
2680 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2683 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2686 int divider, fraction;
2688 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2698 rawclk = CNP_RAWCLK_DIV(divider / 1000);
2702 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2704 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2705 rawclk |= ICP_RAWCLK_NUM(numerator);
2708 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
2709 return divider + fraction;
2712 static int pch_rawclk(struct drm_i915_private *dev_priv)
2714 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2717 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2719 /* RAWCLK_FREQ_VLV register updated from power well code */
2720 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2721 CCK_DISPLAY_REF_CLOCK_CONTROL);
2724 static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
2729 * hrawclock is 1/4 the FSB frequency
2731 * Note that this only reads the state of the FSB
2732 * straps, not the actual FSB frequency. Some BIOSen
2733 * let you configure each independently. Ideally we'd
2734 * read out the actual FSB frequency but sadly we
2735 * don't know which registers have that information,
2736 * and all the relevant docs have gone to bit heaven :(
2738 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
2740 if (IS_MOBILE(dev_priv)) {
2742 case CLKCFG_FSB_400:
2744 case CLKCFG_FSB_533:
2746 case CLKCFG_FSB_667:
2748 case CLKCFG_FSB_800:
2750 case CLKCFG_FSB_1067:
2752 case CLKCFG_FSB_1333:
2755 MISSING_CASE(clkcfg);
2760 case CLKCFG_FSB_400_ALT:
2762 case CLKCFG_FSB_533:
2764 case CLKCFG_FSB_667:
2766 case CLKCFG_FSB_800:
2768 case CLKCFG_FSB_1067_ALT:
2770 case CLKCFG_FSB_1333_ALT:
2772 case CLKCFG_FSB_1600_ALT:
2781 * intel_read_rawclk - Determine the current RAWCLK frequency
2782 * @dev_priv: i915 device
2784 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2785 * frequency clock so this needs to done only once.
2787 u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
2791 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
2792 freq = cnp_rawclk(dev_priv);
2793 else if (HAS_PCH_SPLIT(dev_priv))
2794 freq = pch_rawclk(dev_priv);
2795 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2796 freq = vlv_hrawclk(dev_priv);
2797 else if (INTEL_GEN(dev_priv) >= 3)
2798 freq = i9xx_hrawclk(dev_priv);
2800 /* no rawclk on other platforms, or no need to know it */
2807 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2808 * @dev_priv: i915 device
2810 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2812 if (INTEL_GEN(dev_priv) >= 12) {
2813 dev_priv->display.set_cdclk = bxt_set_cdclk;
2814 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2815 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2816 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
2817 dev_priv->cdclk.table = icl_cdclk_table;
2818 } else if (IS_ELKHARTLAKE(dev_priv)) {
2819 dev_priv->display.set_cdclk = bxt_set_cdclk;
2820 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2821 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2822 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
2823 dev_priv->cdclk.table = icl_cdclk_table;
2824 } else if (INTEL_GEN(dev_priv) >= 11) {
2825 dev_priv->display.set_cdclk = bxt_set_cdclk;
2826 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2827 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2828 dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
2829 dev_priv->cdclk.table = icl_cdclk_table;
2830 } else if (IS_CANNONLAKE(dev_priv)) {
2831 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2832 dev_priv->display.set_cdclk = bxt_set_cdclk;
2833 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2834 dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
2835 dev_priv->cdclk.table = cnl_cdclk_table;
2836 } else if (IS_GEN9_LP(dev_priv)) {
2837 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2838 dev_priv->display.set_cdclk = bxt_set_cdclk;
2839 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2840 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
2841 if (IS_GEMINILAKE(dev_priv))
2842 dev_priv->cdclk.table = glk_cdclk_table;
2844 dev_priv->cdclk.table = bxt_cdclk_table;
2845 } else if (IS_GEN9_BC(dev_priv)) {
2846 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2847 dev_priv->display.set_cdclk = skl_set_cdclk;
2848 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
2849 } else if (IS_BROADWELL(dev_priv)) {
2850 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2851 dev_priv->display.set_cdclk = bdw_set_cdclk;
2852 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
2853 } else if (IS_CHERRYVIEW(dev_priv)) {
2854 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2855 dev_priv->display.set_cdclk = chv_set_cdclk;
2856 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2857 } else if (IS_VALLEYVIEW(dev_priv)) {
2858 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2859 dev_priv->display.set_cdclk = vlv_set_cdclk;
2860 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2862 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2863 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
2866 if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))
2867 dev_priv->display.get_cdclk = bxt_get_cdclk;
2868 else if (IS_GEN9_BC(dev_priv))
2869 dev_priv->display.get_cdclk = skl_get_cdclk;
2870 else if (IS_BROADWELL(dev_priv))
2871 dev_priv->display.get_cdclk = bdw_get_cdclk;
2872 else if (IS_HASWELL(dev_priv))
2873 dev_priv->display.get_cdclk = hsw_get_cdclk;
2874 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2875 dev_priv->display.get_cdclk = vlv_get_cdclk;
2876 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
2877 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2878 else if (IS_GEN(dev_priv, 5))
2879 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2880 else if (IS_GM45(dev_priv))
2881 dev_priv->display.get_cdclk = gm45_get_cdclk;
2882 else if (IS_G45(dev_priv))
2883 dev_priv->display.get_cdclk = g33_get_cdclk;
2884 else if (IS_I965GM(dev_priv))
2885 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2886 else if (IS_I965G(dev_priv))
2887 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2888 else if (IS_PINEVIEW(dev_priv))
2889 dev_priv->display.get_cdclk = pnv_get_cdclk;
2890 else if (IS_G33(dev_priv))
2891 dev_priv->display.get_cdclk = g33_get_cdclk;
2892 else if (IS_I945GM(dev_priv))
2893 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2894 else if (IS_I945G(dev_priv))
2895 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2896 else if (IS_I915GM(dev_priv))
2897 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2898 else if (IS_I915G(dev_priv))
2899 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2900 else if (IS_I865G(dev_priv))
2901 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2902 else if (IS_I85X(dev_priv))
2903 dev_priv->display.get_cdclk = i85x_get_cdclk;
2904 else if (IS_I845G(dev_priv))
2905 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2906 else if (IS_I830(dev_priv))
2907 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2909 if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,
2910 "Unknown platform. Assuming 133 MHz CDCLK\n"))
2911 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;