display/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/component.h>
  25 #include <linux/kernel.h>
  26
  27 #include <drm/drm_edid.h>
  28 #include <drm/i915_component.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_atomic.h"
  32 #include "intel_audio.h"
  33 #include "intel_cdclk.h"
  34 #include "intel_display_types.h"
  35 #include "intel_lpe_audio.h"
  36
  37 /**
  38  * DOC: High Definition Audio over HDMI and Display Port
  39  *
  40  * The graphics and audio drivers together support High Definition Audio over
  41  * HDMI and Display Port. The audio programming sequences are divided into audio
  42  * codec and controller enable and disable sequences. The graphics driver
  43  * handles the audio codec sequences, while the audio driver handles the audio
  44  * controller sequences.
  45  *
  46  * The disable sequences must be performed before disabling the transcoder or
  47  * port. The enable sequences may only be performed after enabling the
  48  * transcoder and port, and after completed link training. Therefore the audio
  49  * enable/disable sequences are part of the modeset sequence.
  50  *
  51  * The codec and controller sequences could be done either parallel or serial,
  52  * but generally the ELDV/PD change in the codec sequence indicates to the audio
  53  * driver that the controller sequence should start. Indeed, most of the
  54  * co-operation between the graphics and audio drivers is handled via audio
  55  * related registers. (The notable exception is the power management, not
  56  * covered here.)
  57  *
  58  * The struct &i915_audio_component is used to interact between the graphics
  59  * and audio drivers. The struct &i915_audio_component_ops @ops in it is
  60  * defined in graphics driver and called in audio driver. The
  61  * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
  62  */
  63
  64 /* DP N/M table */
  65 #define LC_810M 810000
  66 #define LC_540M 540000
  67 #define LC_270M 270000
  68 #define LC_162M 162000
  69
  70 struct dp_aud_n_m {
  71         int sample_rate;
  72         int clock;
  73         u16 m;
  74         u16 n;
  75 };
  76
  77 struct hdmi_aud_ncts {
  78         int sample_rate;
  79         int clock;
  80         int n;
  81         int cts;
  82 };
  83
  84 /* Values according to DP 1.4 Table 2-104 */
  85 static const struct dp_aud_n_m dp_aud_n_m[] = {
  86         { 32000, LC_162M, 1024, 10125 },
  87         { 44100, LC_162M, 784, 5625 },
  88         { 48000, LC_162M, 512, 3375 },
  89         { 64000, LC_162M, 2048, 10125 },
  90         { 88200, LC_162M, 1568, 5625 },
  91         { 96000, LC_162M, 1024, 3375 },
  92         { 128000, LC_162M, 4096, 10125 },
  93         { 176400, LC_162M, 3136, 5625 },
  94         { 192000, LC_162M, 2048, 3375 },
  95         { 32000, LC_270M, 1024, 16875 },
  96         { 44100, LC_270M, 784, 9375 },
  97         { 48000, LC_270M, 512, 5625 },
  98         { 64000, LC_270M, 2048, 16875 },
  99         { 88200, LC_270M, 1568, 9375 },
 100         { 96000, LC_270M, 1024, 5625 },
 101         { 128000, LC_270M, 4096, 16875 },
 102         { 176400, LC_270M, 3136, 9375 },
 103         { 192000, LC_270M, 2048, 5625 },
 104         { 32000, LC_540M, 1024, 33750 },
 105         { 44100, LC_540M, 784, 18750 },
 106         { 48000, LC_540M, 512, 11250 },
 107         { 64000, LC_540M, 2048, 33750 },
 108         { 88200, LC_540M, 1568, 18750 },
 109         { 96000, LC_540M, 1024, 11250 },
 110         { 128000, LC_540M, 4096, 33750 },
 111         { 176400, LC_540M, 3136, 18750 },
 112         { 192000, LC_540M, 2048, 11250 },
 113         { 32000, LC_810M, 1024, 50625 },
 114         { 44100, LC_810M, 784, 28125 },
 115         { 48000, LC_810M, 512, 16875 },
 116         { 64000, LC_810M, 2048, 50625 },
 117         { 88200, LC_810M, 1568, 28125 },
 118         { 96000, LC_810M, 1024, 16875 },
 119         { 128000, LC_810M, 4096, 50625 },
 120         { 176400, LC_810M, 3136, 28125 },
 121         { 192000, LC_810M, 2048, 16875 },
 122 };
 123
 124 static const struct dp_aud_n_m *
 125 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
 126 {
 127         int i;
 128
 129         for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
 130                 if (rate == dp_aud_n_m[i].sample_rate &&
 131                     crtc_state->port_clock == dp_aud_n_m[i].clock)
 132                         return &dp_aud_n_m[i];
 133         }
 134
 135         return NULL;
 136 }
 137
 138 static const struct {
 139         int clock;
 140         u32 config;
 141 } hdmi_audio_clock[] = {
 142         { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
 143         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
 144         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
 145         { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
 146         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
 147         { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
 148         { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
 149         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
 150         { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
 151         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
 152         { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
 153         { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
 154         { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
 155         { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
 156 };
 157
 158 /* HDMI N/CTS table */
 159 #define TMDS_297M 297000
 160 #define TMDS_296M 296703
 161 #define TMDS_594M 594000
 162 #define TMDS_593M 593407
 163
 164 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
 165         { 32000, TMDS_296M, 5824, 421875 },
 166         { 32000, TMDS_297M, 3072, 222750 },
 167         { 32000, TMDS_593M, 5824, 843750 },
 168         { 32000, TMDS_594M, 3072, 445500 },
 169         { 44100, TMDS_296M, 4459, 234375 },
 170         { 44100, TMDS_297M, 4704, 247500 },
 171         { 44100, TMDS_593M, 8918, 937500 },
 172         { 44100, TMDS_594M, 9408, 990000 },
 173         { 88200, TMDS_296M, 8918, 234375 },
 174         { 88200, TMDS_297M, 9408, 247500 },
 175         { 88200, TMDS_593M, 17836, 937500 },
 176         { 88200, TMDS_594M, 18816, 990000 },
 177         { 176400, TMDS_296M, 17836, 234375 },
 178         { 176400, TMDS_297M, 18816, 247500 },
 179         { 176400, TMDS_593M, 35672, 937500 },
 180         { 176400, TMDS_594M, 37632, 990000 },
 181         { 48000, TMDS_296M, 5824, 281250 },
 182         { 48000, TMDS_297M, 5120, 247500 },
 183         { 48000, TMDS_593M, 5824, 562500 },
 184         { 48000, TMDS_594M, 6144, 594000 },
 185         { 96000, TMDS_296M, 11648, 281250 },
 186         { 96000, TMDS_297M, 10240, 247500 },
 187         { 96000, TMDS_593M, 11648, 562500 },
 188         { 96000, TMDS_594M, 12288, 594000 },
 189         { 192000, TMDS_296M, 23296, 281250 },
 190         { 192000, TMDS_297M, 20480, 247500 },
 191         { 192000, TMDS_593M, 23296, 562500 },
 192         { 192000, TMDS_594M, 24576, 594000 },
 193 };
 194
 195 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
 196 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
 197 #define TMDS_371M 371250
 198 #define TMDS_370M 370878
 199
 200 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
 201         { 32000, TMDS_370M, 5824, 527344 },
 202         { 32000, TMDS_371M, 6144, 556875 },
 203         { 44100, TMDS_370M, 8918, 585938 },
 204         { 44100, TMDS_371M, 4704, 309375 },
 205         { 88200, TMDS_370M, 17836, 585938 },
 206         { 88200, TMDS_371M, 9408, 309375 },
 207         { 176400, TMDS_370M, 35672, 585938 },
 208         { 176400, TMDS_371M, 18816, 309375 },
 209         { 48000, TMDS_370M, 11648, 703125 },
 210         { 48000, TMDS_371M, 5120, 309375 },
 211         { 96000, TMDS_370M, 23296, 703125 },
 212         { 96000, TMDS_371M, 10240, 309375 },
 213         { 192000, TMDS_370M, 46592, 703125 },
 214         { 192000, TMDS_371M, 20480, 309375 },
 215 };
 216
 217 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
 218 #define TMDS_445_5M 445500
 219 #define TMDS_445M 445054
 220
 221 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
 222         { 32000, TMDS_445M, 5824, 632813 },
 223         { 32000, TMDS_445_5M, 4096, 445500 },
 224         { 44100, TMDS_445M, 8918, 703125 },
 225         { 44100, TMDS_445_5M, 4704, 371250 },
 226         { 88200, TMDS_445M, 17836, 703125 },
 227         { 88200, TMDS_445_5M, 9408, 371250 },
 228         { 176400, TMDS_445M, 35672, 703125 },
 229         { 176400, TMDS_445_5M, 18816, 371250 },
 230         { 48000, TMDS_445M, 5824, 421875 },
 231         { 48000, TMDS_445_5M, 5120, 371250 },
 232         { 96000, TMDS_445M, 11648, 421875 },
 233         { 96000, TMDS_445_5M, 10240, 371250 },
 234         { 192000, TMDS_445M, 23296, 421875 },
 235         { 192000, TMDS_445_5M, 20480, 371250 },
 236 };
 237
 238 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
 239 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
 240 {
 241         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 242         const struct drm_display_mode *adjusted_mode =
 243                 &crtc_state->hw.adjusted_mode;
 244         int i;
 245
 246         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
 247                 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
 248                         break;
 249         }
 250
 251         if (INTEL_GEN(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500)
 252                 i = ARRAY_SIZE(hdmi_audio_clock);
 253
 254         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
 255                 drm_dbg_kms(&dev_priv->drm,
 256                             "HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
 257                             adjusted_mode->crtc_clock);
 258                 i = 1;
 259         }
 260
 261         drm_dbg_kms(&dev_priv->drm,
 262                     "Configuring HDMI audio for pixel clock %d (0x%08x)\n",
 263                     hdmi_audio_clock[i].clock,
 264                     hdmi_audio_clock[i].config);
 265
 266         return hdmi_audio_clock[i].config;
 267 }
 268
 269 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
 270                                    int rate)
 271 {
 272         const struct hdmi_aud_ncts *hdmi_ncts_table;
 273         int i, size;
 274
 275         if (crtc_state->pipe_bpp == 36) {
 276                 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
 277                 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
 278         } else if (crtc_state->pipe_bpp == 30) {
 279                 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
 280                 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
 281         } else {
 282                 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
 283                 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
 284         }
 285
 286         for (i = 0; i < size; i++) {
 287                 if (rate == hdmi_ncts_table[i].sample_rate &&
 288                     crtc_state->port_clock == hdmi_ncts_table[i].clock) {
 289                         return hdmi_ncts_table[i].n;
 290                 }
 291         }
 292         return 0;
 293 }
 294
 295 static bool intel_eld_uptodate(struct drm_connector *connector,
 296                                i915_reg_t reg_eldv, u32 bits_eldv,
 297                                i915_reg_t reg_elda, u32 bits_elda,
 298                                i915_reg_t reg_edid)
 299 {
 300         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 301         const u8 *eld = connector->eld;
 302         u32 tmp;
 303         int i;
 304
 305         tmp = intel_de_read(dev_priv, reg_eldv);
 306         tmp &= bits_eldv;
 307
 308         if (!tmp)
 309                 return false;
 310
 311         tmp = intel_de_read(dev_priv, reg_elda);
 312         tmp &= ~bits_elda;
 313         intel_de_write(dev_priv, reg_elda, tmp);
 314
 315         for (i = 0; i < drm_eld_size(eld) / 4; i++)
 316                 if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i))
 317                         return false;
 318
 319         return true;
 320 }
 321
 322 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
 323                                     const struct intel_crtc_state *old_crtc_state,
 324                                     const struct drm_connector_state *old_conn_state)
 325 {
 326         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 327         u32 eldv, tmp;
 328
 329         drm_dbg_kms(&dev_priv->drm, "Disable audio codec\n");
 330
 331         tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
 332         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 333                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 334         else
 335                 eldv = G4X_ELDV_DEVCTG;
 336
 337         /* Invalidate ELD */
 338         tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
 339         tmp &= ~eldv;
 340         intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
 341 }
 342
 343 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
 344                                    const struct intel_crtc_state *crtc_state,
 345                                    const struct drm_connector_state *conn_state)
 346 {
 347         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 348         struct drm_connector *connector = conn_state->connector;
 349         const u8 *eld = connector->eld;
 350         u32 eldv;
 351         u32 tmp;
 352         int len, i;
 353
 354         drm_dbg_kms(&dev_priv->drm, "Enable audio codec, %u bytes ELD\n",
 355                     drm_eld_size(eld));
 356
 357         tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
 358         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 359                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 360         else
 361                 eldv = G4X_ELDV_DEVCTG;
 362
 363         if (intel_eld_uptodate(connector,
 364                                G4X_AUD_CNTL_ST, eldv,
 365                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
 366                                G4X_HDMIW_HDMIEDID))
 367                 return;
 368
 369         tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
 370         tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
 371         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 372         intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
 373
 374         len = min(drm_eld_size(eld) / 4, len);
 375         drm_dbg(&dev_priv->drm, "ELD size %d\n", len);
 376         for (i = 0; i < len; i++)
 377                 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID,
 378                                *((const u32 *)eld + i));
 379
 380         tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
 381         tmp |= eldv;
 382         intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
 383 }
 384
 385 static void
 386 hsw_dp_audio_config_update(struct intel_encoder *encoder,
 387                            const struct intel_crtc_state *crtc_state)
 388 {
 389         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 390         struct i915_audio_component *acomp = dev_priv->audio_component;
 391         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 392         enum port port = encoder->port;
 393         const struct dp_aud_n_m *nm;
 394         int rate;
 395         u32 tmp;
 396
 397         rate = acomp ? acomp->aud_sample_rate[port] : 0;
 398         nm = audio_config_dp_get_n_m(crtc_state, rate);
 399         if (nm)
 400                 drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m,
 401                             nm->n);
 402         else
 403                 drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n");
 404
 405         tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
 406         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 407         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 408         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 409         tmp |= AUD_CONFIG_N_VALUE_INDEX;
 410
 411         if (nm) {
 412                 tmp &= ~AUD_CONFIG_N_MASK;
 413                 tmp |= AUD_CONFIG_N(nm->n);
 414                 tmp |= AUD_CONFIG_N_PROG_ENABLE;
 415         }
 416
 417         intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
 418
 419         tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
 420         tmp &= ~AUD_CONFIG_M_MASK;
 421         tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 422         tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 423
 424         if (nm) {
 425                 tmp |= nm->m;
 426                 tmp |= AUD_M_CTS_M_VALUE_INDEX;
 427                 tmp |= AUD_M_CTS_M_PROG_ENABLE;
 428         }
 429
 430         intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
 431 }
 432
 433 static void
 434 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
 435                              const struct intel_crtc_state *crtc_state)
 436 {
 437         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 438         struct i915_audio_component *acomp = dev_priv->audio_component;
 439         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 440         enum port port = encoder->port;
 441         int n, rate;
 442         u32 tmp;
 443
 444         rate = acomp ? acomp->aud_sample_rate[port] : 0;
 445
 446         tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
 447         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 448         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 449         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 450         tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 451
 452         n = audio_config_hdmi_get_n(crtc_state, rate);
 453         if (n != 0) {
 454                 drm_dbg_kms(&dev_priv->drm, "using N %d\n", n);
 455
 456                 tmp &= ~AUD_CONFIG_N_MASK;
 457                 tmp |= AUD_CONFIG_N(n);
 458                 tmp |= AUD_CONFIG_N_PROG_ENABLE;
 459         } else {
 460                 drm_dbg_kms(&dev_priv->drm, "using automatic N\n");
 461         }
 462
 463         intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
 464
 465         /*
 466          * Let's disable "Enable CTS or M Prog bit"
 467          * and let HW calculate the value
 468          */
 469         tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
 470         tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 471         tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 472         intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
 473 }
 474
 475 static void
 476 hsw_audio_config_update(struct intel_encoder *encoder,
 477                         const struct intel_crtc_state *crtc_state)
 478 {
 479         if (intel_crtc_has_dp_encoder(crtc_state))
 480                 hsw_dp_audio_config_update(encoder, crtc_state);
 481         else
 482                 hsw_hdmi_audio_config_update(encoder, crtc_state);
 483 }
 484
 485 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
 486                                     const struct intel_crtc_state *old_crtc_state,
 487                                     const struct drm_connector_state *old_conn_state)
 488 {
 489         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 490         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 491         u32 tmp;
 492
 493         drm_dbg_kms(&dev_priv->drm, "Disable audio codec on transcoder %s\n",
 494                     transcoder_name(cpu_transcoder));
 495
 496         mutex_lock(&dev_priv->av_mutex);
 497
 498         /* Disable timestamps */
 499         tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
 500         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 501         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 502         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 503         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 504         if (intel_crtc_has_dp_encoder(old_crtc_state))
 505                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 506         intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
 507
 508         /* Invalidate ELD */
 509         tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
 510         tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
 511         tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
 512         intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
 513
 514         mutex_unlock(&dev_priv->av_mutex);
 515 }
 516
 517 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 518                                            const struct intel_crtc_state *crtc_state)
 519 {
 520         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 521         unsigned int link_clks_available, link_clks_required;
 522         unsigned int tu_data, tu_line, link_clks_active;
 523         unsigned int h_active, h_total, hblank_delta, pixel_clk;
 524         unsigned int fec_coeff, cdclk, vdsc_bpp;
 525         unsigned int link_clk, lanes;
 526         unsigned int hblank_rise;
 527
 528         h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 529         h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 530         pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
 531         vdsc_bpp = crtc_state->dsc.compressed_bpp;
 532         cdclk = i915->cdclk.hw.cdclk;
 533         /* fec= 0.972261, using rounding multiplier of 1000000 */
 534         fec_coeff = 972261;
 535         link_clk = crtc_state->port_clock;
 536         lanes = crtc_state->lane_count;
 537
 538         drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
 539                     "lanes = %u vdsc_bpp = %u cdclk = %u\n",
 540                     h_active, link_clk, lanes, vdsc_bpp, cdclk);
 541
 542         if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
 543                 return 0;
 544
 545         link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
 546         link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2);
 547
 548         if (link_clks_available > link_clks_required)
 549                 hblank_delta = 32;
 550         else
 551                 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
 552                                                   mul_u32_u32(link_clk, cdclk));
 553
 554         tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
 555                             mul_u32_u32(link_clk * lanes, fec_coeff));
 556         tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
 557                             mul_u32_u32(64 * pixel_clk, 1000000));
 558         link_clks_active  = (tu_line - 1) * 64 + tu_data;
 559
 560         hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk;
 561
 562         return h_active - hblank_rise + hblank_delta;
 563 }
 564
 565 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state)
 566 {
 567         unsigned int h_active, h_total, pixel_clk;
 568         unsigned int link_clk, lanes;
 569
 570         h_active = crtc_state->hw.adjusted_mode.hdisplay;
 571         h_total = crtc_state->hw.adjusted_mode.htotal;
 572         pixel_clk = crtc_state->hw.adjusted_mode.clock;
 573         link_clk = crtc_state->port_clock;
 574         lanes = crtc_state->lane_count;
 575
 576         return ((h_total - h_active) * link_clk - 12 * pixel_clk) /
 577                 (pixel_clk * (48 / lanes + 2));
 578 }
 579
 580 static void enable_audio_dsc_wa(struct intel_encoder *encoder,
 581                                 const struct intel_crtc_state *crtc_state)
 582 {
 583         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 584         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 585         enum pipe pipe = crtc->pipe;
 586         unsigned int hblank_early_prog, samples_room;
 587         unsigned int val;
 588
 589         if (INTEL_GEN(i915) < 11)
 590                 return;
 591
 592         val = intel_de_read(i915, AUD_CONFIG_BE);
 593
 594         if (INTEL_GEN(i915) == 11)
 595                 val |= HBLANK_EARLY_ENABLE_ICL(pipe);
 596         else if (INTEL_GEN(i915) >= 12)
 597                 val |= HBLANK_EARLY_ENABLE_TGL(pipe);
 598
 599         if (crtc_state->dsc.compression_enable &&
 600             (crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
 601             crtc_state->hw.adjusted_mode.vdisplay >= 2160)) {
 602                 /* Get hblank early enable value required */
 603                 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state);
 604                 if (hblank_early_prog < 32) {
 605                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 606                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32);
 607                 } else if (hblank_early_prog < 64) {
 608                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 609                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64);
 610                 } else if (hblank_early_prog < 96) {
 611                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 612                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96);
 613                 } else {
 614                         val &= ~HBLANK_START_COUNT_MASK(pipe);
 615                         val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128);
 616                 }
 617
 618                 /* Get samples room value required */
 619                 samples_room = calc_samples_room(crtc_state);
 620                 if (samples_room < 3) {
 621                         val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
 622                         val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room);
 623                 } else {
 624                         /* Program 0 i.e "All Samples available in buffer" */
 625                         val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
 626                         val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0);
 627                 }
 628         }
 629
 630         intel_de_write(i915, AUD_CONFIG_BE, val);
 631 }
 632
 633 #undef ROUNDING_FACTOR
 634
 635 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
 636                                    const struct intel_crtc_state *crtc_state,
 637                                    const struct drm_connector_state *conn_state)
 638 {
 639         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 640         struct drm_connector *connector = conn_state->connector;
 641         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 642         const u8 *eld = connector->eld;
 643         u32 tmp;
 644         int len, i;
 645
 646         drm_dbg_kms(&dev_priv->drm,
 647                     "Enable audio codec on transcoder %s, %u bytes ELD\n",
 648                      transcoder_name(cpu_transcoder), drm_eld_size(eld));
 649
 650         mutex_lock(&dev_priv->av_mutex);
 651
 652         /* Enable Audio WA for 4k DSC usecases */
 653         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
 654                 enable_audio_dsc_wa(encoder, crtc_state);
 655
 656         /* Enable audio presence detect, invalidate ELD */
 657         tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
 658         tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
 659         tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
 660         intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
 661
 662         /*
 663          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 664          * disabled during the mode set. The proper fix would be to push the
 665          * rest of the setup into a vblank work item, queued here, but the
 666          * infrastructure is not there yet.
 667          */
 668
 669         /* Reset ELD write address */
 670         tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
 671         tmp &= ~IBX_ELD_ADDRESS_MASK;
 672         intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
 673
 674         /* Up to 84 bytes of hw ELD buffer */
 675         len = min(drm_eld_size(eld), 84);
 676         for (i = 0; i < len / 4; i++)
 677                 intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder),
 678                                *((const u32 *)eld + i));
 679
 680         /* ELD valid */
 681         tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
 682         tmp |= AUDIO_ELD_VALID(cpu_transcoder);
 683         intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
 684
 685         /* Enable timestamps */
 686         hsw_audio_config_update(encoder, crtc_state);
 687
 688         mutex_unlock(&dev_priv->av_mutex);
 689 }
 690
 691 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
 692                                     const struct intel_crtc_state *old_crtc_state,
 693                                     const struct drm_connector_state *old_conn_state)
 694 {
 695         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 696         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 697         enum pipe pipe = crtc->pipe;
 698         enum port port = encoder->port;
 699         u32 tmp, eldv;
 700         i915_reg_t aud_config, aud_cntrl_st2;
 701
 702         drm_dbg_kms(&dev_priv->drm,
 703                     "Disable audio codec on [ENCODER:%d:%s], pipe %c\n",
 704                      encoder->base.base.id, encoder->base.name,
 705                      pipe_name(pipe));
 706
 707         if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
 708                 return;
 709
 710         if (HAS_PCH_IBX(dev_priv)) {
 711                 aud_config = IBX_AUD_CFG(pipe);
 712                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 713         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 714                 aud_config = VLV_AUD_CFG(pipe);
 715                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 716         } else {
 717                 aud_config = CPT_AUD_CFG(pipe);
 718                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 719         }
 720
 721         /* Disable timestamps */
 722         tmp = intel_de_read(dev_priv, aud_config);
 723         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 724         tmp |= AUD_CONFIG_N_PROG_ENABLE;
 725         tmp &= ~AUD_CONFIG_UPPER_N_MASK;
 726         tmp &= ~AUD_CONFIG_LOWER_N_MASK;
 727         if (intel_crtc_has_dp_encoder(old_crtc_state))
 728                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 729         intel_de_write(dev_priv, aud_config, tmp);
 730
 731         eldv = IBX_ELD_VALID(port);
 732
 733         /* Invalidate ELD */
 734         tmp = intel_de_read(dev_priv, aud_cntrl_st2);
 735         tmp &= ~eldv;
 736         intel_de_write(dev_priv, aud_cntrl_st2, tmp);
 737 }
 738
 739 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
 740                                    const struct intel_crtc_state *crtc_state,
 741                                    const struct drm_connector_state *conn_state)
 742 {
 743         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 744         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 745         struct drm_connector *connector = conn_state->connector;
 746         enum pipe pipe = crtc->pipe;
 747         enum port port = encoder->port;
 748         const u8 *eld = connector->eld;
 749         u32 tmp, eldv;
 750         int len, i;
 751         i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 752
 753         drm_dbg_kms(&dev_priv->drm,
 754                     "Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n",
 755                     encoder->base.base.id, encoder->base.name,
 756                     pipe_name(pipe), drm_eld_size(eld));
 757
 758         if (drm_WARN_ON(&dev_priv->drm, port == PORT_A))
 759                 return;
 760
 761         /*
 762          * FIXME: We're supposed to wait for vblank here, but we have vblanks
 763          * disabled during the mode set. The proper fix would be to push the
 764          * rest of the setup into a vblank work item, queued here, but the
 765          * infrastructure is not there yet.
 766          */
 767
 768         if (HAS_PCH_IBX(dev_priv)) {
 769                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 770                 aud_config = IBX_AUD_CFG(pipe);
 771                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 772                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 773         } else if (IS_VALLEYVIEW(dev_priv) ||
 774                    IS_CHERRYVIEW(dev_priv)) {
 775                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 776                 aud_config = VLV_AUD_CFG(pipe);
 777                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 778                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 779         } else {
 780                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 781                 aud_config = CPT_AUD_CFG(pipe);
 782                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 783                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 784         }
 785
 786         eldv = IBX_ELD_VALID(port);
 787
 788         /* Invalidate ELD */
 789         tmp = intel_de_read(dev_priv, aud_cntrl_st2);
 790         tmp &= ~eldv;
 791         intel_de_write(dev_priv, aud_cntrl_st2, tmp);
 792
 793         /* Reset ELD write address */
 794         tmp = intel_de_read(dev_priv, aud_cntl_st);
 795         tmp &= ~IBX_ELD_ADDRESS_MASK;
 796         intel_de_write(dev_priv, aud_cntl_st, tmp);
 797
 798         /* Up to 84 bytes of hw ELD buffer */
 799         len = min(drm_eld_size(eld), 84);
 800         for (i = 0; i < len / 4; i++)
 801                 intel_de_write(dev_priv, hdmiw_hdmiedid,
 802                                *((const u32 *)eld + i));
 803
 804         /* ELD valid */
 805         tmp = intel_de_read(dev_priv, aud_cntrl_st2);
 806         tmp |= eldv;
 807         intel_de_write(dev_priv, aud_cntrl_st2, tmp);
 808
 809         /* Enable timestamps */
 810         tmp = intel_de_read(dev_priv, aud_config);
 811         tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 812         tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 813         tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 814         if (intel_crtc_has_dp_encoder(crtc_state))
 815                 tmp |= AUD_CONFIG_N_VALUE_INDEX;
 816         else
 817                 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 818         intel_de_write(dev_priv, aud_config, tmp);
 819 }
 820
 821 /**
 822  * intel_audio_codec_enable - Enable the audio codec for HD audio
 823  * @encoder: encoder on which to enable audio
 824  * @crtc_state: pointer to the current crtc state.
 825  * @conn_state: pointer to the current connector state.
 826  *
 827  * The enable sequences may only be performed after enabling the transcoder and
 828  * port, and after completed link training.
 829  */
 830 void intel_audio_codec_enable(struct intel_encoder *encoder,
 831                               const struct intel_crtc_state *crtc_state,
 832                               const struct drm_connector_state *conn_state)
 833 {
 834         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 835         struct i915_audio_component *acomp = dev_priv->audio_component;
 836         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 837         struct drm_connector *connector = conn_state->connector;
 838         const struct drm_display_mode *adjusted_mode =
 839                 &crtc_state->hw.adjusted_mode;
 840         enum port port = encoder->port;
 841         enum pipe pipe = crtc->pipe;
 842
 843         /* FIXME precompute the ELD in .compute_config() */
 844         if (!connector->eld[0])
 845                 drm_dbg_kms(&dev_priv->drm,
 846                             "Bogus ELD on [CONNECTOR:%d:%s]\n",
 847                             connector->base.id, connector->name);
 848
 849         drm_dbg(&dev_priv->drm, "ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 850                 connector->base.id,
 851                 connector->name,
 852                 encoder->base.base.id,
 853                 encoder->base.name);
 854
 855         connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 856
 857         if (dev_priv->display.audio_codec_enable)
 858                 dev_priv->display.audio_codec_enable(encoder,
 859                                                      crtc_state,
 860                                                      conn_state);
 861
 862         mutex_lock(&dev_priv->av_mutex);
 863         encoder->audio_connector = connector;
 864
 865         /* referred in audio callbacks */
 866         dev_priv->av_enc_map[pipe] = encoder;
 867         mutex_unlock(&dev_priv->av_mutex);
 868
 869         if (acomp && acomp->base.audio_ops &&
 870             acomp->base.audio_ops->pin_eld_notify) {
 871                 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
 872                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 873                         pipe = -1;
 874                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 875                                                  (int) port, (int) pipe);
 876         }
 877
 878         intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
 879                                crtc_state->port_clock,
 880                                intel_crtc_has_dp_encoder(crtc_state));
 881 }
 882
 883 /**
 884  * intel_audio_codec_disable - Disable the audio codec for HD audio
 885  * @encoder: encoder on which to disable audio
 886  * @old_crtc_state: pointer to the old crtc state.
 887  * @old_conn_state: pointer to the old connector state.
 888  *
 889  * The disable sequences must be performed before disabling the transcoder or
 890  * port.
 891  */
 892 void intel_audio_codec_disable(struct intel_encoder *encoder,
 893                                const struct intel_crtc_state *old_crtc_state,
 894                                const struct drm_connector_state *old_conn_state)
 895 {
 896         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 897         struct i915_audio_component *acomp = dev_priv->audio_component;
 898         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 899         enum port port = encoder->port;
 900         enum pipe pipe = crtc->pipe;
 901
 902         if (dev_priv->display.audio_codec_disable)
 903                 dev_priv->display.audio_codec_disable(encoder,
 904                                                       old_crtc_state,
 905                                                       old_conn_state);
 906
 907         mutex_lock(&dev_priv->av_mutex);
 908         encoder->audio_connector = NULL;
 909         dev_priv->av_enc_map[pipe] = NULL;
 910         mutex_unlock(&dev_priv->av_mutex);
 911
 912         if (acomp && acomp->base.audio_ops &&
 913             acomp->base.audio_ops->pin_eld_notify) {
 914                 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
 915                 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
 916                         pipe = -1;
 917                 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 918                                                  (int) port, (int) pipe);
 919         }
 920
 921         intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
 922 }
 923
 924 /**
 925  * intel_init_audio_hooks - Set up chip specific audio hooks
 926  * @dev_priv: device private
 927  */
 928 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 929 {
 930         if (IS_G4X(dev_priv)) {
 931                 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
 932                 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
 933         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 934                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 935                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 936         } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
 937                 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 938                 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 939         } else if (HAS_PCH_SPLIT(dev_priv)) {
 940                 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 941                 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
 942         }
 943 }
 944
 945 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
 946                                         struct intel_crtc *crtc,
 947                                         bool enable)
 948 {
 949         struct intel_cdclk_state *cdclk_state;
 950         int ret;
 951
 952         /* need to hold at least one crtc lock for the global state */
 953         ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
 954         if (ret)
 955                 return ret;
 956
 957         cdclk_state = intel_atomic_get_cdclk_state(state);
 958         if (IS_ERR(cdclk_state))
 959                 return PTR_ERR(cdclk_state);
 960
 961         cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
 962
 963         return drm_atomic_commit(&state->base);
 964 }
 965
 966 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
 967                                   bool enable)
 968 {
 969         struct drm_modeset_acquire_ctx ctx;
 970         struct drm_atomic_state *state;
 971         struct intel_crtc *crtc;
 972         int ret;
 973
 974         crtc = intel_get_first_crtc(dev_priv);
 975         if (!crtc)
 976                 return;
 977
 978         drm_modeset_acquire_init(&ctx, 0);
 979         state = drm_atomic_state_alloc(&dev_priv->drm);
 980         if (drm_WARN_ON(&dev_priv->drm, !state))
 981                 return;
 982
 983         state->acquire_ctx = &ctx;
 984
 985 retry:
 986         ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
 987                                            enable);
 988         if (ret == -EDEADLK) {
 989                 drm_atomic_state_clear(state);
 990                 drm_modeset_backoff(&ctx);
 991                 goto retry;
 992         }
 993
 994         drm_WARN_ON(&dev_priv->drm, ret);
 995
 996         drm_atomic_state_put(state);
 997
 998         drm_modeset_drop_locks(&ctx);
 999         drm_modeset_acquire_fini(&ctx);
1000 }
1001
1002 static unsigned long i915_audio_component_get_power(struct device *kdev)
1003 {
1004         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1005         intel_wakeref_t ret;
1006
1007         /* Catch potential impedance mismatches before they occur! */
1008         BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
1009
1010         ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1011
1012         if (dev_priv->audio_power_refcount++ == 0) {
1013                 if (INTEL_GEN(dev_priv) >= 9) {
1014                         intel_de_write(dev_priv, AUD_FREQ_CNTRL,
1015                                        dev_priv->audio_freq_cntrl);
1016                         drm_dbg_kms(&dev_priv->drm,
1017                                     "restored AUD_FREQ_CNTRL to 0x%x\n",
1018                                     dev_priv->audio_freq_cntrl);
1019                 }
1020
1021                 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
1022                 if (IS_GEMINILAKE(dev_priv))
1023                         glk_force_audio_cdclk(dev_priv, true);
1024
1025                 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1026                         intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
1027                                        (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
1028         }
1029
1030         return ret;
1031 }
1032
1033 static void i915_audio_component_put_power(struct device *kdev,
1034                                            unsigned long cookie)
1035 {
1036         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1037
1038         /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
1039         if (--dev_priv->audio_power_refcount == 0)
1040                 if (IS_GEMINILAKE(dev_priv))
1041                         glk_force_audio_cdclk(dev_priv, false);
1042
1043         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
1044 }
1045
1046 static void i915_audio_component_codec_wake_override(struct device *kdev,
1047                                                      bool enable)
1048 {
1049         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1050         unsigned long cookie;
1051         u32 tmp;
1052
1053         if (INTEL_GEN(dev_priv) < 9)
1054                 return;
1055
1056         cookie = i915_audio_component_get_power(kdev);
1057
1058         /*
1059          * Enable/disable generating the codec wake signal, overriding the
1060          * internal logic to generate the codec wake to controller.
1061          */
1062         tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1063         tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
1064         intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1065         usleep_range(1000, 1500);
1066
1067         if (enable) {
1068                 tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
1069                 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
1070                 intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
1071                 usleep_range(1000, 1500);
1072         }
1073
1074         i915_audio_component_put_power(kdev, cookie);
1075 }
1076
1077 /* Get CDCLK in kHz  */
1078 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
1079 {
1080         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1081
1082         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
1083                 return -ENODEV;
1084
1085         return dev_priv->cdclk.hw.cdclk;
1086 }
1087
1088 /*
1089  * get the intel_encoder according to the parameter port and pipe
1090  * intel_encoder is saved by the index of pipe
1091  * MST & (pipe >= 0): return the av_enc_map[pipe],
1092  *   when port is matched
1093  * MST & (pipe < 0): this is invalid
1094  * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
1095  *   will get the right intel_encoder with port matched
1096  * Non-MST & (pipe < 0): get the right intel_encoder with port matched
1097  */
1098 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
1099                                                int port, int pipe)
1100 {
1101         struct intel_encoder *encoder;
1102
1103         /* MST */
1104         if (pipe >= 0) {
1105                 if (drm_WARN_ON(&dev_priv->drm,
1106                                 pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
1107                         return NULL;
1108
1109                 encoder = dev_priv->av_enc_map[pipe];
1110                 /*
1111                  * when bootup, audio driver may not know it is
1112                  * MST or not. So it will poll all the port & pipe
1113                  * combinations
1114                  */
1115                 if (encoder != NULL && encoder->port == port &&
1116                     encoder->type == INTEL_OUTPUT_DP_MST)
1117                         return encoder;
1118         }
1119
1120         /* Non-MST */
1121         if (pipe > 0)
1122                 return NULL;
1123
1124         for_each_pipe(dev_priv, pipe) {
1125                 encoder = dev_priv->av_enc_map[pipe];
1126                 if (encoder == NULL)
1127                         continue;
1128
1129                 if (encoder->type == INTEL_OUTPUT_DP_MST)
1130                         continue;
1131
1132                 if (port == encoder->port)
1133                         return encoder;
1134         }
1135
1136         return NULL;
1137 }
1138
1139 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
1140                                                 int pipe, int rate)
1141 {
1142         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1143         struct i915_audio_component *acomp = dev_priv->audio_component;
1144         struct intel_encoder *encoder;
1145         struct intel_crtc *crtc;
1146         unsigned long cookie;
1147         int err = 0;
1148
1149         if (!HAS_DDI(dev_priv))
1150                 return 0;
1151
1152         cookie = i915_audio_component_get_power(kdev);
1153         mutex_lock(&dev_priv->av_mutex);
1154
1155         /* 1. get the pipe */
1156         encoder = get_saved_enc(dev_priv, port, pipe);
1157         if (!encoder || !encoder->base.crtc) {
1158                 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1159                             port_name(port));
1160                 err = -ENODEV;
1161                 goto unlock;
1162         }
1163
1164         crtc = to_intel_crtc(encoder->base.crtc);
1165
1166         /* port must be valid now, otherwise the pipe will be invalid */
1167         acomp->aud_sample_rate[port] = rate;
1168
1169         hsw_audio_config_update(encoder, crtc->config);
1170
1171  unlock:
1172         mutex_unlock(&dev_priv->av_mutex);
1173         i915_audio_component_put_power(kdev, cookie);
1174         return err;
1175 }
1176
1177 static int i915_audio_component_get_eld(struct device *kdev, int port,
1178                                         int pipe, bool *enabled,
1179                                         unsigned char *buf, int max_bytes)
1180 {
1181         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1182         struct intel_encoder *intel_encoder;
1183         const u8 *eld;
1184         int ret = -EINVAL;
1185
1186         mutex_lock(&dev_priv->av_mutex);
1187
1188         intel_encoder = get_saved_enc(dev_priv, port, pipe);
1189         if (!intel_encoder) {
1190                 drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
1191                             port_name(port));
1192                 mutex_unlock(&dev_priv->av_mutex);
1193                 return ret;
1194         }
1195
1196         ret = 0;
1197         *enabled = intel_encoder->audio_connector != NULL;
1198         if (*enabled) {
1199                 eld = intel_encoder->audio_connector->eld;
1200                 ret = drm_eld_size(eld);
1201                 memcpy(buf, eld, min(max_bytes, ret));
1202         }
1203
1204         mutex_unlock(&dev_priv->av_mutex);
1205         return ret;
1206 }
1207
1208 static const struct drm_audio_component_ops i915_audio_component_ops = {
1209         .owner          = THIS_MODULE,
1210         .get_power      = i915_audio_component_get_power,
1211         .put_power      = i915_audio_component_put_power,
1212         .codec_wake_override = i915_audio_component_codec_wake_override,
1213         .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1214         .sync_audio_rate = i915_audio_component_sync_audio_rate,
1215         .get_eld        = i915_audio_component_get_eld,
1216 };
1217
1218 static int i915_audio_component_bind(struct device *i915_kdev,
1219                                      struct device *hda_kdev, void *data)
1220 {
1221         struct i915_audio_component *acomp = data;
1222         struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1223         int i;
1224
1225         if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev))
1226                 return -EEXIST;
1227
1228         if (drm_WARN_ON(&dev_priv->drm,
1229                         !device_link_add(hda_kdev, i915_kdev,
1230                                          DL_FLAG_STATELESS)))
1231                 return -ENOMEM;
1232
1233         drm_modeset_lock_all(&dev_priv->drm);
1234         acomp->base.ops = &i915_audio_component_ops;
1235         acomp->base.dev = i915_kdev;
1236         BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1237         for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1238                 acomp->aud_sample_rate[i] = 0;
1239         dev_priv->audio_component = acomp;
1240         drm_modeset_unlock_all(&dev_priv->drm);
1241
1242         return 0;
1243 }
1244
1245 static void i915_audio_component_unbind(struct device *i915_kdev,
1246                                         struct device *hda_kdev, void *data)
1247 {
1248         struct i915_audio_component *acomp = data;
1249         struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1250
1251         drm_modeset_lock_all(&dev_priv->drm);
1252         acomp->base.ops = NULL;
1253         acomp->base.dev = NULL;
1254         dev_priv->audio_component = NULL;
1255         drm_modeset_unlock_all(&dev_priv->drm);
1256
1257         device_link_remove(hda_kdev, i915_kdev);
1258
1259         if (dev_priv->audio_power_refcount)
1260                 drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n",
1261                         dev_priv->audio_power_refcount);
1262 }
1263
1264 static const struct component_ops i915_audio_component_bind_ops = {
1265         .bind   = i915_audio_component_bind,
1266         .unbind = i915_audio_component_unbind,
1267 };
1268
1269 /**
1270  * i915_audio_component_init - initialize and register the audio component
1271  * @dev_priv: i915 device instance
1272  *
1273  * This will register with the component framework a child component which
1274  * will bind dynamically to the snd_hda_intel driver's corresponding master
1275  * component when the latter is registered. During binding the child
1276  * initializes an instance of struct i915_audio_component which it receives
1277  * from the master. The master can then start to use the interface defined by
1278  * this struct. Each side can break the binding at any point by deregistering
1279  * its own component after which each side's component unbind callback is
1280  * called.
1281  *
1282  * We ignore any error during registration and continue with reduced
1283  * functionality (i.e. without HDMI audio).
1284  */
1285 static void i915_audio_component_init(struct drm_i915_private *dev_priv)
1286 {
1287         int ret;
1288
1289         ret = component_add_typed(dev_priv->drm.dev,
1290                                   &i915_audio_component_bind_ops,
1291                                   I915_COMPONENT_AUDIO);
1292         if (ret < 0) {
1293                 drm_err(&dev_priv->drm,
1294                         "failed to add audio component (%d)\n", ret);
1295                 /* continue with reduced functionality */
1296                 return;
1297         }
1298
1299         if (INTEL_GEN(dev_priv) >= 9) {
1300                 dev_priv->audio_freq_cntrl = intel_de_read(dev_priv,
1301                                                            AUD_FREQ_CNTRL);
1302                 drm_dbg_kms(&dev_priv->drm,
1303                             "init value of AUD_FREQ_CNTRL of 0x%x\n",
1304                             dev_priv->audio_freq_cntrl);
1305         }
1306
1307         dev_priv->audio_component_registered = true;
1308 }
1309
1310 /**
1311  * i915_audio_component_cleanup - deregister the audio component
1312  * @dev_priv: i915 device instance
1313  *
1314  * Deregisters the audio component, breaking any existing binding to the
1315  * corresponding snd_hda_intel driver's master component.
1316  */
1317 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1318 {
1319         if (!dev_priv->audio_component_registered)
1320                 return;
1321
1322         component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1323         dev_priv->audio_component_registered = false;
1324 }
1325
1326 /**
1327  * intel_audio_init() - Initialize the audio driver either using
1328  * component framework or using lpe audio bridge
1329  * @dev_priv: the i915 drm device private data
1330  *
1331  */
1332 void intel_audio_init(struct drm_i915_private *dev_priv)
1333 {
1334         if (intel_lpe_audio_init(dev_priv) < 0)
1335                 i915_audio_component_init(dev_priv);
1336 }
1337
1338 /**
1339  * intel_audio_deinit() - deinitialize the audio driver
1340  * @dev_priv: the i915 drm device private data
1341  *
1342  */
1343 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1344 {
1345         if ((dev_priv)->lpe_audio.platdev != NULL)
1346                 intel_lpe_audio_teardown(dev_priv);
1347         else
1348                 i915_audio_component_cleanup(dev_priv);
1349 }