1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 #include <linux/reset-controller.h>
12 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
17 #include "clk-regmap-divider.h"
24 P_DISP_CC_PLL0_OUT_MAIN,
25 P_DSI0_PHY_PLL_OUT_BYTECLK,
26 P_DSI0_PHY_PLL_OUT_DSICLK,
27 P_DSI1_PHY_PLL_OUT_BYTECLK,
28 P_DSI1_PHY_PLL_OUT_DSICLK,
31 P_DP_PHY_PLL_LINK_CLK,
32 P_DP_PHY_PLL_VCO_DIV_CLK,
35 static struct clk_alpha_pll disp_cc_pll0 = {
37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
39 .hw.init = &(struct clk_init_data){
40 .name = "disp_cc_pll0",
41 .parent_data = &(const struct clk_parent_data){
42 .fw_name = "bi_tcxo", .name = "bi_tcxo",
45 .ops = &clk_alpha_pll_fabia_ops,
50 static const struct parent_map disp_cc_parent_map_0[] = {
52 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
53 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
56 static const struct clk_parent_data disp_cc_parent_data_0[] = {
57 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
58 { .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
59 { .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
62 static const struct parent_map disp_cc_parent_map_1[] = {
64 { P_DP_PHY_PLL_LINK_CLK, 1 },
65 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
68 static const struct clk_parent_data disp_cc_parent_data_1[] = {
69 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
70 { .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" },
71 { .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" },
74 static const struct parent_map disp_cc_parent_map_2[] = {
78 static const struct clk_parent_data disp_cc_parent_data_2[] = {
79 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
82 static const struct parent_map disp_cc_parent_map_3[] = {
84 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
85 { P_GPLL0_OUT_MAIN, 4 },
86 { P_GPLL0_OUT_MAIN_DIV, 5 },
89 static const struct clk_parent_data disp_cc_parent_data_3[] = {
90 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
91 { .hw = &disp_cc_pll0.clkr.hw },
92 { .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" },
93 { .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" },
96 static const struct parent_map disp_cc_parent_map_4[] = {
98 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
99 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
102 static const struct clk_parent_data disp_cc_parent_data_4[] = {
103 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
104 { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
105 { .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
108 /* Return the HW recalc rate for idle use case */
109 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
113 .parent_map = disp_cc_parent_map_0,
114 .clkr.hw.init = &(struct clk_init_data){
115 .name = "disp_cc_mdss_byte0_clk_src",
116 .parent_data = disp_cc_parent_data_0,
117 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
118 .flags = CLK_SET_RATE_PARENT,
119 .ops = &clk_byte2_ops,
123 /* Return the HW recalc rate for idle use case */
124 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
128 .parent_map = disp_cc_parent_map_0,
129 .clkr.hw.init = &(struct clk_init_data){
130 .name = "disp_cc_mdss_byte1_clk_src",
131 .parent_data = disp_cc_parent_data_0,
132 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
133 .flags = CLK_SET_RATE_PARENT,
134 .ops = &clk_byte2_ops,
138 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
139 F(19200000, P_BI_TCXO, 1, 0, 0),
143 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
147 .parent_map = disp_cc_parent_map_2,
148 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
149 .clkr.hw.init = &(struct clk_init_data){
150 .name = "disp_cc_mdss_dp_aux_clk_src",
151 .parent_data = disp_cc_parent_data_2,
152 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
153 .flags = CLK_SET_RATE_PARENT,
154 .ops = &clk_rcg2_ops,
158 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
162 .parent_map = disp_cc_parent_map_1,
163 .clkr.hw.init = &(struct clk_init_data){
164 .name = "disp_cc_mdss_dp_crypto_clk_src",
165 .parent_data = disp_cc_parent_data_1,
166 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
167 .ops = &clk_byte2_ops,
171 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
175 .parent_map = disp_cc_parent_map_1,
176 .clkr.hw.init = &(struct clk_init_data){
177 .name = "disp_cc_mdss_dp_link_clk_src",
178 .parent_data = disp_cc_parent_data_1,
179 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
180 .flags = CLK_SET_RATE_PARENT,
181 .ops = &clk_byte2_ops,
185 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
189 .parent_map = disp_cc_parent_map_1,
190 .clkr.hw.init = &(struct clk_init_data){
191 .name = "disp_cc_mdss_dp_pixel1_clk_src",
192 .parent_data = disp_cc_parent_data_1,
193 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
194 .flags = CLK_SET_RATE_PARENT,
199 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
203 .parent_map = disp_cc_parent_map_1,
204 .clkr.hw.init = &(struct clk_init_data){
205 .name = "disp_cc_mdss_dp_pixel_clk_src",
206 .parent_data = disp_cc_parent_data_1,
207 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
208 .flags = CLK_SET_RATE_PARENT,
213 static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
214 F(19200000, P_BI_TCXO, 1, 0, 0),
218 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
222 .parent_map = disp_cc_parent_map_0,
223 .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
224 .clkr.hw.init = &(struct clk_init_data){
225 .name = "disp_cc_mdss_esc0_clk_src",
226 .parent_data = disp_cc_parent_data_0,
227 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
228 .ops = &clk_rcg2_ops,
232 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
236 .parent_map = disp_cc_parent_map_0,
237 .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
238 .clkr.hw.init = &(struct clk_init_data){
239 .name = "disp_cc_mdss_esc1_clk_src",
240 .parent_data = disp_cc_parent_data_0,
241 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
242 .ops = &clk_rcg2_ops,
246 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
247 F(19200000, P_BI_TCXO, 1, 0, 0),
248 F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),
249 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
250 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
251 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
252 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
253 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
254 F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
255 F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
259 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
263 .parent_map = disp_cc_parent_map_3,
264 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
265 .clkr.hw.init = &(struct clk_init_data){
266 .name = "disp_cc_mdss_mdp_clk_src",
267 .parent_data = disp_cc_parent_data_3,
268 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
269 .ops = &clk_rcg2_shared_ops,
273 /* Return the HW recalc rate for idle use case */
274 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
278 .parent_map = disp_cc_parent_map_4,
279 .clkr.hw.init = &(struct clk_init_data){
280 .name = "disp_cc_mdss_pclk0_clk_src",
281 .parent_data = disp_cc_parent_data_4,
282 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
283 .flags = CLK_SET_RATE_PARENT,
284 .ops = &clk_pixel_ops,
288 /* Return the HW recalc rate for idle use case */
289 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
293 .parent_map = disp_cc_parent_map_4,
294 .clkr.hw.init = &(struct clk_init_data){
295 .name = "disp_cc_mdss_pclk1_clk_src",
296 .parent_data = disp_cc_parent_data_4,
297 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
298 .flags = CLK_SET_RATE_PARENT,
299 .ops = &clk_pixel_ops,
303 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
304 F(19200000, P_BI_TCXO, 1, 0, 0),
305 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
306 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
307 F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
308 F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
312 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
316 .parent_map = disp_cc_parent_map_3,
317 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
318 .clkr.hw.init = &(struct clk_init_data){
319 .name = "disp_cc_mdss_rot_clk_src",
320 .parent_data = disp_cc_parent_data_3,
321 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
322 .ops = &clk_rcg2_shared_ops,
326 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
330 .parent_map = disp_cc_parent_map_2,
331 .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
332 .clkr.hw.init = &(struct clk_init_data){
333 .name = "disp_cc_mdss_vsync_clk_src",
334 .parent_data = disp_cc_parent_data_2,
335 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
336 .ops = &clk_rcg2_ops,
340 static struct clk_branch disp_cc_mdss_ahb_clk = {
342 .halt_check = BRANCH_HALT,
344 .enable_reg = 0x4004,
345 .enable_mask = BIT(0),
346 .hw.init = &(struct clk_init_data){
347 .name = "disp_cc_mdss_ahb_clk",
348 .ops = &clk_branch2_ops,
353 static struct clk_branch disp_cc_mdss_axi_clk = {
355 .halt_check = BRANCH_HALT,
357 .enable_reg = 0x4008,
358 .enable_mask = BIT(0),
359 .hw.init = &(struct clk_init_data){
360 .name = "disp_cc_mdss_axi_clk",
361 .ops = &clk_branch2_ops,
366 /* Return the HW recalc rate for idle use case */
367 static struct clk_branch disp_cc_mdss_byte0_clk = {
369 .halt_check = BRANCH_HALT,
371 .enable_reg = 0x2028,
372 .enable_mask = BIT(0),
373 .hw.init = &(struct clk_init_data){
374 .name = "disp_cc_mdss_byte0_clk",
375 .parent_hws = (const struct clk_hw*[]){
376 &disp_cc_mdss_byte0_clk_src.clkr.hw,
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_branch2_ops,
385 /* Return the HW recalc rate for idle use case */
386 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
391 .hw.init = &(struct clk_init_data){
392 .name = "disp_cc_mdss_byte0_div_clk_src",
393 .parent_hws = (const struct clk_hw*[]){
394 &disp_cc_mdss_byte0_clk_src.clkr.hw,
397 .ops = &clk_regmap_div_ops,
402 /* Return the HW recalc rate for idle use case */
403 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
405 .halt_check = BRANCH_HALT,
407 .enable_reg = 0x202c,
408 .enable_mask = BIT(0),
409 .hw.init = &(struct clk_init_data){
410 .name = "disp_cc_mdss_byte0_intf_clk",
411 .parent_hws = (const struct clk_hw*[]){
412 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
415 .flags = CLK_SET_RATE_PARENT,
416 .ops = &clk_branch2_ops,
421 /* Return the HW recalc rate for idle use case */
422 static struct clk_branch disp_cc_mdss_byte1_clk = {
424 .halt_check = BRANCH_HALT,
426 .enable_reg = 0x2030,
427 .enable_mask = BIT(0),
428 .hw.init = &(struct clk_init_data){
429 .name = "disp_cc_mdss_byte1_clk",
430 .parent_hws = (const struct clk_hw*[]){
431 &disp_cc_mdss_byte1_clk_src.clkr.hw,
434 .flags = CLK_SET_RATE_PARENT,
435 .ops = &clk_branch2_ops,
440 /* Return the HW recalc rate for idle use case */
441 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
446 .hw.init = &(struct clk_init_data){
447 .name = "disp_cc_mdss_byte1_div_clk_src",
448 .parent_hws = (const struct clk_hw*[]){
449 &disp_cc_mdss_byte1_clk_src.clkr.hw,
452 .ops = &clk_regmap_div_ops,
457 /* Return the HW recalc rate for idle use case */
458 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
460 .halt_check = BRANCH_HALT,
462 .enable_reg = 0x2034,
463 .enable_mask = BIT(0),
464 .hw.init = &(struct clk_init_data){
465 .name = "disp_cc_mdss_byte1_intf_clk",
466 .parent_hws = (const struct clk_hw*[]){
467 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
470 .flags = CLK_SET_RATE_PARENT,
471 .ops = &clk_branch2_ops,
476 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
478 .halt_check = BRANCH_HALT,
480 .enable_reg = 0x2054,
481 .enable_mask = BIT(0),
482 .hw.init = &(struct clk_init_data){
483 .name = "disp_cc_mdss_dp_aux_clk",
484 .parent_hws = (const struct clk_hw*[]){
485 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
488 .flags = CLK_SET_RATE_PARENT,
489 .ops = &clk_branch2_ops,
494 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
496 .halt_check = BRANCH_HALT,
498 .enable_reg = 0x2048,
499 .enable_mask = BIT(0),
500 .hw.init = &(struct clk_init_data){
501 .name = "disp_cc_mdss_dp_crypto_clk",
502 .parent_hws = (const struct clk_hw*[]){
503 &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
506 .flags = CLK_SET_RATE_PARENT,
507 .ops = &clk_branch2_ops,
512 static struct clk_branch disp_cc_mdss_dp_link_clk = {
514 .halt_check = BRANCH_HALT,
516 .enable_reg = 0x2040,
517 .enable_mask = BIT(0),
518 .hw.init = &(struct clk_init_data){
519 .name = "disp_cc_mdss_dp_link_clk",
520 .parent_hws = (const struct clk_hw*[]){
521 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
524 .flags = CLK_SET_RATE_PARENT,
525 .ops = &clk_branch2_ops,
530 /* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
531 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
533 .halt_check = BRANCH_HALT,
535 .enable_reg = 0x2044,
536 .enable_mask = BIT(0),
537 .hw.init = &(struct clk_init_data){
538 .name = "disp_cc_mdss_dp_link_intf_clk",
539 .parent_hws = (const struct clk_hw*[]){
540 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
543 .ops = &clk_branch2_ops,
548 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
550 .halt_check = BRANCH_HALT,
552 .enable_reg = 0x2050,
553 .enable_mask = BIT(0),
554 .hw.init = &(struct clk_init_data){
555 .name = "disp_cc_mdss_dp_pixel1_clk",
556 .parent_hws = (const struct clk_hw*[]){
557 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
560 .flags = CLK_SET_RATE_PARENT,
561 .ops = &clk_branch2_ops,
566 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
568 .halt_check = BRANCH_HALT,
570 .enable_reg = 0x204c,
571 .enable_mask = BIT(0),
572 .hw.init = &(struct clk_init_data){
573 .name = "disp_cc_mdss_dp_pixel_clk",
574 .parent_hws = (const struct clk_hw*[]){
575 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
578 .flags = CLK_SET_RATE_PARENT,
579 .ops = &clk_branch2_ops,
584 static struct clk_branch disp_cc_mdss_esc0_clk = {
586 .halt_check = BRANCH_HALT,
588 .enable_reg = 0x2038,
589 .enable_mask = BIT(0),
590 .hw.init = &(struct clk_init_data){
591 .name = "disp_cc_mdss_esc0_clk",
592 .parent_hws = (const struct clk_hw*[]){
593 &disp_cc_mdss_esc0_clk_src.clkr.hw,
596 .flags = CLK_SET_RATE_PARENT,
597 .ops = &clk_branch2_ops,
602 static struct clk_branch disp_cc_mdss_esc1_clk = {
604 .halt_check = BRANCH_HALT,
606 .enable_reg = 0x203c,
607 .enable_mask = BIT(0),
608 .hw.init = &(struct clk_init_data){
609 .name = "disp_cc_mdss_esc1_clk",
610 .parent_hws = (const struct clk_hw*[]){
611 &disp_cc_mdss_esc1_clk_src.clkr.hw,
614 .flags = CLK_SET_RATE_PARENT,
615 .ops = &clk_branch2_ops,
620 static struct clk_branch disp_cc_mdss_mdp_clk = {
622 .halt_check = BRANCH_HALT,
624 .enable_reg = 0x200c,
625 .enable_mask = BIT(0),
626 .hw.init = &(struct clk_init_data){
627 .name = "disp_cc_mdss_mdp_clk",
628 .parent_hws = (const struct clk_hw*[]){
629 &disp_cc_mdss_mdp_clk_src.clkr.hw,
632 .flags = CLK_SET_RATE_PARENT,
633 .ops = &clk_branch2_ops,
638 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
640 .halt_check = BRANCH_HALT,
642 .enable_reg = 0x201c,
643 .enable_mask = BIT(0),
644 .hw.init = &(struct clk_init_data){
645 .name = "disp_cc_mdss_mdp_lut_clk",
646 .parent_hws = (const struct clk_hw*[]){
647 &disp_cc_mdss_mdp_clk_src.clkr.hw,
650 .ops = &clk_branch2_ops,
655 /* Return the HW recalc rate for idle use case */
656 static struct clk_branch disp_cc_mdss_pclk0_clk = {
658 .halt_check = BRANCH_HALT,
660 .enable_reg = 0x2004,
661 .enable_mask = BIT(0),
662 .hw.init = &(struct clk_init_data){
663 .name = "disp_cc_mdss_pclk0_clk",
664 .parent_hws = (const struct clk_hw*[]){
665 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
668 .flags = CLK_SET_RATE_PARENT,
669 .ops = &clk_branch2_ops,
674 /* Return the HW recalc rate for idle use case */
675 static struct clk_branch disp_cc_mdss_pclk1_clk = {
677 .halt_check = BRANCH_HALT,
679 .enable_reg = 0x2008,
680 .enable_mask = BIT(0),
681 .hw.init = &(struct clk_init_data){
682 .name = "disp_cc_mdss_pclk1_clk",
683 .parent_hws = (const struct clk_hw*[]){
684 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
687 .flags = CLK_SET_RATE_PARENT,
688 .ops = &clk_branch2_ops,
693 static struct clk_branch disp_cc_mdss_rot_clk = {
695 .halt_check = BRANCH_HALT,
697 .enable_reg = 0x2014,
698 .enable_mask = BIT(0),
699 .hw.init = &(struct clk_init_data){
700 .name = "disp_cc_mdss_rot_clk",
701 .parent_hws = (const struct clk_hw*[]){
702 &disp_cc_mdss_rot_clk_src.clkr.hw,
705 .flags = CLK_SET_RATE_PARENT,
706 .ops = &clk_branch2_ops,
711 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
713 .halt_check = BRANCH_HALT,
715 .enable_reg = 0x5004,
716 .enable_mask = BIT(0),
717 .hw.init = &(struct clk_init_data){
718 .name = "disp_cc_mdss_rscc_ahb_clk",
719 .ops = &clk_branch2_ops,
724 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
726 .halt_check = BRANCH_HALT,
728 .enable_reg = 0x5008,
729 .enable_mask = BIT(0),
730 .hw.init = &(struct clk_init_data){
731 .name = "disp_cc_mdss_rscc_vsync_clk",
732 .parent_hws = (const struct clk_hw*[]){
733 &disp_cc_mdss_vsync_clk_src.clkr.hw,
736 .flags = CLK_SET_RATE_PARENT,
737 .ops = &clk_branch2_ops,
742 static struct clk_branch disp_cc_mdss_vsync_clk = {
744 .halt_check = BRANCH_HALT,
746 .enable_reg = 0x2024,
747 .enable_mask = BIT(0),
748 .hw.init = &(struct clk_init_data){
749 .name = "disp_cc_mdss_vsync_clk",
750 .parent_hws = (const struct clk_hw*[]){
751 &disp_cc_mdss_vsync_clk_src.clkr.hw,
754 .flags = CLK_SET_RATE_PARENT,
755 .ops = &clk_branch2_ops,
760 static struct gdsc mdss_gdsc = {
765 .pwrsts = PWRSTS_OFF_ON,
766 .flags = HW_CTRL | POLL_CFG_GDSCR,
769 static struct clk_regmap *disp_cc_sdm845_clocks[] = {
770 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
771 [DISP_CC_MDSS_AXI_CLK] = &disp_cc_mdss_axi_clk.clkr,
772 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
773 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
774 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
775 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =
776 &disp_cc_mdss_byte0_div_clk_src.clkr,
777 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
778 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
779 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
780 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =
781 &disp_cc_mdss_byte1_div_clk_src.clkr,
782 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
783 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
784 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
785 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] =
786 &disp_cc_mdss_dp_crypto_clk_src.clkr,
787 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
788 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
789 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
790 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
791 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =
792 &disp_cc_mdss_dp_pixel1_clk_src.clkr,
793 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
794 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
795 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
796 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
797 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
798 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
799 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
800 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
801 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
802 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
803 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
804 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
805 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
806 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
807 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
808 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
809 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
810 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
811 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
812 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
815 static const struct qcom_reset_map disp_cc_sdm845_resets[] = {
816 [DISP_CC_MDSS_RSCC_BCR] = { 0x5000 },
819 static struct gdsc *disp_cc_sdm845_gdscs[] = {
820 [MDSS_GDSC] = &mdss_gdsc,
823 static const struct regmap_config disp_cc_sdm845_regmap_config = {
827 .max_register = 0x10000,
831 static const struct qcom_cc_desc disp_cc_sdm845_desc = {
832 .config = &disp_cc_sdm845_regmap_config,
833 .clks = disp_cc_sdm845_clocks,
834 .num_clks = ARRAY_SIZE(disp_cc_sdm845_clocks),
835 .resets = disp_cc_sdm845_resets,
836 .num_resets = ARRAY_SIZE(disp_cc_sdm845_resets),
837 .gdscs = disp_cc_sdm845_gdscs,
838 .num_gdscs = ARRAY_SIZE(disp_cc_sdm845_gdscs),
841 static const struct of_device_id disp_cc_sdm845_match_table[] = {
842 { .compatible = "qcom,sdm845-dispcc" },
845 MODULE_DEVICE_TABLE(of, disp_cc_sdm845_match_table);
847 static int disp_cc_sdm845_probe(struct platform_device *pdev)
849 struct regmap *regmap;
850 struct alpha_pll_config disp_cc_pll0_config = {};
852 regmap = qcom_cc_map(pdev, &disp_cc_sdm845_desc);
854 return PTR_ERR(regmap);
856 disp_cc_pll0_config.l = 0x2c;
857 disp_cc_pll0_config.alpha = 0xcaaa;
859 clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
861 /* Enable hardware clock gating for DSI and MDP clocks */
862 regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
864 return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
867 static struct platform_driver disp_cc_sdm845_driver = {
868 .probe = disp_cc_sdm845_probe,
870 .name = "disp_cc-sdm845",
871 .of_match_table = disp_cc_sdm845_match_table,
875 static int __init disp_cc_sdm845_init(void)
877 return platform_driver_register(&disp_cc_sdm845_driver);
879 subsys_initcall(disp_cc_sdm845_init);
881 static void __exit disp_cc_sdm845_exit(void)
883 platform_driver_unregister(&disp_cc_sdm845_driver);
885 module_exit(disp_cc_sdm845_exit);
887 MODULE_LICENSE("GPL v2");
888 MODULE_DESCRIPTION("QTI DISPCC SDM845 Driver");