1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021-2022, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
11 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
16 #include "clk-regmap-divider.h"
22 P_DISP_CC_PLL0_OUT_EVEN,
23 P_DISP_CC_PLL0_OUT_MAIN,
24 P_DP_PHY_PLL_LINK_CLK,
25 P_DP_PHY_PLL_VCO_DIV_CLK,
26 P_DSI0_PHY_PLL_OUT_BYTECLK,
27 P_DSI0_PHY_PLL_OUT_DSICLK,
28 P_EDP_PHY_PLL_LINK_CLK,
29 P_EDP_PHY_PLL_VCO_DIV_CLK,
33 static const struct pll_vco lucid_vco[] = {
34 { 249600000, 2000000000, 0 },
37 /* 1520MHz Configuration*/
38 static const struct alpha_pll_config disp_cc_pll0_config = {
41 .config_ctl_val = 0x20485699,
42 .config_ctl_hi_val = 0x00002261,
43 .config_ctl_hi1_val = 0x329A299C,
44 .user_ctl_val = 0x00000001,
45 .user_ctl_hi_val = 0x00000805,
46 .user_ctl_hi1_val = 0x00000000,
49 static struct clk_alpha_pll disp_cc_pll0 = {
51 .vco_table = lucid_vco,
52 .num_vco = ARRAY_SIZE(lucid_vco),
53 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
55 .hw.init = &(struct clk_init_data){
56 .name = "disp_cc_pll0",
57 .parent_data = &(const struct clk_parent_data){
61 .ops = &clk_alpha_pll_lucid_ops,
66 static const struct parent_map disp_cc_parent_map_0[] = {
70 static const struct clk_parent_data disp_cc_parent_data_0[] = {
71 { .fw_name = "bi_tcxo" },
74 static const struct parent_map disp_cc_parent_map_1[] = {
76 { P_DP_PHY_PLL_LINK_CLK, 1 },
77 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
80 static const struct clk_parent_data disp_cc_parent_data_1[] = {
81 { .fw_name = "bi_tcxo" },
82 { .fw_name = "dp_phy_pll_link_clk" },
83 { .fw_name = "dp_phy_pll_vco_div_clk" },
86 static const struct parent_map disp_cc_parent_map_2[] = {
88 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
91 static const struct clk_parent_data disp_cc_parent_data_2[] = {
92 { .fw_name = "bi_tcxo" },
93 { .fw_name = "dsi0_phy_pll_out_byteclk" },
96 static const struct parent_map disp_cc_parent_map_3[] = {
98 { P_EDP_PHY_PLL_LINK_CLK, 1 },
99 { P_EDP_PHY_PLL_VCO_DIV_CLK, 2 },
102 static const struct clk_parent_data disp_cc_parent_data_3[] = {
103 { .fw_name = "bi_tcxo" },
104 { .fw_name = "edp_phy_pll_link_clk" },
105 { .fw_name = "edp_phy_pll_vco_div_clk" },
108 static const struct parent_map disp_cc_parent_map_4[] = {
110 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
111 { P_GCC_DISP_GPLL0_CLK, 4 },
112 { P_DISP_CC_PLL0_OUT_EVEN, 5 },
115 static const struct clk_parent_data disp_cc_parent_data_4[] = {
116 { .fw_name = "bi_tcxo" },
117 { .hw = &disp_cc_pll0.clkr.hw },
118 { .fw_name = "gcc_disp_gpll0_clk" },
119 { .hw = &disp_cc_pll0.clkr.hw },
122 static const struct parent_map disp_cc_parent_map_5[] = {
124 { P_GCC_DISP_GPLL0_CLK, 4 },
127 static const struct clk_parent_data disp_cc_parent_data_5[] = {
128 { .fw_name = "bi_tcxo" },
129 { .fw_name = "gcc_disp_gpll0_clk" },
132 static const struct parent_map disp_cc_parent_map_6[] = {
134 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
137 static const struct clk_parent_data disp_cc_parent_data_6[] = {
138 { .fw_name = "bi_tcxo" },
139 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
142 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
143 F(19200000, P_BI_TCXO, 1, 0, 0),
144 F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
145 F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
149 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
153 .parent_map = disp_cc_parent_map_5,
154 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
155 .clkr.hw.init = &(struct clk_init_data){
156 .name = "disp_cc_mdss_ahb_clk_src",
157 .parent_data = disp_cc_parent_data_5,
158 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
159 .ops = &clk_rcg2_shared_ops,
163 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
167 .parent_map = disp_cc_parent_map_2,
168 .clkr.hw.init = &(struct clk_init_data){
169 .name = "disp_cc_mdss_byte0_clk_src",
170 .parent_data = disp_cc_parent_data_2,
171 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
172 .flags = CLK_SET_RATE_PARENT,
173 .ops = &clk_byte2_ops,
177 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
178 F(19200000, P_BI_TCXO, 1, 0, 0),
182 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
186 .parent_map = disp_cc_parent_map_0,
187 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
188 .clkr.hw.init = &(struct clk_init_data){
189 .name = "disp_cc_mdss_dp_aux_clk_src",
190 .parent_data = disp_cc_parent_data_0,
191 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
192 .ops = &clk_rcg2_ops,
196 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
200 .parent_map = disp_cc_parent_map_1,
201 .clkr.hw.init = &(struct clk_init_data){
202 .name = "disp_cc_mdss_dp_crypto_clk_src",
203 .parent_data = disp_cc_parent_data_1,
204 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
205 .ops = &clk_byte2_ops,
209 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
213 .parent_map = disp_cc_parent_map_1,
214 .clkr.hw.init = &(struct clk_init_data){
215 .name = "disp_cc_mdss_dp_link_clk_src",
216 .parent_data = disp_cc_parent_data_1,
217 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
218 .ops = &clk_byte2_ops,
222 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
226 .parent_map = disp_cc_parent_map_1,
227 .clkr.hw.init = &(struct clk_init_data){
228 .name = "disp_cc_mdss_dp_pixel_clk_src",
229 .parent_data = disp_cc_parent_data_1,
230 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
235 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
239 .parent_map = disp_cc_parent_map_0,
240 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
241 .clkr.hw.init = &(struct clk_init_data){
242 .name = "disp_cc_mdss_edp_aux_clk_src",
243 .parent_data = disp_cc_parent_data_0,
244 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
245 .ops = &clk_rcg2_ops,
249 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
253 .parent_map = disp_cc_parent_map_3,
254 .clkr.hw.init = &(struct clk_init_data){
255 .name = "disp_cc_mdss_edp_link_clk_src",
256 .parent_data = disp_cc_parent_data_3,
257 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
258 .flags = CLK_SET_RATE_PARENT,
259 .ops = &clk_byte2_ops,
263 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
267 .parent_map = disp_cc_parent_map_3,
268 .clkr.hw.init = &(struct clk_init_data){
269 .name = "disp_cc_mdss_edp_pixel_clk_src",
270 .parent_data = disp_cc_parent_data_3,
271 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
276 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
280 .parent_map = disp_cc_parent_map_2,
281 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
282 .clkr.hw.init = &(struct clk_init_data){
283 .name = "disp_cc_mdss_esc0_clk_src",
284 .parent_data = disp_cc_parent_data_2,
285 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
286 .ops = &clk_rcg2_ops,
290 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
291 F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
292 F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
293 F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
294 F(506666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
295 F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
299 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
303 .parent_map = disp_cc_parent_map_4,
304 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
305 .clkr.hw.init = &(struct clk_init_data){
306 .name = "disp_cc_mdss_mdp_clk_src",
307 .parent_data = disp_cc_parent_data_4,
308 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
309 .ops = &clk_rcg2_shared_ops,
313 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
317 .parent_map = disp_cc_parent_map_6,
318 .clkr.hw.init = &(struct clk_init_data){
319 .name = "disp_cc_mdss_pclk0_clk_src",
320 .parent_data = disp_cc_parent_data_6,
321 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
322 .flags = CLK_SET_RATE_PARENT,
323 .ops = &clk_pixel_ops,
327 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
331 .parent_map = disp_cc_parent_map_4,
332 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
333 .clkr.hw.init = &(struct clk_init_data){
334 .name = "disp_cc_mdss_rot_clk_src",
335 .parent_data = disp_cc_parent_data_4,
336 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
337 .ops = &clk_rcg2_shared_ops,
341 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
345 .parent_map = disp_cc_parent_map_0,
346 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
347 .clkr.hw.init = &(struct clk_init_data){
348 .name = "disp_cc_mdss_vsync_clk_src",
349 .parent_data = disp_cc_parent_data_0,
350 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
351 .ops = &clk_rcg2_ops,
355 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
359 .clkr.hw.init = &(struct clk_init_data) {
360 .name = "disp_cc_mdss_byte0_div_clk_src",
361 .parent_hws = (const struct clk_hw*[]){
362 &disp_cc_mdss_byte0_clk_src.clkr.hw,
365 .ops = &clk_regmap_div_ops,
369 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
373 .clkr.hw.init = &(struct clk_init_data) {
374 .name = "disp_cc_mdss_dp_link_div_clk_src",
375 .parent_hws = (const struct clk_hw*[]){
376 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
379 .ops = &clk_regmap_div_ro_ops,
383 static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
387 .clkr.hw.init = &(struct clk_init_data) {
388 .name = "disp_cc_mdss_edp_link_div_clk_src",
389 .parent_hws = (const struct clk_hw*[]){
390 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
393 .ops = &clk_regmap_div_ro_ops,
397 static struct clk_branch disp_cc_mdss_ahb_clk = {
399 .halt_check = BRANCH_HALT,
401 .enable_reg = 0x1050,
402 .enable_mask = BIT(0),
403 .hw.init = &(struct clk_init_data){
404 .name = "disp_cc_mdss_ahb_clk",
405 .parent_hws = (const struct clk_hw*[]){
406 &disp_cc_mdss_ahb_clk_src.clkr.hw,
409 .flags = CLK_SET_RATE_PARENT,
410 .ops = &clk_branch2_ops,
415 static struct clk_branch disp_cc_mdss_byte0_clk = {
417 .halt_check = BRANCH_HALT,
419 .enable_reg = 0x1030,
420 .enable_mask = BIT(0),
421 .hw.init = &(struct clk_init_data){
422 .name = "disp_cc_mdss_byte0_clk",
423 .parent_hws = (const struct clk_hw*[]){
424 &disp_cc_mdss_byte0_clk_src.clkr.hw,
427 .flags = CLK_SET_RATE_PARENT,
428 .ops = &clk_branch2_ops,
433 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
435 .halt_check = BRANCH_HALT,
437 .enable_reg = 0x1034,
438 .enable_mask = BIT(0),
439 .hw.init = &(struct clk_init_data){
440 .name = "disp_cc_mdss_byte0_intf_clk",
441 .parent_hws = (const struct clk_hw*[]){
442 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
445 .flags = CLK_SET_RATE_PARENT,
446 .ops = &clk_branch2_ops,
451 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
453 .halt_check = BRANCH_HALT,
455 .enable_reg = 0x104c,
456 .enable_mask = BIT(0),
457 .hw.init = &(struct clk_init_data){
458 .name = "disp_cc_mdss_dp_aux_clk",
459 .parent_hws = (const struct clk_hw*[]){
460 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
463 .flags = CLK_SET_RATE_PARENT,
464 .ops = &clk_branch2_ops,
469 static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
471 .halt_check = BRANCH_HALT,
473 .enable_reg = 0x1044,
474 .enable_mask = BIT(0),
475 .hw.init = &(struct clk_init_data){
476 .name = "disp_cc_mdss_dp_crypto_clk",
477 .parent_hws = (const struct clk_hw*[]){
478 &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
481 .flags = CLK_SET_RATE_PARENT,
482 .ops = &clk_branch2_ops,
487 static struct clk_branch disp_cc_mdss_dp_link_clk = {
489 .halt_check = BRANCH_HALT,
491 .enable_reg = 0x103c,
492 .enable_mask = BIT(0),
493 .hw.init = &(struct clk_init_data){
494 .name = "disp_cc_mdss_dp_link_clk",
495 .parent_hws = (const struct clk_hw*[]){
496 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
499 .flags = CLK_SET_RATE_PARENT,
500 .ops = &clk_branch2_ops,
505 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
507 .halt_check = BRANCH_HALT,
509 .enable_reg = 0x1040,
510 .enable_mask = BIT(0),
511 .hw.init = &(struct clk_init_data){
512 .name = "disp_cc_mdss_dp_link_intf_clk",
513 .parent_hws = (const struct clk_hw*[]){
514 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
517 .flags = CLK_SET_RATE_PARENT,
518 .ops = &clk_branch2_ops,
523 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
525 .halt_check = BRANCH_HALT,
527 .enable_reg = 0x1048,
528 .enable_mask = BIT(0),
529 .hw.init = &(struct clk_init_data){
530 .name = "disp_cc_mdss_dp_pixel_clk",
531 .parent_hws = (const struct clk_hw*[]){
532 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
535 .flags = CLK_SET_RATE_PARENT,
536 .ops = &clk_branch2_ops,
541 static struct clk_branch disp_cc_mdss_edp_aux_clk = {
543 .halt_check = BRANCH_HALT,
545 .enable_reg = 0x1060,
546 .enable_mask = BIT(0),
547 .hw.init = &(struct clk_init_data){
548 .name = "disp_cc_mdss_edp_aux_clk",
549 .parent_hws = (const struct clk_hw*[]){
550 &disp_cc_mdss_edp_aux_clk_src.clkr.hw,
553 .flags = CLK_SET_RATE_PARENT,
554 .ops = &clk_branch2_ops,
559 static struct clk_branch disp_cc_mdss_edp_link_clk = {
561 .halt_check = BRANCH_HALT,
563 .enable_reg = 0x1058,
564 .enable_mask = BIT(0),
565 .hw.init = &(struct clk_init_data){
566 .name = "disp_cc_mdss_edp_link_clk",
567 .parent_hws = (const struct clk_hw*[]){
568 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
571 .flags = CLK_SET_RATE_PARENT,
572 .ops = &clk_branch2_ops,
577 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
579 .halt_check = BRANCH_HALT,
581 .enable_reg = 0x105c,
582 .enable_mask = BIT(0),
583 .hw.init = &(struct clk_init_data){
584 .name = "disp_cc_mdss_edp_link_intf_clk",
585 .parent_hws = (const struct clk_hw*[]){
586 &disp_cc_mdss_edp_link_div_clk_src.clkr.hw
589 .flags = CLK_SET_RATE_PARENT,
590 .ops = &clk_branch2_ops,
595 static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
597 .halt_check = BRANCH_HALT,
599 .enable_reg = 0x1054,
600 .enable_mask = BIT(0),
601 .hw.init = &(struct clk_init_data){
602 .name = "disp_cc_mdss_edp_pixel_clk",
603 .parent_hws = (const struct clk_hw*[]){
604 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
607 .flags = CLK_SET_RATE_PARENT,
608 .ops = &clk_branch2_ops,
613 static struct clk_branch disp_cc_mdss_esc0_clk = {
615 .halt_check = BRANCH_HALT,
617 .enable_reg = 0x1038,
618 .enable_mask = BIT(0),
619 .hw.init = &(struct clk_init_data){
620 .name = "disp_cc_mdss_esc0_clk",
621 .parent_hws = (const struct clk_hw*[]){
622 &disp_cc_mdss_esc0_clk_src.clkr.hw,
625 .flags = CLK_SET_RATE_PARENT,
626 .ops = &clk_branch2_ops,
631 static struct clk_branch disp_cc_mdss_mdp_clk = {
633 .halt_check = BRANCH_HALT,
635 .enable_reg = 0x1014,
636 .enable_mask = BIT(0),
637 .hw.init = &(struct clk_init_data){
638 .name = "disp_cc_mdss_mdp_clk",
639 .parent_hws = (const struct clk_hw*[]){
640 &disp_cc_mdss_mdp_clk_src.clkr.hw,
643 .flags = CLK_SET_RATE_PARENT,
644 .ops = &clk_branch2_ops,
649 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
651 .halt_check = BRANCH_HALT_VOTED,
653 .enable_reg = 0x1024,
654 .enable_mask = BIT(0),
655 .hw.init = &(struct clk_init_data){
656 .name = "disp_cc_mdss_mdp_lut_clk",
657 .parent_hws = (const struct clk_hw*[]){
658 &disp_cc_mdss_mdp_clk_src.clkr.hw,
661 .flags = CLK_SET_RATE_PARENT,
662 .ops = &clk_branch2_ops,
667 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
669 .halt_check = BRANCH_HALT_VOTED,
671 .enable_reg = 0x2004,
672 .enable_mask = BIT(0),
673 .hw.init = &(struct clk_init_data){
674 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
675 .parent_hws = (const struct clk_hw*[]){
676 &disp_cc_mdss_ahb_clk_src.clkr.hw,
679 .flags = CLK_SET_RATE_PARENT,
680 .ops = &clk_branch2_ops,
685 static struct clk_branch disp_cc_mdss_pclk0_clk = {
687 .halt_check = BRANCH_HALT,
689 .enable_reg = 0x1010,
690 .enable_mask = BIT(0),
691 .hw.init = &(struct clk_init_data){
692 .name = "disp_cc_mdss_pclk0_clk",
693 .parent_hws = (const struct clk_hw*[]){
694 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
697 .flags = CLK_SET_RATE_PARENT,
698 .ops = &clk_branch2_ops,
703 static struct clk_branch disp_cc_mdss_rot_clk = {
705 .halt_check = BRANCH_HALT,
707 .enable_reg = 0x101c,
708 .enable_mask = BIT(0),
709 .hw.init = &(struct clk_init_data){
710 .name = "disp_cc_mdss_rot_clk",
711 .parent_hws = (const struct clk_hw*[]){
712 &disp_cc_mdss_rot_clk_src.clkr.hw,
715 .flags = CLK_SET_RATE_PARENT,
716 .ops = &clk_branch2_ops,
721 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
723 .halt_check = BRANCH_HALT,
725 .enable_reg = 0x200c,
726 .enable_mask = BIT(0),
727 .hw.init = &(struct clk_init_data){
728 .name = "disp_cc_mdss_rscc_ahb_clk",
729 .parent_hws = (const struct clk_hw*[]){
730 &disp_cc_mdss_ahb_clk_src.clkr.hw,
733 .flags = CLK_SET_RATE_PARENT,
734 .ops = &clk_branch2_ops,
739 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
741 .halt_check = BRANCH_HALT,
743 .enable_reg = 0x2008,
744 .enable_mask = BIT(0),
745 .hw.init = &(struct clk_init_data){
746 .name = "disp_cc_mdss_rscc_vsync_clk",
747 .parent_hws = (const struct clk_hw*[]){
748 &disp_cc_mdss_vsync_clk_src.clkr.hw,
751 .flags = CLK_SET_RATE_PARENT,
752 .ops = &clk_branch2_ops,
757 static struct clk_branch disp_cc_mdss_vsync_clk = {
759 .halt_check = BRANCH_HALT,
761 .enable_reg = 0x102c,
762 .enable_mask = BIT(0),
763 .hw.init = &(struct clk_init_data){
764 .name = "disp_cc_mdss_vsync_clk",
765 .parent_hws = (const struct clk_hw*[]){
766 &disp_cc_mdss_vsync_clk_src.clkr.hw,
769 .flags = CLK_SET_RATE_PARENT,
770 .ops = &clk_branch2_ops,
775 static struct clk_branch disp_cc_sleep_clk = {
777 .halt_check = BRANCH_HALT,
779 .enable_reg = 0x5004,
780 .enable_mask = BIT(0),
781 .hw.init = &(struct clk_init_data){
782 .name = "disp_cc_sleep_clk",
783 .ops = &clk_branch2_ops,
788 static struct gdsc disp_cc_mdss_core_gdsc = {
790 .en_rest_wait_val = 0x2,
791 .en_few_wait_val = 0x2,
792 .clk_dis_wait_val = 0xf,
794 .name = "disp_cc_mdss_core_gdsc",
796 .pwrsts = PWRSTS_OFF_ON,
797 .flags = HW_CTRL | RETAIN_FF_ENABLE,
800 static struct clk_regmap *disp_cc_sc7280_clocks[] = {
801 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
802 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
803 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
804 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
805 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
806 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
807 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
808 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
809 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
810 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
811 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
812 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
813 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
814 &disp_cc_mdss_dp_link_div_clk_src.clkr,
815 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
816 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
817 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
818 [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
819 [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
820 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
821 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
822 [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] =
823 &disp_cc_mdss_edp_link_div_clk_src.clkr,
824 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
825 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
826 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
827 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
828 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
829 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
830 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
831 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
832 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
833 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
834 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
835 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
836 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
837 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
838 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
839 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
840 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
841 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
842 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
845 static struct gdsc *disp_cc_sc7280_gdscs[] = {
846 [DISP_CC_MDSS_CORE_GDSC] = &disp_cc_mdss_core_gdsc,
849 static const struct regmap_config disp_cc_sc7280_regmap_config = {
853 .max_register = 0x10000,
857 static const struct qcom_cc_desc disp_cc_sc7280_desc = {
858 .config = &disp_cc_sc7280_regmap_config,
859 .clks = disp_cc_sc7280_clocks,
860 .num_clks = ARRAY_SIZE(disp_cc_sc7280_clocks),
861 .gdscs = disp_cc_sc7280_gdscs,
862 .num_gdscs = ARRAY_SIZE(disp_cc_sc7280_gdscs),
865 static const struct of_device_id disp_cc_sc7280_match_table[] = {
866 { .compatible = "qcom,sc7280-dispcc" },
869 MODULE_DEVICE_TABLE(of, disp_cc_sc7280_match_table);
871 static int disp_cc_sc7280_probe(struct platform_device *pdev)
873 struct regmap *regmap;
875 regmap = qcom_cc_map(pdev, &disp_cc_sc7280_desc);
877 return PTR_ERR(regmap);
879 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
882 * Keep the clocks always-ON
885 regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0));
887 return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap);
890 static struct platform_driver disp_cc_sc7280_driver = {
891 .probe = disp_cc_sc7280_probe,
893 .name = "disp_cc-sc7280",
894 .of_match_table = disp_cc_sc7280_match_table,
898 static int __init disp_cc_sc7280_init(void)
900 return platform_driver_register(&disp_cc_sc7280_driver);
902 subsys_initcall(disp_cc_sc7280_init);
904 static void __exit disp_cc_sc7280_exit(void)
906 platform_driver_unregister(&disp_cc_sc7280_driver);
908 module_exit(disp_cc_sc7280_exit);
910 MODULE_DESCRIPTION("QTI DISP_CC sc7280 Driver");
911 MODULE_LICENSE("GPL v2");