2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
21 #include <linux/serial.h>
22 #include <linux/serial_reg.h>
24 #include "dgnc_driver.h"
28 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
29 static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
30 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
31 static inline void neo_clear_break(struct channel_t *ch, int force);
32 static inline void neo_set_cts_flow_control(struct channel_t *ch);
33 static inline void neo_set_rts_flow_control(struct channel_t *ch);
34 static inline void neo_set_ixon_flow_control(struct channel_t *ch);
35 static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
36 static inline void neo_set_no_output_flow_control(struct channel_t *ch);
37 static inline void neo_set_no_input_flow_control(struct channel_t *ch);
38 static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
39 static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
40 static void neo_tasklet(unsigned long data);
41 static void neo_vpd(struct dgnc_board *brd);
42 static void neo_uart_init(struct channel_t *ch);
43 static void neo_uart_off(struct channel_t *ch);
44 static int neo_drain(struct tty_struct *tty, uint seconds);
45 static void neo_param(struct tty_struct *tty);
46 static void neo_assert_modem_signals(struct channel_t *ch);
47 static void neo_flush_uart_write(struct channel_t *ch);
48 static void neo_flush_uart_read(struct channel_t *ch);
49 static void neo_disable_receiver(struct channel_t *ch);
50 static void neo_enable_receiver(struct channel_t *ch);
51 static void neo_send_break(struct channel_t *ch, int msecs);
52 static void neo_send_start_character(struct channel_t *ch);
53 static void neo_send_stop_character(struct channel_t *ch);
54 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
55 static uint neo_get_uart_bytes_left(struct channel_t *ch);
56 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
57 static irqreturn_t neo_intr(int irq, void *voidbrd);
59 struct board_ops dgnc_neo_ops = {
60 .tasklet = neo_tasklet,
62 .uart_init = neo_uart_init,
63 .uart_off = neo_uart_off,
67 .assert_modem_signals = neo_assert_modem_signals,
68 .flush_uart_write = neo_flush_uart_write,
69 .flush_uart_read = neo_flush_uart_read,
70 .disable_receiver = neo_disable_receiver,
71 .enable_receiver = neo_enable_receiver,
72 .send_break = neo_send_break,
73 .send_start_character = neo_send_start_character,
74 .send_stop_character = neo_send_stop_character,
75 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
76 .get_uart_bytes_left = neo_get_uart_bytes_left,
77 .send_immediate_char = neo_send_immediate_char
81 * This function allows calls to ensure that all outstanding
82 * PCI writes have been completed, by doing a PCI read against
83 * a non-destructive, read-only location on the Neo card.
85 * In this case, we are reading the DVID (Read-only Device Identification)
86 * value of the Neo card.
88 static inline void neo_pci_posting_flush(struct dgnc_board *bd)
90 readb(bd->re_map_membase + 0x8D);
93 static inline void neo_set_cts_flow_control(struct channel_t *ch)
95 unsigned char ier = readb(&ch->ch_neo_uart->ier);
96 unsigned char efr = readb(&ch->ch_neo_uart->efr);
98 /* Turn on auto CTS flow control */
99 ier |= UART_17158_IER_CTSDSR;
100 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
102 /* Turn off auto Xon flow control */
103 efr &= ~UART_17158_EFR_IXON;
106 * Why? Because Exar's spec says we have to zero it
107 * out before setting it
109 writeb(0, &ch->ch_neo_uart->efr);
111 /* Turn on UART enhanced bits */
112 writeb(efr, &ch->ch_neo_uart->efr);
114 /* Turn on table D, with 8 char hi/low watermarks */
115 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
116 &ch->ch_neo_uart->fctr);
118 /* Feed the UART our trigger levels */
119 writeb(8, &ch->ch_neo_uart->tfifo);
122 writeb(ier, &ch->ch_neo_uart->ier);
124 neo_pci_posting_flush(ch->ch_bd);
127 static inline void neo_set_rts_flow_control(struct channel_t *ch)
129 unsigned char ier = readb(&ch->ch_neo_uart->ier);
130 unsigned char efr = readb(&ch->ch_neo_uart->efr);
132 /* Turn on auto RTS flow control */
133 ier |= UART_17158_IER_RTSDTR;
134 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
136 /* Turn off auto Xoff flow control */
137 ier &= ~UART_17158_IER_XOFF;
138 efr &= ~UART_17158_EFR_IXOFF;
141 * Why? Because Exar's spec says we have to zero it
142 * out before setting it
144 writeb(0, &ch->ch_neo_uart->efr);
146 /* Turn on UART enhanced bits */
147 writeb(efr, &ch->ch_neo_uart->efr);
149 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
150 &ch->ch_neo_uart->fctr);
151 ch->ch_r_watermark = 4;
153 writeb(32, &ch->ch_neo_uart->rfifo);
154 ch->ch_r_tlevel = 32;
156 writeb(ier, &ch->ch_neo_uart->ier);
159 * From the Neo UART spec sheet:
160 * The auto RTS/DTR function must be started by asserting
161 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
164 ch->ch_mostat |= UART_MCR_RTS;
166 neo_pci_posting_flush(ch->ch_bd);
169 static inline void neo_set_ixon_flow_control(struct channel_t *ch)
171 unsigned char ier = readb(&ch->ch_neo_uart->ier);
172 unsigned char efr = readb(&ch->ch_neo_uart->efr);
174 /* Turn off auto CTS flow control */
175 ier &= ~UART_17158_IER_CTSDSR;
176 efr &= ~UART_17158_EFR_CTSDSR;
178 /* Turn on auto Xon flow control */
179 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
182 * Why? Because Exar's spec says we have to zero it
183 * out before setting it
185 writeb(0, &ch->ch_neo_uart->efr);
187 /* Turn on UART enhanced bits */
188 writeb(efr, &ch->ch_neo_uart->efr);
190 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
191 &ch->ch_neo_uart->fctr);
192 ch->ch_r_watermark = 4;
194 writeb(32, &ch->ch_neo_uart->rfifo);
195 ch->ch_r_tlevel = 32;
197 /* Tell UART what start/stop chars it should be looking for */
198 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
199 writeb(0, &ch->ch_neo_uart->xonchar2);
201 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
202 writeb(0, &ch->ch_neo_uart->xoffchar2);
204 writeb(ier, &ch->ch_neo_uart->ier);
206 neo_pci_posting_flush(ch->ch_bd);
209 static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
211 unsigned char ier = readb(&ch->ch_neo_uart->ier);
212 unsigned char efr = readb(&ch->ch_neo_uart->efr);
214 /* Turn off auto RTS flow control */
215 ier &= ~UART_17158_IER_RTSDTR;
216 efr &= ~UART_17158_EFR_RTSDTR;
218 /* Turn on auto Xoff flow control */
219 ier |= UART_17158_IER_XOFF;
220 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
223 * Why? Because Exar's spec says we have to zero it
224 * out before setting it
226 writeb(0, &ch->ch_neo_uart->efr);
228 /* Turn on UART enhanced bits */
229 writeb(efr, &ch->ch_neo_uart->efr);
231 /* Turn on table D, with 8 char hi/low watermarks */
232 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
233 &ch->ch_neo_uart->fctr);
235 writeb(8, &ch->ch_neo_uart->tfifo);
238 /* Tell UART what start/stop chars it should be looking for */
239 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
240 writeb(0, &ch->ch_neo_uart->xonchar2);
242 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
243 writeb(0, &ch->ch_neo_uart->xoffchar2);
245 writeb(ier, &ch->ch_neo_uart->ier);
247 neo_pci_posting_flush(ch->ch_bd);
250 static inline void neo_set_no_input_flow_control(struct channel_t *ch)
252 unsigned char ier = readb(&ch->ch_neo_uart->ier);
253 unsigned char efr = readb(&ch->ch_neo_uart->efr);
255 /* Turn off auto RTS flow control */
256 ier &= ~UART_17158_IER_RTSDTR;
257 efr &= ~UART_17158_EFR_RTSDTR;
259 /* Turn off auto Xoff flow control */
260 ier &= ~UART_17158_IER_XOFF;
261 if (ch->ch_c_iflag & IXON)
262 efr &= ~(UART_17158_EFR_IXOFF);
264 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
267 * Why? Because Exar's spec says we have to zero
268 * it out before setting it
270 writeb(0, &ch->ch_neo_uart->efr);
272 /* Turn on UART enhanced bits */
273 writeb(efr, &ch->ch_neo_uart->efr);
275 /* Turn on table D, with 8 char hi/low watermarks */
276 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
277 &ch->ch_neo_uart->fctr);
279 ch->ch_r_watermark = 0;
281 writeb(16, &ch->ch_neo_uart->tfifo);
282 ch->ch_t_tlevel = 16;
284 writeb(16, &ch->ch_neo_uart->rfifo);
285 ch->ch_r_tlevel = 16;
287 writeb(ier, &ch->ch_neo_uart->ier);
289 neo_pci_posting_flush(ch->ch_bd);
292 static inline void neo_set_no_output_flow_control(struct channel_t *ch)
294 unsigned char ier = readb(&ch->ch_neo_uart->ier);
295 unsigned char efr = readb(&ch->ch_neo_uart->efr);
297 /* Turn off auto CTS flow control */
298 ier &= ~UART_17158_IER_CTSDSR;
299 efr &= ~UART_17158_EFR_CTSDSR;
301 /* Turn off auto Xon flow control */
302 if (ch->ch_c_iflag & IXOFF)
303 efr &= ~UART_17158_EFR_IXON;
305 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
308 * Why? Because Exar's spec says we have to zero it
309 * out before setting it
311 writeb(0, &ch->ch_neo_uart->efr);
313 /* Turn on UART enhanced bits */
314 writeb(efr, &ch->ch_neo_uart->efr);
316 /* Turn on table D, with 8 char hi/low watermarks */
317 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
318 &ch->ch_neo_uart->fctr);
320 ch->ch_r_watermark = 0;
322 writeb(16, &ch->ch_neo_uart->tfifo);
323 ch->ch_t_tlevel = 16;
325 writeb(16, &ch->ch_neo_uart->rfifo);
326 ch->ch_r_tlevel = 16;
328 writeb(ier, &ch->ch_neo_uart->ier);
330 neo_pci_posting_flush(ch->ch_bd);
333 /* change UARTs start/stop chars */
334 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
336 /* if hardware flow control is set, then skip this whole thing */
337 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) ||
338 ch->ch_c_cflag & CRTSCTS)
341 /* Tell UART what start/stop chars it should be looking for */
342 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
343 writeb(0, &ch->ch_neo_uart->xonchar2);
345 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
346 writeb(0, &ch->ch_neo_uart->xoffchar2);
348 neo_pci_posting_flush(ch->ch_bd);
351 /* No locks are assumed to be held when calling this function. */
352 static inline void neo_clear_break(struct channel_t *ch, int force)
356 spin_lock_irqsave(&ch->ch_lock, flags);
358 if (!ch->ch_stop_sending_break) {
359 spin_unlock_irqrestore(&ch->ch_lock, flags);
363 if (ch->ch_flags & CH_BREAK_SENDING) {
365 time_after_eq(jiffies, ch->ch_stop_sending_break)) {
366 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
368 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
369 neo_pci_posting_flush(ch->ch_bd);
370 ch->ch_flags &= ~(CH_BREAK_SENDING);
371 ch->ch_stop_sending_break = 0;
374 spin_unlock_irqrestore(&ch->ch_lock, flags);
377 /* Parse the ISR register. */
378 static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
380 struct channel_t *ch;
385 ch = brd->channels[port];
389 /* Here we try to figure out what caused the interrupt to happen */
391 isr = readb(&ch->ch_neo_uart->isr_fcr);
393 if (isr & UART_IIR_NO_INT)
397 * Yank off the upper 2 bits,
398 * which just show that the FIFO's are enabled.
400 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
402 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
403 /* Read data from uart -> queue */
404 neo_copy_data_from_uart_to_queue(ch);
406 * Call our tty layer to enforce queue
407 * flow control if needed.
409 spin_lock_irqsave(&ch->ch_lock, flags);
410 dgnc_check_queue_flow_control(ch);
411 spin_unlock_irqrestore(&ch->ch_lock, flags);
414 if (isr & UART_IIR_THRI) {
415 spin_lock_irqsave(&ch->ch_lock, flags);
416 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
417 spin_unlock_irqrestore(&ch->ch_lock, flags);
418 neo_copy_data_from_queue_to_uart(ch);
421 if (isr & UART_17158_IIR_XONXOFF) {
422 cause = readb(&ch->ch_neo_uart->xoffchar1);
425 * Since the UART detected either an XON or
426 * XOFF match, we need to figure out which
427 * one it was, so we can suspend or resume data flow.
429 if (cause == UART_17158_XON_DETECT) {
430 /* resume output if stopped */
431 if (brd->channels[port]->ch_flags & CH_STOP) {
432 spin_lock_irqsave(&ch->ch_lock,
434 ch->ch_flags &= ~(CH_STOP);
435 spin_unlock_irqrestore(&ch->ch_lock,
438 } else if (cause == UART_17158_XOFF_DETECT) {
439 if (!(brd->channels[port]->ch_flags &
441 spin_lock_irqsave(&ch->ch_lock,
443 ch->ch_flags |= CH_STOP;
444 spin_unlock_irqrestore(&ch->ch_lock,
450 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
452 * If we get here, this means the hardware is
453 * doing auto flow control. Check to see whether
454 * RTS/DTR or CTS/DSR caused this interrupt.
456 cause = readb(&ch->ch_neo_uart->mcr);
457 /* Which pin is doing auto flow? RTS or DTR? */
458 if ((cause & 0x4) == 0) {
459 if (cause & UART_MCR_RTS) {
460 spin_lock_irqsave(&ch->ch_lock,
462 ch->ch_mostat |= UART_MCR_RTS;
463 spin_unlock_irqrestore(&ch->ch_lock,
466 spin_lock_irqsave(&ch->ch_lock,
468 ch->ch_mostat &= ~(UART_MCR_RTS);
469 spin_unlock_irqrestore(&ch->ch_lock,
473 if (cause & UART_MCR_DTR) {
474 spin_lock_irqsave(&ch->ch_lock,
476 ch->ch_mostat |= UART_MCR_DTR;
477 spin_unlock_irqrestore(&ch->ch_lock,
480 spin_lock_irqsave(&ch->ch_lock,
482 ch->ch_mostat &= ~(UART_MCR_DTR);
483 spin_unlock_irqrestore(&ch->ch_lock,
489 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
493 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
495 struct channel_t *ch;
502 if (port >= brd->maxports)
505 ch = brd->channels[port];
509 linestatus = readb(&ch->ch_neo_uart->lsr);
511 ch->ch_cached_lsr |= linestatus;
513 if (ch->ch_cached_lsr & UART_LSR_DR) {
514 neo_copy_data_from_uart_to_queue(ch);
515 spin_lock_irqsave(&ch->ch_lock, flags);
516 dgnc_check_queue_flow_control(ch);
517 spin_unlock_irqrestore(&ch->ch_lock, flags);
521 * The next 3 tests should *NOT* happen, as the above test
522 * should encapsulate all 3... At least, thats what Exar says.
525 if (linestatus & UART_LSR_PE)
528 if (linestatus & UART_LSR_FE)
531 if (linestatus & UART_LSR_BI)
534 if (linestatus & UART_LSR_OE) {
536 * Rx Oruns. Exar says that an orun will NOT corrupt
537 * the FIFO. It will just replace the holding register
538 * with this new data byte. So basically just ignore this.
539 * Probably we should eventually have an orun stat in our
542 ch->ch_err_overrun++;
545 if (linestatus & UART_LSR_THRE) {
546 spin_lock_irqsave(&ch->ch_lock, flags);
547 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
548 spin_unlock_irqrestore(&ch->ch_lock, flags);
550 neo_copy_data_from_queue_to_uart(ch);
551 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
552 spin_lock_irqsave(&ch->ch_lock, flags);
553 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
554 spin_unlock_irqrestore(&ch->ch_lock, flags);
556 neo_copy_data_from_queue_to_uart(ch);
560 /* Send any/all changes to the line to the UART. */
561 static void neo_param(struct tty_struct *tty)
563 unsigned char lcr = 0;
564 unsigned char uart_lcr = 0;
565 unsigned char ier = 0;
566 unsigned char uart_ier = 0;
569 struct dgnc_board *bd;
570 struct channel_t *ch;
576 un = (struct un_t *)tty->driver_data;
588 /* If baud rate is zero, flush queues, and set mval to drop DTR. */
589 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
597 neo_flush_uart_write(ch);
598 neo_flush_uart_read(ch);
600 /* The baudrate is B0 so all modem lines are to be dropped. */
601 ch->ch_flags |= (CH_BAUD0);
602 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
603 neo_assert_modem_signals(ch);
607 } else if (ch->ch_custom_speed) {
608 baud = ch->ch_custom_speed;
609 /* Handle transition from B0 */
610 if (ch->ch_flags & CH_BAUD0) {
611 ch->ch_flags &= ~(CH_BAUD0);
614 * Bring back up RTS and DTR...
615 * Also handle RTS or DTR toggle if set.
617 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
618 ch->ch_mostat |= (UART_MCR_RTS);
619 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
620 ch->ch_mostat |= (UART_MCR_DTR);
626 ulong bauds[4][16] = {
630 600, 1200, 1800, 2400,
631 4800, 9600, 19200, 38400 },
632 { /* slowbaud & CBAUDEX */
633 0, 57600, 115200, 230400,
634 460800, 150, 200, 921600,
635 600, 1200, 1800, 2400,
636 4800, 9600, 19200, 38400 },
638 0, 57600, 76800, 115200,
639 131657, 153600, 230400, 460800,
640 921600, 1200, 1800, 2400,
641 4800, 9600, 19200, 38400 },
642 { /* fastbaud & CBAUDEX */
643 0, 57600, 115200, 230400,
644 460800, 150, 200, 921600,
645 600, 1200, 1800, 2400,
646 4800, 9600, 19200, 38400 }
650 * Only use the TXPrint baud rate if the terminal unit
653 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
654 (un->un_type == DGNC_PRINT))
655 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
657 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
659 if (ch->ch_c_cflag & CBAUDEX)
662 if (ch->ch_digi.digi_flags & DIGI_FAST)
667 if ((iindex >= 0) && (iindex < 4) &&
668 (jindex >= 0) && (jindex < 16))
669 baud = bauds[iindex][jindex];
676 /* Handle transition from B0 */
677 if (ch->ch_flags & CH_BAUD0) {
678 ch->ch_flags &= ~(CH_BAUD0);
681 * Bring back up RTS and DTR...
682 * Also handle RTS or DTR toggle if set.
684 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
685 ch->ch_mostat |= (UART_MCR_RTS);
686 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
687 ch->ch_mostat |= (UART_MCR_DTR);
691 if (ch->ch_c_cflag & PARENB)
692 lcr |= UART_LCR_PARITY;
694 if (!(ch->ch_c_cflag & PARODD))
695 lcr |= UART_LCR_EPAR;
698 if (ch->ch_c_cflag & CMSPAR)
699 lcr |= UART_LCR_SPAR;
702 if (ch->ch_c_cflag & CSTOPB)
703 lcr |= UART_LCR_STOP;
705 switch (ch->ch_c_cflag & CSIZE) {
707 lcr |= UART_LCR_WLEN5;
710 lcr |= UART_LCR_WLEN6;
713 lcr |= UART_LCR_WLEN7;
717 lcr |= UART_LCR_WLEN8;
721 uart_ier = readb(&ch->ch_neo_uart->ier);
724 uart_lcr = readb(&ch->ch_neo_uart->lcr);
729 quot = ch->ch_bd->bd_dividend / baud;
731 if (quot != 0 && ch->ch_old_baud != baud) {
732 ch->ch_old_baud = baud;
733 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
734 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
735 writeb((quot >> 8), &ch->ch_neo_uart->ier);
736 writeb(lcr, &ch->ch_neo_uart->lcr);
740 writeb(lcr, &ch->ch_neo_uart->lcr);
742 if (ch->ch_c_cflag & CREAD)
743 ier |= (UART_IER_RDI | UART_IER_RLSI);
745 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
748 * Have the UART interrupt on modem signal changes ONLY when
749 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
751 if ((ch->ch_digi.digi_flags & CTSPACE) ||
752 (ch->ch_digi.digi_flags & RTSPACE) ||
753 (ch->ch_c_cflag & CRTSCTS) ||
754 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
755 !(ch->ch_c_cflag & CLOCAL))
758 ier &= ~UART_IER_MSI;
760 ier |= UART_IER_THRI;
763 writeb(ier, &ch->ch_neo_uart->ier);
765 neo_set_new_start_stop_chars(ch);
767 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
768 neo_set_cts_flow_control(ch);
769 } else if (ch->ch_c_iflag & IXON) {
770 if ((ch->ch_startc == _POSIX_VDISABLE) ||
771 (ch->ch_stopc == _POSIX_VDISABLE))
772 neo_set_no_output_flow_control(ch);
774 neo_set_ixon_flow_control(ch);
776 neo_set_no_output_flow_control(ch);
779 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
780 neo_set_rts_flow_control(ch);
781 } else if (ch->ch_c_iflag & IXOFF) {
782 if ((ch->ch_startc == _POSIX_VDISABLE) ||
783 (ch->ch_stopc == _POSIX_VDISABLE))
784 neo_set_no_input_flow_control(ch);
786 neo_set_ixoff_flow_control(ch);
788 neo_set_no_input_flow_control(ch);
792 * Adjust the RX FIFO Trigger level if baud is less than 9600.
793 * Not exactly elegant, but this is needed because of the Exar chip's
794 * delay on firing off the RX FIFO interrupt on slower baud rates.
797 writeb(1, &ch->ch_neo_uart->rfifo);
801 neo_assert_modem_signals(ch);
803 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
806 /* Board poller function. */
807 static void neo_tasklet(unsigned long data)
809 struct dgnc_board *bd = (struct dgnc_board *)data;
810 struct channel_t *ch;
819 spin_lock_irqsave(&bd->bd_lock, flags);
822 spin_unlock_irqrestore(&bd->bd_lock, flags);
825 * Do NOT allow the interrupt routine to read the intr registers
826 * Until we release this lock.
828 spin_lock_irqsave(&bd->bd_intr_lock, flags);
830 if ((state == BOARD_READY) && (ports > 0)) {
831 for (i = 0; i < ports; i++) {
832 ch = bd->channels[i];
837 * NOTE: Remember you CANNOT hold any channel
838 * locks when calling the input routine.
840 * During input processing, its possible we
841 * will call the Linux ld, which might in turn,
842 * do a callback right back into us, resulting
843 * in us trying to grab the channel lock twice!
848 * Channel lock is grabbed and then released
849 * inside both of these routines, but neither
850 * call anything else that could call back into us.
852 neo_copy_data_from_queue_to_uart(ch);
853 dgnc_wakeup_writes(ch);
858 * Check to see if we need to turn off a sending break.
859 * The timing check is done inside clear_break()
861 if (ch->ch_stop_sending_break)
862 neo_clear_break(ch, 0);
866 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
869 /* Neo specific interrupt handler. */
870 static irqreturn_t neo_intr(int irq, void *voidbrd)
872 struct dgnc_board *brd = voidbrd;
873 struct channel_t *ch;
878 unsigned long flags2;
883 /* Lock out the slow poller from running on this board. */
884 spin_lock_irqsave(&brd->bd_intr_lock, flags);
887 * Read in "extended" IRQ information from the 32bit Neo register.
888 * Bits 0-7: What port triggered the interrupt.
889 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
891 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
894 * If 0, no interrupts pending.
895 * This can happen if the IRQ is shared among a couple Neo/Classic
899 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
903 while ((uart_poll & 0xff) != 0) {
904 type = uart_poll >> (8 + (port * 3));
907 uart_poll &= ~(0x01 << port);
910 case UART_17158_RXRDY_TIMEOUT:
912 * RXRDY Time-out is cleared by reading data in the
913 * RX FIFO until it falls below the trigger level.
916 if (port >= brd->nasync)
919 ch = brd->channels[port];
920 neo_copy_data_from_uart_to_queue(ch);
923 * Call our tty layer to enforce queue flow control if
926 spin_lock_irqsave(&ch->ch_lock, flags2);
927 dgnc_check_queue_flow_control(ch);
928 spin_unlock_irqrestore(&ch->ch_lock, flags2);
932 case UART_17158_RX_LINE_STATUS:
934 /* RXRDY and RX LINE Status (logic OR of LSR[4:1]) */
936 neo_parse_lsr(brd, port);
939 case UART_17158_TXRDY:
941 * TXRDY interrupt clears after reading ISR register
942 * for the UART channel.
946 * Yes, this is odd...
947 * Why would I check EVERY possibility of type of
948 * interrupt, when we know its TXRDY???
949 * Becuz for some reason, even tho we got triggered for
950 * TXRDY, it seems to be occasionally wrong. Instead of
951 * TX, which it should be, I was getting things like
954 neo_parse_isr(brd, port);
958 /* MSR or flow control was seen. */
959 neo_parse_isr(brd, port);
969 tasklet_schedule(&brd->helper_tasklet);
971 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
977 * Neo specific way of turning off the receiver.
978 * Used as a way to enforce queue flow control when in
979 * hardware flow control mode.
981 static void neo_disable_receiver(struct channel_t *ch)
983 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
985 tmp &= ~(UART_IER_RDI);
986 writeb(tmp, &ch->ch_neo_uart->ier);
987 neo_pci_posting_flush(ch->ch_bd);
991 * Neo specific way of turning on the receiver.
992 * Used as a way to un-enforce queue flow control when in
993 * hardware flow control mode.
995 static void neo_enable_receiver(struct channel_t *ch)
997 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
999 tmp |= (UART_IER_RDI);
1000 writeb(tmp, &ch->ch_neo_uart->ier);
1001 neo_pci_posting_flush(ch->ch_bd);
1004 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1007 unsigned char linestatus = 0;
1008 unsigned char error_mask = 0;
1013 unsigned long flags;
1018 spin_lock_irqsave(&ch->ch_lock, flags);
1020 head = ch->ch_r_head & RQUEUEMASK;
1021 tail = ch->ch_r_tail & RQUEUEMASK;
1023 linestatus = ch->ch_cached_lsr;
1024 ch->ch_cached_lsr = 0;
1026 qleft = tail - head - 1;
1028 qleft += RQUEUEMASK + 1;
1030 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1031 /* force the FIFO copy to NOT be run */
1034 total = readb(&ch->ch_neo_uart->rfifo);
1037 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1039 * This resolves a problem/bug with the Exar chip that sometimes
1040 * returns a bogus value in the rfifo register.
1041 * The count can be any where from 0-3 bytes "off".
1042 * Bizarre, but true.
1044 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
1050 total = min(total, qleft);
1053 linestatus = readb(&ch->ch_neo_uart->lsr);
1055 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1058 /* Make sure we don't go over the end of our queue */
1059 n = min(((uint)total), (RQUEUESIZE - (uint)head));
1062 * Cut down n even further if needed, this is to fix
1063 * a problem with memcpy_fromio() with the Neo on the
1064 * IBM pSeries platform.
1065 * 15 bytes max appears to be the magic number.
1067 n = min_t(uint, n, 12);
1070 * Since we are grabbing the linestatus register, which
1071 * will reset some bits after our read, we need to ensure
1072 * we don't miss our TX FIFO emptys.
1074 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
1075 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1079 memcpy_fromio(ch->ch_rqueue + head,
1080 &ch->ch_neo_uart->txrxburst, n);
1083 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
1084 * that all the data currently in the FIFO is free of
1085 * breaks and parity/frame/orun errors.
1087 memset(ch->ch_equeue + head, 0, n);
1089 head = (head + n) & RQUEUEMASK;
1092 ch->ch_rxcount += n;
1096 * Create a mask to determine whether we should
1097 * insert the character (if any) into our queue.
1099 if (ch->ch_c_iflag & IGNBRK)
1100 error_mask |= UART_LSR_BI;
1103 * Now cleanup any leftover bytes still in the UART.
1104 * Also deal with any possible queue overflow here as well.
1108 * Its possible we have a linestatus from the loop above
1109 * this, so we "OR" on any extra bits.
1111 linestatus |= readb(&ch->ch_neo_uart->lsr);
1114 * If the chip tells us there is no more data pending to
1115 * be read, we can then leave.
1116 * But before we do, cache the linestatus, just in case.
1118 if (!(linestatus & UART_LSR_DR)) {
1119 ch->ch_cached_lsr = linestatus;
1123 /* No need to store this bit */
1124 linestatus &= ~UART_LSR_DR;
1127 * Since we are grabbing the linestatus register, which
1128 * will reset some bits after our read, we need to ensure
1129 * we don't miss our TX FIFO emptys.
1131 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1132 linestatus &= ~(UART_LSR_THRE |
1133 UART_17158_TX_AND_FIFO_CLR);
1134 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1137 if (linestatus & error_mask) {
1138 unsigned char discard;
1141 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1146 * If our queue is full, we have no choice but to drop
1147 * some data. The assumption is that HWFLOW or SWFLOW
1148 * should have stopped things way way before we got to
1152 tail = (tail + 1) & RQUEUEMASK;
1153 ch->ch_r_tail = tail;
1154 ch->ch_err_overrun++;
1158 memcpy_fromio(ch->ch_rqueue + head,
1159 &ch->ch_neo_uart->txrxburst, 1);
1160 ch->ch_equeue[head] = (unsigned char)linestatus;
1164 head = (head + 1) & RQUEUEMASK;
1170 ch->ch_r_head = head & RQUEUEMASK;
1171 ch->ch_e_head = head & EQUEUEMASK;
1173 spin_unlock_irqrestore(&ch->ch_lock, flags);
1177 * This function basically goes to sleep for secs, or until
1178 * it gets signalled that the port has fully drained.
1180 static int neo_drain(struct tty_struct *tty, uint seconds)
1182 unsigned long flags;
1183 struct channel_t *ch;
1190 un = (struct un_t *)tty->driver_data;
1198 spin_lock_irqsave(&ch->ch_lock, flags);
1199 un->un_flags |= UN_EMPTY;
1200 spin_unlock_irqrestore(&ch->ch_lock, flags);
1202 rc = wait_event_interruptible_timeout(un->un_flags_wait,
1203 ((un->un_flags & UN_EMPTY) == 0),
1204 msecs_to_jiffies(seconds * 1000));
1206 /* If ret is non-zero, user ctrl-c'ed us */
1211 * Flush the WRITE FIFO on the Neo.
1212 * Channel lock MUST be held before calling this function!
1214 static void neo_flush_uart_write(struct channel_t *ch)
1216 unsigned char tmp = 0;
1222 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1223 &ch->ch_neo_uart->isr_fcr);
1224 neo_pci_posting_flush(ch->ch_bd);
1226 for (i = 0; i < 10; i++) {
1228 * Check to see if the UART completely flushed the FIFO
1231 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1238 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1242 * Flush the READ FIFO on the Neo.
1243 * Channel lock MUST be held before calling this function!
1245 static void neo_flush_uart_read(struct channel_t *ch)
1247 unsigned char tmp = 0;
1253 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1254 &ch->ch_neo_uart->isr_fcr);
1255 neo_pci_posting_flush(ch->ch_bd);
1257 for (i = 0; i < 10; i++) {
1259 * Check to see if the UART feels it completely flushed the
1262 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1270 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1277 uint len_written = 0;
1278 unsigned long flags;
1283 spin_lock_irqsave(&ch->ch_lock, flags);
1285 if (ch->ch_w_tail == ch->ch_w_head)
1288 /* If port is "stopped", don't send any data to the UART */
1289 if ((ch->ch_flags & CH_FORCED_STOP) ||
1290 (ch->ch_flags & CH_BREAK_SENDING))
1293 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1294 /* Send data directly to txrx register */
1295 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
1297 ch->ch_cached_lsr |= lsrbits;
1298 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1299 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1302 * If RTS Toggle mode is on, turn on RTS now if not
1303 * already set, and make sure we get an event when the
1304 * data transfer has completed.
1306 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1307 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1308 ch->ch_mostat |= (UART_MCR_RTS);
1309 neo_assert_modem_signals(ch);
1311 ch->ch_tun.un_flags |= (UN_EMPTY);
1314 * If DTR Toggle mode is on, turn on DTR now if not
1315 * already set, and make sure we get an event when the
1316 * data transfer has completed.
1318 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1319 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1320 ch->ch_mostat |= (UART_MCR_DTR);
1321 neo_assert_modem_signals(ch);
1323 ch->ch_tun.un_flags |= (UN_EMPTY);
1326 writeb(ch->ch_wqueue[ch->ch_w_tail],
1327 &ch->ch_neo_uart->txrx);
1329 ch->ch_w_tail &= WQUEUEMASK;
1336 /* We have to do it this way, because of the EXAR TXFIFO count bug. */
1338 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1339 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1344 n = readb(&ch->ch_neo_uart->tfifo);
1346 if ((unsigned int)n > ch->ch_t_tlevel)
1349 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1351 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1354 head = ch->ch_w_head & WQUEUEMASK;
1355 tail = ch->ch_w_tail & WQUEUEMASK;
1356 qlen = (head - tail) & WQUEUEMASK;
1361 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1368 * If RTS Toggle mode is on, turn on RTS now if not already set,
1369 * and make sure we get an event when the data transfer has
1372 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1373 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1374 ch->ch_mostat |= (UART_MCR_RTS);
1375 neo_assert_modem_signals(ch);
1377 ch->ch_tun.un_flags |= (UN_EMPTY);
1381 * If DTR Toggle mode is on, turn on DTR now if not already set,
1382 * and make sure we get an event when the data transfer has
1385 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1386 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1387 ch->ch_mostat |= (UART_MCR_DTR);
1388 neo_assert_modem_signals(ch);
1390 ch->ch_tun.un_flags |= (UN_EMPTY);
1393 memcpy_toio(&ch->ch_neo_uart->txrxburst,
1394 ch->ch_wqueue + tail, s);
1396 tail = (tail + s) & WQUEUEMASK;
1398 ch->ch_txcount += s;
1402 ch->ch_w_tail = tail & WQUEUEMASK;
1404 if (len_written > 0) {
1405 neo_pci_posting_flush(ch->ch_bd);
1406 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1410 spin_unlock_irqrestore(&ch->ch_lock, flags);
1413 static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
1415 unsigned char msignals = signals;
1421 * Do altpin switching. Altpin switches DCD and DSR.
1422 * This prolly breaks DSRPACE, so we should be more clever here.
1424 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1425 unsigned char mswap = msignals;
1427 if (mswap & UART_MSR_DDCD) {
1428 msignals &= ~UART_MSR_DDCD;
1429 msignals |= UART_MSR_DDSR;
1431 if (mswap & UART_MSR_DDSR) {
1432 msignals &= ~UART_MSR_DDSR;
1433 msignals |= UART_MSR_DDCD;
1435 if (mswap & UART_MSR_DCD) {
1436 msignals &= ~UART_MSR_DCD;
1437 msignals |= UART_MSR_DSR;
1439 if (mswap & UART_MSR_DSR) {
1440 msignals &= ~UART_MSR_DSR;
1441 msignals |= UART_MSR_DCD;
1445 /* Scrub off lower bits. They signify delta's */
1448 if (msignals & UART_MSR_DCD)
1449 ch->ch_mistat |= UART_MSR_DCD;
1451 ch->ch_mistat &= ~UART_MSR_DCD;
1453 if (msignals & UART_MSR_DSR)
1454 ch->ch_mistat |= UART_MSR_DSR;
1456 ch->ch_mistat &= ~UART_MSR_DSR;
1458 if (msignals & UART_MSR_RI)
1459 ch->ch_mistat |= UART_MSR_RI;
1461 ch->ch_mistat &= ~UART_MSR_RI;
1463 if (msignals & UART_MSR_CTS)
1464 ch->ch_mistat |= UART_MSR_CTS;
1466 ch->ch_mistat &= ~UART_MSR_CTS;
1469 /* Make the UART raise any of the output signals we want up */
1470 static void neo_assert_modem_signals(struct channel_t *ch)
1477 out = ch->ch_mostat;
1479 if (ch->ch_flags & CH_LOOPBACK)
1480 out |= UART_MCR_LOOP;
1482 writeb(out, &ch->ch_neo_uart->mcr);
1483 neo_pci_posting_flush(ch->ch_bd);
1485 /* Give time for the UART to actually raise/drop the signals */
1489 static void neo_send_start_character(struct channel_t *ch)
1494 if (ch->ch_startc != _POSIX_VDISABLE) {
1496 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1497 neo_pci_posting_flush(ch->ch_bd);
1502 static void neo_send_stop_character(struct channel_t *ch)
1507 if (ch->ch_stopc != _POSIX_VDISABLE) {
1508 ch->ch_xoff_sends++;
1509 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1510 neo_pci_posting_flush(ch->ch_bd);
1517 static void neo_uart_init(struct channel_t *ch)
1519 writeb(0, &ch->ch_neo_uart->ier);
1520 writeb(0, &ch->ch_neo_uart->efr);
1521 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1523 /* Clear out UART and FIFO */
1524 readb(&ch->ch_neo_uart->txrx);
1525 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1526 &ch->ch_neo_uart->isr_fcr);
1527 readb(&ch->ch_neo_uart->lsr);
1528 readb(&ch->ch_neo_uart->msr);
1530 ch->ch_flags |= CH_FIFO_ENABLED;
1532 /* Assert any signals we want up */
1533 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1534 neo_pci_posting_flush(ch->ch_bd);
1537 /* Make the UART completely turn off. */
1538 static void neo_uart_off(struct channel_t *ch)
1540 /* Turn off UART enhanced bits */
1541 writeb(0, &ch->ch_neo_uart->efr);
1543 /* Stop all interrupts from occurring. */
1544 writeb(0, &ch->ch_neo_uart->ier);
1545 neo_pci_posting_flush(ch->ch_bd);
1548 static uint neo_get_uart_bytes_left(struct channel_t *ch)
1550 unsigned char left = 0;
1551 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
1553 /* We must cache the LSR as some of the bits get reset once read... */
1554 ch->ch_cached_lsr |= lsr;
1556 /* Determine whether the Transmitter is empty or not */
1557 if (!(lsr & UART_LSR_TEMT)) {
1558 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1559 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1562 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1569 /* Channel lock MUST be held by the calling function! */
1570 static void neo_send_break(struct channel_t *ch, int msecs)
1572 /* If we receive a time of 0, this means turn off the break. */
1575 if (ch->ch_flags & CH_BREAK_SENDING) {
1576 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1578 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1579 neo_pci_posting_flush(ch->ch_bd);
1580 ch->ch_flags &= ~(CH_BREAK_SENDING);
1581 ch->ch_stop_sending_break = 0;
1587 * Set the time we should stop sending the break.
1588 * If we are already sending a break, toss away the existing
1589 * time to stop, and use this new value instead.
1591 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1593 /* Tell the UART to start sending the break */
1594 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1595 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1597 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1598 neo_pci_posting_flush(ch->ch_bd);
1599 ch->ch_flags |= (CH_BREAK_SENDING);
1604 * Sends a specific character as soon as possible to the UART,
1605 * jumping over any bytes that might be in the write queue.
1607 * The channel lock MUST be held by the calling function.
1609 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1614 writeb(c, &ch->ch_neo_uart->txrx);
1615 neo_pci_posting_flush(ch->ch_bd);
1618 static unsigned int neo_read_eeprom(unsigned char __iomem *base,
1619 unsigned int address)
1621 unsigned int enable;
1623 unsigned int databit;
1626 /* enable chip select */
1627 writeb(NEO_EECS, base + NEO_EEREG);
1629 enable = address | 0x180;
1631 for (bits = 9; bits--; ) {
1632 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1633 /* Set read address */
1634 writeb(databit | NEO_EECS, base + NEO_EEREG);
1635 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1640 for (bits = 17; bits--; ) {
1641 /* clock to EEPROM */
1642 writeb(NEO_EECS, base + NEO_EEREG);
1643 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1646 if (readb(base + NEO_EEREG) & NEO_EEDO)
1650 /* clock falling edge */
1651 writeb(NEO_EECS, base + NEO_EEREG);
1653 /* drop chip select */
1654 writeb(0x00, base + NEO_EEREG);
1659 static void neo_vpd(struct dgnc_board *brd)
1667 if (!brd->re_map_membase)
1670 /* Store the VPD into our buffer */
1671 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1672 a = neo_read_eeprom(brd->re_map_membase, i);
1673 brd->vpd[i * 2] = a & 0xff;
1674 brd->vpd[(i * 2) + 1] = (a >> 8) & 0xff;
1678 * brd->vpd has different name tags by below index.
1679 * 0x08 : long resource name tag
1680 * 0x10 : long resource name tage (PCI-66 files)
1681 * 0x7F : small resource end tag
1683 if (((brd->vpd[0x08] != 0x82) &&
1684 (brd->vpd[0x10] != 0x82)) ||
1685 (brd->vpd[0x7F] != 0x78)) {
1686 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1688 /* Search for the serial number */
1689 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1690 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
1691 strncpy(brd->serial_num, &brd->vpd[i + 3], 9);