2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
21 #include <linux/serial.h>
22 #include <linux/serial_reg.h>
23 #include <linux/pci.h>
25 #include "dgnc_driver.h"
29 static inline void cls_set_cts_flow_control(struct channel_t *ch)
31 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
32 unsigned char ier = readb(&ch->ch_cls_uart->ier);
33 unsigned char isr_fcr = 0;
36 * The Enhanced Register Set may only be accessed when
37 * the Line Control Register is set to 0xBFh.
39 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
41 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
43 /* Turn on CTS flow control, turn off IXON flow control */
44 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
45 isr_fcr &= ~(UART_EXAR654_EFR_IXON);
47 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
49 /* Write old LCR value back out, which turns enhanced access off */
50 writeb(lcrb, &ch->ch_cls_uart->lcr);
53 * Enable interrupts for CTS flow, turn off interrupts for
56 ier |= (UART_EXAR654_IER_CTSDSR);
57 ier &= ~(UART_EXAR654_IER_XOFF);
58 writeb(ier, &ch->ch_cls_uart->ier);
60 /* Set the usual FIFO values */
61 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
63 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
64 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
65 &ch->ch_cls_uart->isr_fcr);
70 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
72 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
73 unsigned char ier = readb(&ch->ch_cls_uart->ier);
74 unsigned char isr_fcr = 0;
77 * The Enhanced Register Set may only be accessed when
78 * the Line Control Register is set to 0xBFh.
80 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
82 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
84 /* Turn on IXON flow control, turn off CTS flow control */
85 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
86 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
88 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
90 /* Now set our current start/stop chars while in enhanced mode */
91 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
92 writeb(0, &ch->ch_cls_uart->lsr);
93 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
94 writeb(0, &ch->ch_cls_uart->spr);
96 /* Write old LCR value back out, which turns enhanced access off */
97 writeb(lcrb, &ch->ch_cls_uart->lcr);
100 * Disable interrupts for CTS flow, turn on interrupts for
101 * received XOFF chars
103 ier &= ~(UART_EXAR654_IER_CTSDSR);
104 ier |= (UART_EXAR654_IER_XOFF);
105 writeb(ier, &ch->ch_cls_uart->ier);
107 /* Set the usual FIFO values */
108 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
110 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
111 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
112 &ch->ch_cls_uart->isr_fcr);
115 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
117 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
118 unsigned char ier = readb(&ch->ch_cls_uart->ier);
119 unsigned char isr_fcr = 0;
122 * The Enhanced Register Set may only be accessed when
123 * the Line Control Register is set to 0xBFh.
125 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
127 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
129 /* Turn off IXON flow control, turn off CTS flow control */
130 isr_fcr |= (UART_EXAR654_EFR_ECB);
131 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
133 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
135 /* Write old LCR value back out, which turns enhanced access off */
136 writeb(lcrb, &ch->ch_cls_uart->lcr);
139 * Disable interrupts for CTS flow, turn off interrupts for
140 * received XOFF chars
142 ier &= ~(UART_EXAR654_IER_CTSDSR);
143 ier &= ~(UART_EXAR654_IER_XOFF);
144 writeb(ier, &ch->ch_cls_uart->ier);
146 /* Set the usual FIFO values */
147 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
149 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
150 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
151 &ch->ch_cls_uart->isr_fcr);
153 ch->ch_r_watermark = 0;
154 ch->ch_t_tlevel = 16;
155 ch->ch_r_tlevel = 16;
158 static inline void cls_set_rts_flow_control(struct channel_t *ch)
160 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
161 unsigned char ier = readb(&ch->ch_cls_uart->ier);
162 unsigned char isr_fcr = 0;
165 * The Enhanced Register Set may only be accessed when
166 * the Line Control Register is set to 0xBFh.
168 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
170 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
172 /* Turn on RTS flow control, turn off IXOFF flow control */
173 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
174 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
176 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
178 /* Write old LCR value back out, which turns enhanced access off */
179 writeb(lcrb, &ch->ch_cls_uart->lcr);
181 /* Enable interrupts for RTS flow */
182 ier |= (UART_EXAR654_IER_RTSDTR);
183 writeb(ier, &ch->ch_cls_uart->ier);
185 /* Set the usual FIFO values */
186 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
188 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
189 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
190 &ch->ch_cls_uart->isr_fcr);
192 ch->ch_r_watermark = 4;
196 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
198 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
199 unsigned char ier = readb(&ch->ch_cls_uart->ier);
200 unsigned char isr_fcr = 0;
203 * The Enhanced Register Set may only be accessed when
204 * the Line Control Register is set to 0xBFh.
206 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
208 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
210 /* Turn on IXOFF flow control, turn off RTS flow control */
211 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
212 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
214 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
216 /* Now set our current start/stop chars while in enhanced mode */
217 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
218 writeb(0, &ch->ch_cls_uart->lsr);
219 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
220 writeb(0, &ch->ch_cls_uart->spr);
222 /* Write old LCR value back out, which turns enhanced access off */
223 writeb(lcrb, &ch->ch_cls_uart->lcr);
225 /* Disable interrupts for RTS flow */
226 ier &= ~(UART_EXAR654_IER_RTSDTR);
227 writeb(ier, &ch->ch_cls_uart->ier);
229 /* Set the usual FIFO values */
230 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
232 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
233 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
234 &ch->ch_cls_uart->isr_fcr);
237 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
239 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
240 unsigned char ier = readb(&ch->ch_cls_uart->ier);
241 unsigned char isr_fcr = 0;
244 * The Enhanced Register Set may only be accessed when
245 * the Line Control Register is set to 0xBFh.
247 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
249 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
251 /* Turn off IXOFF flow control, turn off RTS flow control */
252 isr_fcr |= (UART_EXAR654_EFR_ECB);
253 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
255 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
257 /* Write old LCR value back out, which turns enhanced access off */
258 writeb(lcrb, &ch->ch_cls_uart->lcr);
260 /* Disable interrupts for RTS flow */
261 ier &= ~(UART_EXAR654_IER_RTSDTR);
262 writeb(ier, &ch->ch_cls_uart->ier);
264 /* Set the usual FIFO values */
265 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
267 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
268 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
269 &ch->ch_cls_uart->isr_fcr);
271 ch->ch_t_tlevel = 16;
272 ch->ch_r_tlevel = 16;
276 * Determines whether its time to shut off break condition.
278 * No locks are assumed to be held when calling this function.
279 * channel lock is held and released in this function.
281 static inline void cls_clear_break(struct channel_t *ch, int force)
288 spin_lock_irqsave(&ch->ch_lock, flags);
290 if (!ch->ch_stop_sending_break) {
291 spin_unlock_irqrestore(&ch->ch_lock, flags);
295 /* Turn break off, and unset some variables */
296 if (ch->ch_flags & CH_BREAK_SENDING) {
297 if (time_after(jiffies, ch->ch_stop_sending_break) || force) {
298 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
300 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
301 ch->ch_flags &= ~(CH_BREAK_SENDING);
302 ch->ch_stop_sending_break = 0;
305 spin_unlock_irqrestore(&ch->ch_lock, flags);
308 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
311 unsigned char linestatus = 0;
312 unsigned char error_mask = 0;
320 spin_lock_irqsave(&ch->ch_lock, flags);
322 head = ch->ch_r_head;
323 tail = ch->ch_r_tail;
325 qleft = tail - head - 1;
327 qleft += RQUEUEMASK + 1;
330 * Create a mask to determine whether we should
331 * insert the character (if any) into our queue.
333 if (ch->ch_c_iflag & IGNBRK)
334 error_mask |= UART_LSR_BI;
337 linestatus = readb(&ch->ch_cls_uart->lsr);
339 if (!(linestatus & (UART_LSR_DR)))
342 /* Discard character if we are ignoring the error mask. */
343 if (linestatus & error_mask) {
345 readb(&ch->ch_cls_uart->txrx);
350 * If our queue is full, we have no choice but to drop some
351 * data. The assumption is that HWFLOW or SWFLOW should have
352 * stopped things way way before we got to this point.
355 tail = (tail + 1) & RQUEUEMASK;
356 ch->ch_r_tail = tail;
357 ch->ch_err_overrun++;
361 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
363 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
367 if (ch->ch_equeue[head] & UART_LSR_PE)
369 if (ch->ch_equeue[head] & UART_LSR_BI)
371 if (ch->ch_equeue[head] & UART_LSR_FE)
374 head = (head + 1) & RQUEUEMASK;
378 ch->ch_r_head = head & RQUEUEMASK;
379 ch->ch_e_head = head & EQUEUEMASK;
381 spin_unlock_irqrestore(&ch->ch_lock, flags);
384 /* Make the UART raise any of the output signals we want up */
385 static void cls_assert_modem_signals(struct channel_t *ch)
394 if (ch->ch_flags & CH_LOOPBACK)
395 out |= UART_MCR_LOOP;
397 writeb(out, &ch->ch_cls_uart->mcr);
399 /* Give time for the UART to actually drop the signals */
403 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
409 uint len_written = 0;
415 spin_lock_irqsave(&ch->ch_lock, flags);
417 if (ch->ch_w_tail == ch->ch_w_head)
420 /* If port is "stopped", don't send any data to the UART */
421 if ((ch->ch_flags & CH_FORCED_STOP) ||
422 (ch->ch_flags & CH_BREAK_SENDING))
425 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
430 head = ch->ch_w_head & WQUEUEMASK;
431 tail = ch->ch_w_tail & WQUEUEMASK;
432 qlen = (head - tail) & WQUEUEMASK;
438 * If RTS Toggle mode is on, turn on RTS now if not already set,
439 * and make sure we get an event when the data transfer has
442 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
443 if (!(ch->ch_mostat & UART_MCR_RTS)) {
444 ch->ch_mostat |= (UART_MCR_RTS);
445 cls_assert_modem_signals(ch);
447 ch->ch_tun.un_flags |= (UN_EMPTY);
451 * If DTR Toggle mode is on, turn on DTR now if not already set,
452 * and make sure we get an event when the data transfer has
455 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
456 if (!(ch->ch_mostat & UART_MCR_DTR)) {
457 ch->ch_mostat |= (UART_MCR_DTR);
458 cls_assert_modem_signals(ch);
460 ch->ch_tun.un_flags |= (UN_EMPTY);
462 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
464 ch->ch_w_tail &= WQUEUEMASK;
471 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
474 spin_unlock_irqrestore(&ch->ch_lock, flags);
477 static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
479 unsigned char msignals = signals;
486 * Do altpin switching. Altpin switches DCD and DSR.
487 * This prolly breaks DSRPACE, so we should be more clever here.
489 spin_lock_irqsave(&ch->ch_lock, flags);
490 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
491 unsigned char mswap = signals;
493 if (mswap & UART_MSR_DDCD) {
494 msignals &= ~UART_MSR_DDCD;
495 msignals |= UART_MSR_DDSR;
497 if (mswap & UART_MSR_DDSR) {
498 msignals &= ~UART_MSR_DDSR;
499 msignals |= UART_MSR_DDCD;
501 if (mswap & UART_MSR_DCD) {
502 msignals &= ~UART_MSR_DCD;
503 msignals |= UART_MSR_DSR;
505 if (mswap & UART_MSR_DSR) {
506 msignals &= ~UART_MSR_DSR;
507 msignals |= UART_MSR_DCD;
510 spin_unlock_irqrestore(&ch->ch_lock, flags);
512 /* Scrub off lower bits. They signify delta's */
515 spin_lock_irqsave(&ch->ch_lock, flags);
516 if (msignals & UART_MSR_DCD)
517 ch->ch_mistat |= UART_MSR_DCD;
519 ch->ch_mistat &= ~UART_MSR_DCD;
521 if (msignals & UART_MSR_DSR)
522 ch->ch_mistat |= UART_MSR_DSR;
524 ch->ch_mistat &= ~UART_MSR_DSR;
526 if (msignals & UART_MSR_RI)
527 ch->ch_mistat |= UART_MSR_RI;
529 ch->ch_mistat &= ~UART_MSR_RI;
531 if (msignals & UART_MSR_CTS)
532 ch->ch_mistat |= UART_MSR_CTS;
534 ch->ch_mistat &= ~UART_MSR_CTS;
535 spin_unlock_irqrestore(&ch->ch_lock, flags);
538 /* Parse the ISR register for the specific port */
539 static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
541 struct channel_t *ch;
542 unsigned char isr = 0;
546 * No need to verify board pointer, it was already
547 * verified in the interrupt routine.
550 if (port >= brd->nasync)
553 ch = brd->channels[port];
555 /* Here we try to figure out what caused the interrupt to happen */
557 isr = readb(&ch->ch_cls_uart->isr_fcr);
559 if (isr & UART_IIR_NO_INT)
562 /* Receive Interrupt pending */
563 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
564 cls_copy_data_from_uart_to_queue(ch);
565 dgnc_check_queue_flow_control(ch);
568 /* Transmit Hold register empty pending */
569 if (isr & UART_IIR_THRI) {
570 spin_lock_irqsave(&ch->ch_lock, flags);
571 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
572 spin_unlock_irqrestore(&ch->ch_lock, flags);
573 cls_copy_data_from_queue_to_uart(ch);
576 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
580 /* Channel lock MUST be held before calling this function! */
581 static void cls_flush_uart_write(struct channel_t *ch)
586 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
587 &ch->ch_cls_uart->isr_fcr);
589 /* Must use *delay family functions in atomic context */
592 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
595 /* Channel lock MUST be held before calling this function! */
596 static void cls_flush_uart_read(struct channel_t *ch)
602 * For complete POSIX compatibility, we should be purging the
603 * read FIFO in the UART here.
605 * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
606 * incorrectly flushes write data as well as just basically trashing the
609 * Presumably, this is a bug in this UART.
615 /* Send any/all changes to the line to the UART. */
616 static void cls_param(struct tty_struct *tty)
618 unsigned char lcr = 0;
619 unsigned char uart_lcr = 0;
620 unsigned char ier = 0;
621 unsigned char uart_ier = 0;
624 struct dgnc_board *bd;
625 struct channel_t *ch;
631 un = (struct un_t *)tty->driver_data;
643 /* If baud rate is zero, flush queues, and set mval to drop DTR. */
644 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
652 cls_flush_uart_write(ch);
653 cls_flush_uart_read(ch);
655 /* The baudrate is B0 so all modem lines are to be dropped. */
656 ch->ch_flags |= (CH_BAUD0);
657 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
658 cls_assert_modem_signals(ch);
661 } else if (ch->ch_custom_speed) {
662 baud = ch->ch_custom_speed;
663 /* Handle transition from B0 */
664 if (ch->ch_flags & CH_BAUD0) {
665 ch->ch_flags &= ~(CH_BAUD0);
668 * Bring back up RTS and DTR...
669 * Also handle RTS or DTR toggle if set.
671 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
672 ch->ch_mostat |= (UART_MCR_RTS);
673 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
674 ch->ch_mostat |= (UART_MCR_DTR);
681 ulong bauds[4][16] = {
685 600, 1200, 1800, 2400,
686 4800, 9600, 19200, 38400 },
687 { /* slowbaud & CBAUDEX */
688 0, 57600, 115200, 230400,
689 460800, 150, 200, 921600,
690 600, 1200, 1800, 2400,
691 4800, 9600, 19200, 38400 },
693 0, 57600, 76800, 115200,
694 131657, 153600, 230400, 460800,
695 921600, 1200, 1800, 2400,
696 4800, 9600, 19200, 38400 },
697 { /* fastbaud & CBAUDEX */
698 0, 57600, 115200, 230400,
699 460800, 150, 200, 921600,
700 600, 1200, 1800, 2400,
701 4800, 9600, 19200, 38400 }
705 * Only use the TXPrint baud rate if the terminal
708 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
709 (un->un_type == DGNC_PRINT))
710 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
712 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
714 if (ch->ch_c_cflag & CBAUDEX)
717 if (ch->ch_digi.digi_flags & DIGI_FAST)
722 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) &&
724 baud = bauds[iindex][jindex];
732 /* Handle transition from B0 */
733 if (ch->ch_flags & CH_BAUD0) {
734 ch->ch_flags &= ~(CH_BAUD0);
737 * Bring back up RTS and DTR...
738 * Also handle RTS or DTR toggle if set.
740 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
741 ch->ch_mostat |= (UART_MCR_RTS);
742 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
743 ch->ch_mostat |= (UART_MCR_DTR);
747 if (ch->ch_c_cflag & PARENB)
748 lcr |= UART_LCR_PARITY;
750 if (!(ch->ch_c_cflag & PARODD))
751 lcr |= UART_LCR_EPAR;
754 if (ch->ch_c_cflag & CMSPAR)
755 lcr |= UART_LCR_SPAR;
758 if (ch->ch_c_cflag & CSTOPB)
759 lcr |= UART_LCR_STOP;
761 switch (ch->ch_c_cflag & CSIZE) {
763 lcr |= UART_LCR_WLEN5;
766 lcr |= UART_LCR_WLEN6;
769 lcr |= UART_LCR_WLEN7;
773 lcr |= UART_LCR_WLEN8;
777 uart_ier = readb(&ch->ch_cls_uart->ier);
779 uart_lcr = readb(&ch->ch_cls_uart->lcr);
784 quot = ch->ch_bd->bd_dividend / baud;
786 if (quot != 0 && ch->ch_old_baud != baud) {
787 ch->ch_old_baud = baud;
788 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
789 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
790 writeb((quot >> 8), &ch->ch_cls_uart->ier);
791 writeb(lcr, &ch->ch_cls_uart->lcr);
795 writeb(lcr, &ch->ch_cls_uart->lcr);
797 if (ch->ch_c_cflag & CREAD)
798 ier |= (UART_IER_RDI | UART_IER_RLSI);
800 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
803 * Have the UART interrupt on modem signal changes ONLY when
804 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
806 if ((ch->ch_digi.digi_flags & CTSPACE) ||
807 (ch->ch_digi.digi_flags & RTSPACE) ||
808 (ch->ch_c_cflag & CRTSCTS) ||
809 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
810 !(ch->ch_c_cflag & CLOCAL))
813 ier &= ~UART_IER_MSI;
815 ier |= UART_IER_THRI;
818 writeb(ier, &ch->ch_cls_uart->ier);
820 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
821 cls_set_cts_flow_control(ch);
822 } else if (ch->ch_c_iflag & IXON) {
823 if ((ch->ch_startc == _POSIX_VDISABLE) ||
824 (ch->ch_stopc == _POSIX_VDISABLE))
825 cls_set_no_output_flow_control(ch);
827 cls_set_ixon_flow_control(ch);
829 cls_set_no_output_flow_control(ch);
832 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
833 cls_set_rts_flow_control(ch);
834 } else if (ch->ch_c_iflag & IXOFF) {
835 if ((ch->ch_startc == _POSIX_VDISABLE) ||
836 (ch->ch_stopc == _POSIX_VDISABLE))
837 cls_set_no_input_flow_control(ch);
839 cls_set_ixoff_flow_control(ch);
841 cls_set_no_input_flow_control(ch);
844 cls_assert_modem_signals(ch);
846 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
849 /* Board poller function. */
850 static void cls_tasklet(unsigned long data)
852 struct dgnc_board *bd = (struct dgnc_board *)data;
853 struct channel_t *ch;
862 spin_lock_irqsave(&bd->bd_lock, flags);
865 spin_unlock_irqrestore(&bd->bd_lock, flags);
868 * Do NOT allow the interrupt routine to read the intr registers
869 * Until we release this lock.
871 spin_lock_irqsave(&bd->bd_intr_lock, flags);
873 if ((state == BOARD_READY) && (ports > 0)) {
874 for (i = 0; i < ports; i++) {
875 ch = bd->channels[i];
878 * NOTE: Remember you CANNOT hold any channel
879 * locks when calling input.
880 * During input processing, its possible we
881 * will call ld, which might do callbacks back
887 * Channel lock is grabbed and then released
888 * inside this routine.
890 cls_copy_data_from_queue_to_uart(ch);
891 dgnc_wakeup_writes(ch);
896 * The timing check of turning off the break is done
897 * inside clear_break()
899 if (ch->ch_stop_sending_break)
900 cls_clear_break(ch, 0);
904 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
907 /* Classic specific interrupt handler. */
908 static irqreturn_t cls_intr(int irq, void *voidbrd)
910 struct dgnc_board *brd = voidbrd;
912 unsigned char poll_reg;
918 spin_lock_irqsave(&brd->bd_intr_lock, flags);
920 poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
922 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
926 for (i = 0; i < brd->nasync; i++)
927 cls_parse_isr(brd, i);
929 tasklet_schedule(&brd->helper_tasklet);
931 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
936 static void cls_disable_receiver(struct channel_t *ch)
938 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
940 tmp &= ~(UART_IER_RDI);
941 writeb(tmp, &ch->ch_cls_uart->ier);
944 static void cls_enable_receiver(struct channel_t *ch)
946 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
948 tmp |= (UART_IER_RDI);
949 writeb(tmp, &ch->ch_cls_uart->ier);
953 * This function basically goes to sleep for seconds, or until
954 * it gets signalled that the port has fully drained.
956 static int cls_drain(struct tty_struct *tty, uint seconds)
959 struct channel_t *ch;
965 un = (struct un_t *)tty->driver_data;
973 spin_lock_irqsave(&ch->ch_lock, flags);
974 un->un_flags |= UN_EMPTY;
975 spin_unlock_irqrestore(&ch->ch_lock, flags);
977 /* NOTE: Do something with time passed in. */
979 /* If ret is non-zero, user ctrl-c'ed us */
981 return wait_event_interruptible(un->un_flags_wait,
982 ((un->un_flags & UN_EMPTY) == 0));
985 static void cls_send_start_character(struct channel_t *ch)
990 if (ch->ch_startc != _POSIX_VDISABLE) {
992 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
996 static void cls_send_stop_character(struct channel_t *ch)
1001 if (ch->ch_stopc != _POSIX_VDISABLE) {
1002 ch->ch_xoff_sends++;
1003 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
1007 static void cls_uart_init(struct channel_t *ch)
1009 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
1010 unsigned char isr_fcr = 0;
1012 writeb(0, &ch->ch_cls_uart->ier);
1015 * The Enhanced Register Set may only be accessed when
1016 * the Line Control Register is set to 0xBFh.
1018 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1020 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1022 /* Turn on Enhanced/Extended controls */
1023 isr_fcr |= (UART_EXAR654_EFR_ECB);
1025 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1027 /* Write old LCR value back out, which turns enhanced access off */
1028 writeb(lcrb, &ch->ch_cls_uart->lcr);
1030 /* Clear out UART and FIFO */
1031 readb(&ch->ch_cls_uart->txrx);
1033 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1034 &ch->ch_cls_uart->isr_fcr);
1035 usleep_range(10, 20);
1037 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1039 readb(&ch->ch_cls_uart->lsr);
1040 readb(&ch->ch_cls_uart->msr);
1043 static void cls_uart_off(struct channel_t *ch)
1045 writeb(0, &ch->ch_cls_uart->ier);
1049 * The channel lock MUST be held by the calling function.
1050 * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1052 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1054 unsigned char left = 0;
1055 unsigned char lsr = 0;
1060 lsr = readb(&ch->ch_cls_uart->lsr);
1062 /* Determine whether the Transmitter is empty or not */
1063 if (!(lsr & UART_LSR_TEMT)) {
1064 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1065 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1068 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1076 * Starts sending a break thru the UART.
1077 * The channel lock MUST be held by the calling function.
1079 static void cls_send_break(struct channel_t *ch, int msecs)
1084 /* If we receive a time of 0, this means turn off the break. */
1086 if (ch->ch_flags & CH_BREAK_SENDING) {
1087 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1089 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1090 ch->ch_flags &= ~(CH_BREAK_SENDING);
1091 ch->ch_stop_sending_break = 0;
1097 * Set the time we should stop sending the break.
1098 * If we are already sending a break, toss away the existing
1099 * time to stop, and use this new value instead.
1101 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1103 /* Tell the UART to start sending the break */
1104 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1105 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1107 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1108 ch->ch_flags |= (CH_BREAK_SENDING);
1113 * Sends a specific character as soon as possible to the UART,
1114 * jumping over any bytes that might be in the write queue.
1116 * The channel lock MUST be held by the calling function.
1118 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1123 writeb(c, &ch->ch_cls_uart->txrx);
1126 static void cls_vpd(struct dgnc_board *brd)
1128 ulong vpdbase; /* Start of io base of the card */
1129 u8 __iomem *re_map_vpdbase;/* Remapped memory of the card */
1132 vpdbase = pci_resource_start(brd->pdev, 3);
1136 re_map_vpdbase = ioremap(vpdbase, 0x400);
1138 if (!re_map_vpdbase)
1141 for (i = 0; i < 0x40; i++) {
1142 brd->vpd[i] = readb(re_map_vpdbase + i);
1143 pr_info("%x ", brd->vpd[i]);
1147 iounmap(re_map_vpdbase);
1150 struct board_ops dgnc_cls_ops = {
1151 .tasklet = cls_tasklet,
1153 .uart_init = cls_uart_init,
1154 .uart_off = cls_uart_off,
1158 .assert_modem_signals = cls_assert_modem_signals,
1159 .flush_uart_write = cls_flush_uart_write,
1160 .flush_uart_read = cls_flush_uart_read,
1161 .disable_receiver = cls_disable_receiver,
1162 .enable_receiver = cls_enable_receiver,
1163 .send_break = cls_send_break,
1164 .send_start_character = cls_send_start_character,
1165 .send_stop_character = cls_send_stop_character,
1166 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
1167 .get_uart_bytes_left = cls_get_uart_bytes_left,
1168 .send_immediate_char = cls_send_immediate_char