1 == MediaTek MT7622 pinctrl controller ==
3 Required properties for the root node:
4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 - reg: offset and length of the pinctrl space
8 - gpio-controller: Marks the device node as a GPIO controller.
9 - #gpio-cells: Should be two. The first cell is the pin number and the
10 second is the GPIO flags.
13 - interrupt-controller : Marks the device node as an interrupt controller
15 If the property interrupt-controller is defined, following property is required
16 - reg-names: A string describing the "reg" entries. Must contain "eint".
17 - interrupts : The interrupt output from the controller.
18 - #interrupt-cells: Should be two.
20 Please refer to pinctrl-bindings.txt in this directory for details of the
21 common pinctrl bindings used by client devices, including the meaning of the
22 phrase "pin configuration node".
24 MT7622 pin configuration nodes act as a container for an arbitrary number of
25 subnodes. Each of these subnodes represents some desired configuration for a
26 pin, a group, or a list of pins or groups. This configuration can include the
27 mux function to select on those pin(s)/group(s), and various pin configuration
28 parameters, such as pull-up, slew rate, etc.
30 We support 2 types of configuration nodes. Those nodes can be either pinmux
31 nodes or pinconf nodes. Each configuration node can consist of multiple nodes
32 describing the pinmux and pinconf options.
34 The name of each subnode doesn't matter as long as it is unique; all subnodes
35 should be enumerated and processed purely based on their content.
37 == pinmux nodes content ==
39 The following generic properties as defined in pinctrl-bindings.txt are valid
40 to specify in a pinmux subnode:
42 Required properties are:
43 - groups: An array of strings. Each string contains the name of a group.
44 Valid values for these names are listed below.
45 - function: A string containing the name of the function to mux to the
46 group. Valid values for function names are listed below.
48 == pinconf nodes content ==
50 The following generic properties as defined in pinctrl-bindings.txt are valid
51 to specify in a pinconf subnode:
53 Required properties are:
54 - pins: An array of strings. Each string contains the name of a pin.
55 Valid values for these names are listed below.
56 - groups: An array of strings. Each string contains the name of a group.
57 Valid values for these names are listed below.
59 Optional properies are:
60 bias-disable, bias-pull, bias-pull-down, input-enable,
61 input-schmitt-enable, input-schmitt-disable, output-enable
62 output-low, output-high, drive-strength, slew-rate
64 Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
65 slower slew rate respectively.
66 Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
68 The following specific properties as defined are valid to specify in a pinconf
71 Optional properties are:
72 - mediatek,tdsel: An integer describing the steps for output level shifter duty
73 cycle when asserted (high pulse width adjustment). Valid arguments are from 0
75 - mediatek,rdsel: An integer describing the steps for input level shifter duty
76 cycle when asserted (high pulse width adjustment). Valid arguments are from 0
79 == Valid values for pins, function and groups on MT7622 ==
81 Valid values for pins are:
82 pins can be referenced via the pin names as the below table shown and the
83 related physical number is also put ahead of those names which helps cross
84 references to pins between groups to know whether pins assignment conflict
85 happens among devices try to acquire those available pins.
87 Pin #: Valid values for pins
88 -----------------------------
175 PIN 86: "EPHY_LED0_N"
193 Valid values for function are:
194 "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie",
195 "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
197 Valid values for groups are:
198 additional data is put followingly with valid value allowing us to know which
199 applicable function and which relevant pins (in pin#) are able applied for that
202 Valid value function pins (in pin#)
203 -------------------------------------------------------------------------
204 "emmc" "emmc" 40, 41, 42, 43, 44, 45,
207 "esw" "eth" 51, 52, 53, 54, 55, 56,
208 57, 58, 59, 60, 61, 62,
209 63, 64, 65, 66, 67, 68,
211 "esw_p0_p1" "eth" 51, 52, 53, 54, 55, 56,
213 "esw_p2_p3_p4" "eth" 59, 60, 61, 62, 63, 64,
214 65, 66, 67, 68, 69, 70
215 "rgmii_via_esw" "eth" 59, 60, 61, 62, 63, 64,
216 65, 66, 67, 68, 69, 70
217 "rgmii_via_gmac1" "eth" 59, 60, 61, 62, 63, 64,
218 65, 66, 67, 68, 69, 70
219 "rgmii_via_gmac2" "eth" 25, 26, 27, 28, 29, 30,
220 31, 32, 33, 34, 35, 36
221 "mdc_mdio" "eth" 23, 24
223 "i2c1_0" "i2c" 55, 56
224 "i2c1_1" "i2c" 73, 74
225 "i2c1_2" "i2c" 87, 88
226 "i2c2_0" "i2c" 57, 58
227 "i2c2_1" "i2c" 75, 76
228 "i2c2_2" "i2c" 89, 90
229 "i2s_in_mclk_bclk_ws" "i2s" 3, 4, 5
230 "i2s1_in_data" "i2s" 1
231 "i2s2_in_data" "i2s" 16
232 "i2s3_in_data" "i2s" 17
233 "i2s4_in_data" "i2s" 18
234 "i2s_out_mclk_bclk_ws" "i2s" 3, 4, 5
235 "i2s1_out_data" "i2s" 2
236 "i2s2_out_data" "i2s" 19
237 "i2s3_out_data" "i2s" 20
238 "i2s4_out_data" "i2s" 21
245 "ephy_leds" "led" 86, 91, 92, 93, 94
252 "par_nand" "flash" 37, 38, 39, 40, 41, 42,
253 43, 44, 45, 46, 47, 48,
255 "snfi" "flash" 8, 9, 10, 11, 12, 13
256 "spi_nor" "flash" 8, 9, 10, 11, 12, 13
257 "pcie0_0_waken" "pcie" 14
258 "pcie0_1_waken" "pcie" 79
259 "pcie1_0_waken" "pcie" 14
260 "pcie0_0_clkreq" "pcie" 15
261 "pcie0_1_clkreq" "pcie" 80
262 "pcie1_0_clkreq" "pcie" 15
263 "pcie0_pad_perst" "pcie" 83
264 "pcie1_pad_perst" "pcie" 84
265 "pmic_bus" "pmic" 71, 72
285 "pwm_ch6_3" "pwm" 100
288 "pwm_ch7_2" "pwm" 101
289 "sd_0" "sd" 16, 17, 18, 19, 20, 21
290 "sd_1" "sd" 25, 26, 27, 28, 29, 30
291 "spic0_0" "spi" 63, 64, 65, 66
292 "spic0_1" "spi" 79, 80, 81, 82
293 "spic1_0" "spi" 67, 68, 69, 70
294 "spic1_1" "spi" 73, 74, 75, 76
295 "spic2_0_wp_hold" "spi" 8, 9
296 "spic2_0" "spi" 10, 11, 12, 13
297 "tdm_0_out_mclk_bclk_ws" "tdm" 8, 9, 10
298 "tdm_0_in_mclk_bclk_ws" "tdm" 11, 12, 13
299 "tdm_0_out_data" "tdm" 20
300 "tdm_0_in_data" "tdm" 21
301 "tdm_1_out_mclk_bclk_ws" "tdm" 57, 58, 59
302 "tdm_1_in_mclk_bclk_ws" "tdm" 60, 61, 62
303 "tdm_1_out_data" "tdm" 55
304 "tdm_1_in_data" "tdm" 56
305 "uart0_0_tx_rx" "uart" 6, 7
306 "uart1_0_tx_rx" "uart" 55, 56
307 "uart1_0_rts_cts" "uart" 57, 58
308 "uart1_1_tx_rx" "uart" 73, 74
309 "uart1_1_rts_cts" "uart" 75, 76
310 "uart2_0_tx_rx" "uart" 3, 4
311 "uart2_0_rts_cts" "uart" 1, 2
312 "uart2_1_tx_rx" "uart" 51, 52
313 "uart2_1_rts_cts" "uart" 53, 54
314 "uart2_2_tx_rx" "uart" 59, 60
315 "uart2_2_rts_cts" "uart" 61, 62
316 "uart2_3_tx_rx" "uart" 95, 96
317 "uart3_0_tx_rx" "uart" 57, 58
318 "uart3_1_tx_rx" "uart" 81, 82
319 "uart3_1_rts_cts" "uart" 79, 80
320 "uart4_0_tx_rx" "uart" 61, 62
321 "uart4_1_tx_rx" "uart" 91, 92
322 "uart4_1_rts_cts" "uart" 93, 94
323 "uart4_2_tx_rx" "uart" 97, 98
324 "uart4_2_rts_cts" "uart" 95, 96
325 "watchdog" "watchdog" 78
329 pio: pinctrl@10211000 {
330 compatible = "mediatek,mt7622-pinctrl";
331 reg = <0 0x10211000 0 0x1000>;
335 pinctrl_eth_default: eth-default {
339 drive-strength = <12>;
345 drive-strength = <12>;
351 drive-strength = <8>;