2 * DA8XX/OMAP L1XX platform device data
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/platform_data/syscon.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-contiguous.h>
17 #include <linux/serial_8250.h>
18 #include <linux/ahci_platform.h>
19 #include <linux/clk.h>
20 #include <linux/reboot.h>
21 #include <linux/dmaengine.h>
23 #include <mach/cputype.h>
24 #include <mach/common.h>
25 #include <mach/time.h>
26 #include <mach/da8xx.h>
27 #include <mach/clock.h>
34 #define DA8XX_TPCC_BASE 0x01c00000
35 #define DA8XX_TPTC0_BASE 0x01c08000
36 #define DA8XX_TPTC1_BASE 0x01c08400
37 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
38 #define DA8XX_I2C0_BASE 0x01c22000
39 #define DA8XX_RTC_BASE 0x01c23000
40 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
41 #define DA8XX_MMCSD0_BASE 0x01c40000
42 #define DA8XX_SPI0_BASE 0x01c41000
43 #define DA830_SPI1_BASE 0x01e12000
44 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
45 #define DA850_SATA_BASE 0x01e18000
46 #define DA850_MMCSD1_BASE 0x01e1b000
47 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
48 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
49 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
50 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
51 #define DA8XX_I2C1_BASE 0x01e28000
52 #define DA850_TPCC1_BASE 0x01e30000
53 #define DA850_TPTC2_BASE 0x01e38000
54 #define DA850_SPI1_BASE 0x01f0e000
55 #define DA8XX_DDR2_CTL_BASE 0xb0000000
57 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
58 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
59 #define DA8XX_EMAC_RAM_OFFSET 0x0000
60 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
62 void __iomem *da8xx_syscfg0_base;
63 void __iomem *da8xx_syscfg1_base;
65 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
67 .mapbase = DA8XX_UART0_BASE,
68 .irq = IRQ_DA8XX_UARTINT0,
69 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
78 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
80 .mapbase = DA8XX_UART1_BASE,
81 .irq = IRQ_DA8XX_UARTINT1,
82 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
91 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
93 .mapbase = DA8XX_UART2_BASE,
94 .irq = IRQ_DA8XX_UARTINT2,
95 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
105 struct platform_device da8xx_serial_device[] = {
107 .name = "serial8250",
108 .id = PLAT8250_DEV_PLATFORM,
110 .platform_data = da8xx_serial0_pdata,
114 .name = "serial8250",
115 .id = PLAT8250_DEV_PLATFORM1,
117 .platform_data = da8xx_serial1_pdata,
121 .name = "serial8250",
122 .id = PLAT8250_DEV_PLATFORM2,
124 .platform_data = da8xx_serial2_pdata,
131 static s8 da8xx_queue_priority_mapping[][2] = {
132 /* {event queue no, Priority} */
138 static s8 da850_queue_priority_mapping[][2] = {
139 /* {event queue no, Priority} */
144 static struct edma_soc_info da8xx_edma0_pdata = {
145 .queue_priority_mapping = da8xx_queue_priority_mapping,
146 .default_queue = EVENTQ_1,
149 static struct edma_soc_info da850_edma1_pdata = {
150 .queue_priority_mapping = da850_queue_priority_mapping,
151 .default_queue = EVENTQ_0,
154 static struct resource da8xx_edma0_resources[] = {
157 .start = DA8XX_TPCC_BASE,
158 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
159 .flags = IORESOURCE_MEM,
163 .start = DA8XX_TPTC0_BASE,
164 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
165 .flags = IORESOURCE_MEM,
169 .start = DA8XX_TPTC1_BASE,
170 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
171 .flags = IORESOURCE_MEM,
174 .name = "edma3_ccint",
175 .start = IRQ_DA8XX_CCINT0,
176 .flags = IORESOURCE_IRQ,
179 .name = "edma3_ccerrint",
180 .start = IRQ_DA8XX_CCERRINT,
181 .flags = IORESOURCE_IRQ,
185 static struct resource da850_edma1_resources[] = {
188 .start = DA850_TPCC1_BASE,
189 .end = DA850_TPCC1_BASE + SZ_32K - 1,
190 .flags = IORESOURCE_MEM,
194 .start = DA850_TPTC2_BASE,
195 .end = DA850_TPTC2_BASE + SZ_1K - 1,
196 .flags = IORESOURCE_MEM,
199 .name = "edma3_ccint",
200 .start = IRQ_DA850_CCINT1,
201 .flags = IORESOURCE_IRQ,
204 .name = "edma3_ccerrint",
205 .start = IRQ_DA850_CCERRINT1,
206 .flags = IORESOURCE_IRQ,
210 static const struct platform_device_info da8xx_edma0_device __initconst = {
213 .dma_mask = DMA_BIT_MASK(32),
214 .res = da8xx_edma0_resources,
215 .num_res = ARRAY_SIZE(da8xx_edma0_resources),
216 .data = &da8xx_edma0_pdata,
217 .size_data = sizeof(da8xx_edma0_pdata),
220 static const struct platform_device_info da850_edma1_device __initconst = {
223 .dma_mask = DMA_BIT_MASK(32),
224 .res = da850_edma1_resources,
225 .num_res = ARRAY_SIZE(da850_edma1_resources),
226 .data = &da850_edma1_pdata,
227 .size_data = sizeof(da850_edma1_pdata),
230 static const struct dma_slave_map da830_edma_map[] = {
231 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
232 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
233 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
234 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
235 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
236 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
237 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
238 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
239 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
240 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
241 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
242 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
245 int __init da830_register_edma(struct edma_rsv_info *rsv)
247 struct platform_device *edma_pdev;
249 da8xx_edma0_pdata.rsv = rsv;
251 da8xx_edma0_pdata.slave_map = da830_edma_map;
252 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
254 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
255 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
258 static const struct dma_slave_map da850_edma0_map[] = {
259 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
260 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
261 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
262 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
263 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
264 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
265 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
266 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
267 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
268 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
269 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
270 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
273 static const struct dma_slave_map da850_edma1_map[] = {
274 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
275 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
278 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
280 struct platform_device *edma_pdev;
283 da8xx_edma0_pdata.rsv = rsv[0];
284 da850_edma1_pdata.rsv = rsv[1];
287 da8xx_edma0_pdata.slave_map = da850_edma0_map;
288 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
290 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
291 if (IS_ERR(edma_pdev)) {
292 pr_warn("%s: Failed to register eDMA0\n", __func__);
293 return PTR_ERR(edma_pdev);
296 da850_edma1_pdata.slave_map = da850_edma1_map;
297 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
299 edma_pdev = platform_device_register_full(&da850_edma1_device);
300 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
303 static struct resource da8xx_i2c_resources0[] = {
305 .start = DA8XX_I2C0_BASE,
306 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
307 .flags = IORESOURCE_MEM,
310 .start = IRQ_DA8XX_I2CINT0,
311 .end = IRQ_DA8XX_I2CINT0,
312 .flags = IORESOURCE_IRQ,
316 static struct platform_device da8xx_i2c_device0 = {
317 .name = "i2c_davinci",
319 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
320 .resource = da8xx_i2c_resources0,
323 static struct resource da8xx_i2c_resources1[] = {
325 .start = DA8XX_I2C1_BASE,
326 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
327 .flags = IORESOURCE_MEM,
330 .start = IRQ_DA8XX_I2CINT1,
331 .end = IRQ_DA8XX_I2CINT1,
332 .flags = IORESOURCE_IRQ,
336 static struct platform_device da8xx_i2c_device1 = {
337 .name = "i2c_davinci",
339 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
340 .resource = da8xx_i2c_resources1,
343 int __init da8xx_register_i2c(int instance,
344 struct davinci_i2c_platform_data *pdata)
346 struct platform_device *pdev;
349 pdev = &da8xx_i2c_device0;
350 else if (instance == 1)
351 pdev = &da8xx_i2c_device1;
355 pdev->dev.platform_data = pdata;
356 return platform_device_register(pdev);
359 static struct resource da8xx_watchdog_resources[] = {
361 .start = DA8XX_WDOG_BASE,
362 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
363 .flags = IORESOURCE_MEM,
367 static struct platform_device da8xx_wdt_device = {
368 .name = "davinci-wdt",
370 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
371 .resource = da8xx_watchdog_resources,
374 void da8xx_restart(enum reboot_mode mode, const char *cmd)
378 dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
380 pr_err("%s: failed to find watchdog device\n", __func__);
384 davinci_watchdog_reset(to_platform_device(dev));
387 int __init da8xx_register_watchdog(void)
389 return platform_device_register(&da8xx_wdt_device);
392 static struct resource da8xx_emac_resources[] = {
394 .start = DA8XX_EMAC_CPPI_PORT_BASE,
395 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
396 .flags = IORESOURCE_MEM,
399 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
400 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
401 .flags = IORESOURCE_IRQ,
404 .start = IRQ_DA8XX_C0_RX_PULSE,
405 .end = IRQ_DA8XX_C0_RX_PULSE,
406 .flags = IORESOURCE_IRQ,
409 .start = IRQ_DA8XX_C0_TX_PULSE,
410 .end = IRQ_DA8XX_C0_TX_PULSE,
411 .flags = IORESOURCE_IRQ,
414 .start = IRQ_DA8XX_C0_MISC_PULSE,
415 .end = IRQ_DA8XX_C0_MISC_PULSE,
416 .flags = IORESOURCE_IRQ,
420 struct emac_platform_data da8xx_emac_pdata = {
421 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
422 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
423 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
424 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
425 .version = EMAC_VERSION_2,
428 static struct platform_device da8xx_emac_device = {
429 .name = "davinci_emac",
432 .platform_data = &da8xx_emac_pdata,
434 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
435 .resource = da8xx_emac_resources,
438 static struct resource da8xx_mdio_resources[] = {
440 .start = DA8XX_EMAC_MDIO_BASE,
441 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
442 .flags = IORESOURCE_MEM,
446 static struct platform_device da8xx_mdio_device = {
447 .name = "davinci_mdio",
449 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
450 .resource = da8xx_mdio_resources,
453 int __init da8xx_register_emac(void)
457 ret = platform_device_register(&da8xx_mdio_device);
461 return platform_device_register(&da8xx_emac_device);
464 static struct resource da830_mcasp1_resources[] = {
467 .start = DAVINCI_DA830_MCASP1_REG_BASE,
468 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
469 .flags = IORESOURCE_MEM,
474 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
475 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
476 .flags = IORESOURCE_DMA,
481 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
482 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
483 .flags = IORESOURCE_DMA,
487 .start = IRQ_DA8XX_MCASPINT,
488 .flags = IORESOURCE_IRQ,
492 static struct platform_device da830_mcasp1_device = {
493 .name = "davinci-mcasp",
495 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
496 .resource = da830_mcasp1_resources,
499 static struct resource da830_mcasp2_resources[] = {
502 .start = DAVINCI_DA830_MCASP2_REG_BASE,
503 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
504 .flags = IORESOURCE_MEM,
509 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
510 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
511 .flags = IORESOURCE_DMA,
516 .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
517 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
518 .flags = IORESOURCE_DMA,
522 .start = IRQ_DA8XX_MCASPINT,
523 .flags = IORESOURCE_IRQ,
527 static struct platform_device da830_mcasp2_device = {
528 .name = "davinci-mcasp",
530 .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
531 .resource = da830_mcasp2_resources,
534 static struct resource da850_mcasp_resources[] = {
537 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
538 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
539 .flags = IORESOURCE_MEM,
544 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
545 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
546 .flags = IORESOURCE_DMA,
551 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
552 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
553 .flags = IORESOURCE_DMA,
557 .start = IRQ_DA8XX_MCASPINT,
558 .flags = IORESOURCE_IRQ,
562 static struct platform_device da850_mcasp_device = {
563 .name = "davinci-mcasp",
565 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
566 .resource = da850_mcasp_resources,
569 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
571 struct platform_device *pdev;
575 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
576 pdev = &da850_mcasp_device;
579 /* Valid for DA830/OMAP-L137 only */
580 if (!cpu_is_davinci_da830())
582 pdev = &da830_mcasp1_device;
585 /* Valid for DA830/OMAP-L137 only */
586 if (!cpu_is_davinci_da830())
588 pdev = &da830_mcasp2_device;
594 pdev->dev.platform_data = pdata;
595 platform_device_register(pdev);
598 static struct resource da8xx_pruss_resources[] = {
600 .start = DA8XX_PRUSS_MEM_BASE,
601 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
602 .flags = IORESOURCE_MEM,
605 .start = IRQ_DA8XX_EVTOUT0,
606 .end = IRQ_DA8XX_EVTOUT0,
607 .flags = IORESOURCE_IRQ,
610 .start = IRQ_DA8XX_EVTOUT1,
611 .end = IRQ_DA8XX_EVTOUT1,
612 .flags = IORESOURCE_IRQ,
615 .start = IRQ_DA8XX_EVTOUT2,
616 .end = IRQ_DA8XX_EVTOUT2,
617 .flags = IORESOURCE_IRQ,
620 .start = IRQ_DA8XX_EVTOUT3,
621 .end = IRQ_DA8XX_EVTOUT3,
622 .flags = IORESOURCE_IRQ,
625 .start = IRQ_DA8XX_EVTOUT4,
626 .end = IRQ_DA8XX_EVTOUT4,
627 .flags = IORESOURCE_IRQ,
630 .start = IRQ_DA8XX_EVTOUT5,
631 .end = IRQ_DA8XX_EVTOUT5,
632 .flags = IORESOURCE_IRQ,
635 .start = IRQ_DA8XX_EVTOUT6,
636 .end = IRQ_DA8XX_EVTOUT6,
637 .flags = IORESOURCE_IRQ,
640 .start = IRQ_DA8XX_EVTOUT7,
641 .end = IRQ_DA8XX_EVTOUT7,
642 .flags = IORESOURCE_IRQ,
646 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
647 .pintc_base = 0x4000,
650 static struct platform_device da8xx_uio_pruss_dev = {
653 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
654 .resource = da8xx_pruss_resources,
656 .coherent_dma_mask = DMA_BIT_MASK(32),
657 .platform_data = &da8xx_uio_pruss_pdata,
661 int __init da8xx_register_uio_pruss(void)
663 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
664 return platform_device_register(&da8xx_uio_pruss_dev);
667 static struct lcd_ctrl_config lcd_cfg = {
668 .panel_shade = COLOR_ACTIVE,
672 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
673 .manu_name = "sharp",
674 .controller_data = &lcd_cfg,
675 .type = "Sharp_LCD035Q3DG01",
678 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
679 .manu_name = "sharp",
680 .controller_data = &lcd_cfg,
681 .type = "Sharp_LK043T1DG01",
684 static struct resource da8xx_lcdc_resources[] = {
685 [0] = { /* registers */
686 .start = DA8XX_LCD_CNTRL_BASE,
687 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
688 .flags = IORESOURCE_MEM,
690 [1] = { /* interrupt */
691 .start = IRQ_DA8XX_LCDINT,
692 .end = IRQ_DA8XX_LCDINT,
693 .flags = IORESOURCE_IRQ,
697 static struct platform_device da8xx_lcdc_device = {
698 .name = "da8xx_lcdc",
700 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
701 .resource = da8xx_lcdc_resources,
703 .coherent_dma_mask = DMA_BIT_MASK(32),
707 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
709 da8xx_lcdc_device.dev.platform_data = pdata;
710 return platform_device_register(&da8xx_lcdc_device);
713 static struct resource da8xx_gpio_resources[] = {
715 .start = DA8XX_GPIO_BASE,
716 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
717 .flags = IORESOURCE_MEM,
720 .start = IRQ_DA8XX_GPIO0,
721 .end = IRQ_DA8XX_GPIO8,
722 .flags = IORESOURCE_IRQ,
726 static struct platform_device da8xx_gpio_device = {
727 .name = "davinci_gpio",
729 .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
730 .resource = da8xx_gpio_resources,
733 int __init da8xx_register_gpio(void *pdata)
735 da8xx_gpio_device.dev.platform_data = pdata;
736 return platform_device_register(&da8xx_gpio_device);
739 static struct resource da8xx_mmcsd0_resources[] = {
741 .start = DA8XX_MMCSD0_BASE,
742 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
743 .flags = IORESOURCE_MEM,
746 .start = IRQ_DA8XX_MMCSDINT0,
747 .end = IRQ_DA8XX_MMCSDINT0,
748 .flags = IORESOURCE_IRQ,
752 static struct platform_device da8xx_mmcsd0_device = {
755 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
756 .resource = da8xx_mmcsd0_resources,
759 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
761 da8xx_mmcsd0_device.dev.platform_data = config;
762 return platform_device_register(&da8xx_mmcsd0_device);
765 #ifdef CONFIG_ARCH_DAVINCI_DA850
766 static struct resource da850_mmcsd1_resources[] = {
768 .start = DA850_MMCSD1_BASE,
769 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
770 .flags = IORESOURCE_MEM,
773 .start = IRQ_DA850_MMCSDINT0_1,
774 .end = IRQ_DA850_MMCSDINT0_1,
775 .flags = IORESOURCE_IRQ,
779 static struct platform_device da850_mmcsd1_device = {
782 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
783 .resource = da850_mmcsd1_resources,
786 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
788 da850_mmcsd1_device.dev.platform_data = config;
789 return platform_device_register(&da850_mmcsd1_device);
793 static struct resource da8xx_rproc_resources[] = {
794 { /* DSP boot address */
796 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
797 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
798 .flags = IORESOURCE_MEM,
800 { /* DSP interrupt registers */
802 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
803 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
804 .flags = IORESOURCE_MEM,
808 .start = DA8XX_DSP_L2_RAM_BASE,
809 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
810 .flags = IORESOURCE_MEM,
814 .start = DA8XX_DSP_L1P_RAM_BASE,
815 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
816 .flags = IORESOURCE_MEM,
820 .start = DA8XX_DSP_L1D_RAM_BASE,
821 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
822 .flags = IORESOURCE_MEM,
825 .start = IRQ_DA8XX_CHIPINT0,
826 .end = IRQ_DA8XX_CHIPINT0,
827 .flags = IORESOURCE_IRQ,
831 static struct platform_device da8xx_dsp = {
832 .name = "davinci-rproc",
834 .coherent_dma_mask = DMA_BIT_MASK(32),
836 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
837 .resource = da8xx_rproc_resources,
840 static bool rproc_mem_inited __initdata;
842 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
844 static phys_addr_t rproc_base __initdata;
845 static unsigned long rproc_size __initdata;
847 static int __init early_rproc_mem(char *p)
854 rproc_size = memparse(p, &endp);
856 rproc_base = memparse(endp + 1, NULL);
860 early_param("rproc_mem", early_rproc_mem);
862 void __init da8xx_rproc_reserve_cma(void)
866 if (!rproc_base || !rproc_size) {
867 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
868 " 'nn' and 'address' must both be non-zero\n",
874 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
875 __func__, rproc_size, (unsigned long)rproc_base);
877 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
879 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
881 rproc_mem_inited = true;
886 void __init da8xx_rproc_reserve_cma(void)
892 int __init da8xx_register_rproc(void)
896 if (!rproc_mem_inited) {
897 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
902 ret = platform_device_register(&da8xx_dsp);
904 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
909 static struct resource da8xx_rtc_resources[] = {
911 .start = DA8XX_RTC_BASE,
912 .end = DA8XX_RTC_BASE + SZ_4K - 1,
913 .flags = IORESOURCE_MEM,
916 .start = IRQ_DA8XX_RTC,
917 .end = IRQ_DA8XX_RTC,
918 .flags = IORESOURCE_IRQ,
921 .start = IRQ_DA8XX_RTC,
922 .end = IRQ_DA8XX_RTC,
923 .flags = IORESOURCE_IRQ,
927 static struct platform_device da8xx_rtc_device = {
930 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
931 .resource = da8xx_rtc_resources,
934 int da8xx_register_rtc(void)
936 return platform_device_register(&da8xx_rtc_device);
939 static void __iomem *da8xx_ddr2_ctlr_base;
940 void __iomem * __init da8xx_get_mem_ctlr(void)
942 if (da8xx_ddr2_ctlr_base)
943 return da8xx_ddr2_ctlr_base;
945 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
946 if (!da8xx_ddr2_ctlr_base)
947 pr_warn("%s: Unable to map DDR2 controller", __func__);
949 return da8xx_ddr2_ctlr_base;
952 static struct resource da8xx_cpuidle_resources[] = {
954 .start = DA8XX_DDR2_CTL_BASE,
955 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
956 .flags = IORESOURCE_MEM,
960 /* DA8XX devices support DDR2 power down */
961 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
966 static struct platform_device da8xx_cpuidle_device = {
967 .name = "cpuidle-davinci",
968 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
969 .resource = da8xx_cpuidle_resources,
971 .platform_data = &da8xx_cpuidle_pdata,
975 int __init da8xx_register_cpuidle(void)
977 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
979 return platform_device_register(&da8xx_cpuidle_device);
982 static struct resource da8xx_spi0_resources[] = {
984 .start = DA8XX_SPI0_BASE,
985 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
986 .flags = IORESOURCE_MEM,
989 .start = IRQ_DA8XX_SPINT0,
990 .end = IRQ_DA8XX_SPINT0,
991 .flags = IORESOURCE_IRQ,
995 static struct resource da8xx_spi1_resources[] = {
997 .start = DA830_SPI1_BASE,
998 .end = DA830_SPI1_BASE + SZ_4K - 1,
999 .flags = IORESOURCE_MEM,
1002 .start = IRQ_DA8XX_SPINT1,
1003 .end = IRQ_DA8XX_SPINT1,
1004 .flags = IORESOURCE_IRQ,
1008 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
1010 .version = SPI_VERSION_2,
1012 .dma_event_q = EVENTQ_0,
1013 .prescaler_limit = 2,
1016 .version = SPI_VERSION_2,
1018 .dma_event_q = EVENTQ_0,
1019 .prescaler_limit = 2,
1023 static struct platform_device da8xx_spi_device[] = {
1025 .name = "spi_davinci",
1027 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
1028 .resource = da8xx_spi0_resources,
1030 .platform_data = &da8xx_spi_pdata[0],
1034 .name = "spi_davinci",
1036 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
1037 .resource = da8xx_spi1_resources,
1039 .platform_data = &da8xx_spi_pdata[1],
1044 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1046 if (instance < 0 || instance > 1)
1049 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1051 if (instance == 1 && cpu_is_davinci_da850()) {
1052 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1053 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1056 return platform_device_register(&da8xx_spi_device[instance]);
1059 #ifdef CONFIG_ARCH_DAVINCI_DA850
1060 static struct clk sata_refclk = {
1061 .name = "sata_refclk",
1062 .set_rate = davinci_simple_set_rate,
1065 static struct clk_lookup sata_refclk_lookup =
1066 CLK("ahci_da850", "refclk", &sata_refclk);
1068 int __init da850_register_sata_refclk(int rate)
1072 sata_refclk.rate = rate;
1073 ret = clk_register(&sata_refclk);
1077 clkdev_add(&sata_refclk_lookup);
1082 static struct resource da850_sata_resources[] = {
1084 .start = DA850_SATA_BASE,
1085 .end = DA850_SATA_BASE + 0x1fff,
1086 .flags = IORESOURCE_MEM,
1089 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1090 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1091 .flags = IORESOURCE_MEM,
1094 .start = IRQ_DA850_SATAINT,
1095 .flags = IORESOURCE_IRQ,
1099 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1101 static struct platform_device da850_sata_device = {
1102 .name = "ahci_da850",
1105 .dma_mask = &da850_sata_dmamask,
1106 .coherent_dma_mask = DMA_BIT_MASK(32),
1108 .num_resources = ARRAY_SIZE(da850_sata_resources),
1109 .resource = da850_sata_resources,
1112 int __init da850_register_sata(unsigned long refclkpn)
1116 ret = da850_register_sata_refclk(refclkpn);
1120 return platform_device_register(&da850_sata_device);
1124 static struct syscon_platform_data da8xx_cfgchip_platform_data = {
1128 static struct resource da8xx_cfgchip_resources[] = {
1130 .start = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP0_REG,
1131 .end = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP4_REG + 3,
1132 .flags = IORESOURCE_MEM,
1136 static struct platform_device da8xx_cfgchip_device = {
1140 .platform_data = &da8xx_cfgchip_platform_data,
1142 .num_resources = ARRAY_SIZE(da8xx_cfgchip_resources),
1143 .resource = da8xx_cfgchip_resources,
1146 int __init da8xx_register_cfgchip(void)
1148 return platform_device_register(&da8xx_cfgchip_device);