1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Denali NAND controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
21 There are two register regions:
22 nand_data: host data/command interface
23 denali_reg: register interface
37 There are three clocks:
38 nand: controller core clock
39 nand_x: bus interface clock
40 ecc: ECC circuit clock
52 There are two optional resets:
53 nand: controller core reset
69 $ref: raw-nand-chip.yaml
70 unevaluatedProperties: false
73 - $ref: nand-controller.yaml
79 const: altr,socfpga-denali-nand
96 const: socionext,uniphier-denali-nand-v5a
114 const: socionext,uniphier-denali-nand-v5b
134 unevaluatedProperties: false
138 nand-controller@ff900000 {
139 compatible = "altr,socfpga-denali-nand";
140 reg-names = "nand_data", "denali_reg";
141 reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
142 interrupts = <0 144 4>;
143 clock-names = "nand", "nand_x", "ecc";
144 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
145 reset-names = "nand", "reg";
146 resets = <&nand_rst>, <&nand_reg_rst>;
147 #address-cells = <1>;