1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (C) 2003-2018 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_STXX_DEFS_H__
29 #define __CVMX_STXX_DEFS_H__
31 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
36 #define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
37 #define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
38 #define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
39 #define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
40 #define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
41 #define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
42 #define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
43 #define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
44 #define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
45 #define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
46 #define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
48 void __cvmx_interrupt_stxx_int_msk_enable(int index);
50 union cvmx_stxx_arb_ctl {
52 struct cvmx_stxx_arb_ctl_s {
53 #ifdef __BIG_ENDIAN_BITFIELD
54 uint64_t reserved_6_63:58;
56 uint64_t reserved_4_4:1;
58 uint64_t reserved_0_2:3;
60 uint64_t reserved_0_2:3;
62 uint64_t reserved_4_4:1;
64 uint64_t reserved_6_63:58;
69 union cvmx_stxx_bckprs_cnt {
71 struct cvmx_stxx_bckprs_cnt_s {
72 #ifdef __BIG_ENDIAN_BITFIELD
73 uint64_t reserved_32_63:32;
77 uint64_t reserved_32_63:32;
82 union cvmx_stxx_com_ctl {
84 struct cvmx_stxx_com_ctl_s {
85 #ifdef __BIG_ENDIAN_BITFIELD
86 uint64_t reserved_4_63:60;
88 uint64_t reserved_1_2:2;
92 uint64_t reserved_1_2:2;
94 uint64_t reserved_4_63:60;
99 union cvmx_stxx_dip_cnt {
101 struct cvmx_stxx_dip_cnt_s {
102 #ifdef __BIG_ENDIAN_BITFIELD
103 uint64_t reserved_8_63:56;
109 uint64_t reserved_8_63:56;
114 union cvmx_stxx_ign_cal {
116 struct cvmx_stxx_ign_cal_s {
117 #ifdef __BIG_ENDIAN_BITFIELD
118 uint64_t reserved_16_63:48;
122 uint64_t reserved_16_63:48;
127 union cvmx_stxx_int_msk {
129 struct cvmx_stxx_int_msk_s {
130 #ifdef __BIG_ENDIAN_BITFIELD
131 uint64_t reserved_8_63:56;
149 uint64_t reserved_8_63:56;
154 union cvmx_stxx_int_reg {
156 struct cvmx_stxx_int_reg_s {
157 #ifdef __BIG_ENDIAN_BITFIELD
158 uint64_t reserved_9_63:55;
178 uint64_t reserved_9_63:55;
183 union cvmx_stxx_int_sync {
185 struct cvmx_stxx_int_sync_s {
186 #ifdef __BIG_ENDIAN_BITFIELD
187 uint64_t reserved_8_63:56;
205 uint64_t reserved_8_63:56;
210 union cvmx_stxx_min_bst {
212 struct cvmx_stxx_min_bst_s {
213 #ifdef __BIG_ENDIAN_BITFIELD
214 uint64_t reserved_9_63:55;
218 uint64_t reserved_9_63:55;
223 union cvmx_stxx_spi4_calx {
225 struct cvmx_stxx_spi4_calx_s {
226 #ifdef __BIG_ENDIAN_BITFIELD
227 uint64_t reserved_17_63:47;
239 uint64_t reserved_17_63:47;
244 union cvmx_stxx_spi4_dat {
246 struct cvmx_stxx_spi4_dat_s {
247 #ifdef __BIG_ENDIAN_BITFIELD
248 uint64_t reserved_32_63:32;
254 uint64_t reserved_32_63:32;
259 union cvmx_stxx_spi4_stat {
261 struct cvmx_stxx_spi4_stat_s {
262 #ifdef __BIG_ENDIAN_BITFIELD
263 uint64_t reserved_16_63:48;
265 uint64_t reserved_7_7:1;
269 uint64_t reserved_7_7:1;
271 uint64_t reserved_16_63:48;
276 union cvmx_stxx_stat_bytes_hi {
278 struct cvmx_stxx_stat_bytes_hi_s {
279 #ifdef __BIG_ENDIAN_BITFIELD
280 uint64_t reserved_32_63:32;
284 uint64_t reserved_32_63:32;
289 union cvmx_stxx_stat_bytes_lo {
291 struct cvmx_stxx_stat_bytes_lo_s {
292 #ifdef __BIG_ENDIAN_BITFIELD
293 uint64_t reserved_32_63:32;
297 uint64_t reserved_32_63:32;
302 union cvmx_stxx_stat_ctl {
304 struct cvmx_stxx_stat_ctl_s {
305 #ifdef __BIG_ENDIAN_BITFIELD
306 uint64_t reserved_5_63:59;
312 uint64_t reserved_5_63:59;
317 union cvmx_stxx_stat_pkt_xmt {
319 struct cvmx_stxx_stat_pkt_xmt_s {
320 #ifdef __BIG_ENDIAN_BITFIELD
321 uint64_t reserved_32_63:32;
325 uint64_t reserved_32_63:32;