1 /***********************license start***************
4 * Contact: support@cavium.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2014 Cavium Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Inc. for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_RST_DEFS_H__
29 #define __CVMX_RST_DEFS_H__
31 #define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull))
32 #define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull))
33 #define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull))
34 #define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8)
35 #define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull))
36 #define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull))
37 #define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull))
38 #define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull))
39 #define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull))
40 #define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull))
41 #define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8)
42 #define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull))
46 struct cvmx_rst_boot_s {
47 #ifdef __BIG_ENDIAN_BITFIELD
52 uint64_t ckill_ppdis:1;
53 uint64_t jt_tstmode:1;
55 uint64_t reserved_37_56:20;
58 uint64_t reserved_21_23:3;
70 uint64_t reserved_21_23:3;
73 uint64_t reserved_37_56:20;
75 uint64_t jt_tstmode:1;
76 uint64_t ckill_ppdis:1;
87 struct cvmx_rst_cfg_s {
88 #ifdef __BIG_ENDIAN_BITFIELD
89 uint64_t bist_delay:58;
90 uint64_t reserved_3_5:3;
91 uint64_t cntl_clr_bist:1;
92 uint64_t warm_clr_bist:1;
93 uint64_t soft_clr_bist:1;
95 uint64_t soft_clr_bist:1;
96 uint64_t warm_clr_bist:1;
97 uint64_t cntl_clr_bist:1;
98 uint64_t reserved_3_5:3;
99 uint64_t bist_delay:58;
104 union cvmx_rst_ckill {
106 struct cvmx_rst_ckill_s {
107 #ifdef __BIG_ENDIAN_BITFIELD
108 uint64_t reserved_47_63:17;
112 uint64_t reserved_47_63:17;
117 union cvmx_rst_ctlx {
119 struct cvmx_rst_ctlx_s {
120 #ifdef __BIG_ENDIAN_BITFIELD
121 uint64_t reserved_10_63:54;
122 uint64_t prst_link:1;
125 uint64_t host_mode:1;
126 uint64_t reserved_4_5:2;
136 uint64_t reserved_4_5:2;
137 uint64_t host_mode:1;
140 uint64_t prst_link:1;
141 uint64_t reserved_10_63:54;
146 union cvmx_rst_delay {
148 struct cvmx_rst_delay_s {
149 #ifdef __BIG_ENDIAN_BITFIELD
150 uint64_t reserved_32_63:32;
151 uint64_t warm_rst_dly:16;
152 uint64_t soft_rst_dly:16;
154 uint64_t soft_rst_dly:16;
155 uint64_t warm_rst_dly:16;
156 uint64_t reserved_32_63:32;
163 struct cvmx_rst_eco_s {
164 #ifdef __BIG_ENDIAN_BITFIELD
165 uint64_t reserved_32_63:32;
169 uint64_t reserved_32_63:32;
176 struct cvmx_rst_int_s {
177 #ifdef __BIG_ENDIAN_BITFIELD
178 uint64_t reserved_12_63:52;
180 uint64_t reserved_4_7:4;
184 uint64_t reserved_4_7:4;
186 uint64_t reserved_12_63:52;
189 struct cvmx_rst_int_cn70xx {
190 #ifdef __BIG_ENDIAN_BITFIELD
191 uint64_t reserved_11_63:53;
193 uint64_t reserved_3_7:5;
197 uint64_t reserved_3_7:5;
199 uint64_t reserved_11_63:53;
206 struct cvmx_rst_ocx_s {
207 #ifdef __BIG_ENDIAN_BITFIELD
208 uint64_t reserved_3_63:61;
212 uint64_t reserved_3_63:61;
217 union cvmx_rst_power_dbg {
219 struct cvmx_rst_power_dbg_s {
220 #ifdef __BIG_ENDIAN_BITFIELD
221 uint64_t reserved_3_63:61;
225 uint64_t reserved_3_63:61;
230 union cvmx_rst_pp_power {
232 struct cvmx_rst_pp_power_s {
233 #ifdef __BIG_ENDIAN_BITFIELD
234 uint64_t reserved_48_63:16;
238 uint64_t reserved_48_63:16;
241 struct cvmx_rst_pp_power_cn70xx {
242 #ifdef __BIG_ENDIAN_BITFIELD
243 uint64_t reserved_4_63:60;
247 uint64_t reserved_4_63:60;
252 union cvmx_rst_soft_prstx {
254 struct cvmx_rst_soft_prstx_s {
255 #ifdef __BIG_ENDIAN_BITFIELD
256 uint64_t reserved_1_63:63;
257 uint64_t soft_prst:1;
259 uint64_t soft_prst:1;
260 uint64_t reserved_1_63:63;
265 union cvmx_rst_soft_rst {
267 struct cvmx_rst_soft_rst_s {
268 #ifdef __BIG_ENDIAN_BITFIELD
269 uint64_t reserved_1_63:63;
273 uint64_t reserved_1_63:63;