2 * Driver for IBM PowerNV 842 compression accelerator
4 * Copyright (C) 2015 Dan Streetman, IBM Corp
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/timer.h>
24 #include <asm/icswx.h>
28 MODULE_LICENSE("GPL");
29 MODULE_AUTHOR("Dan Streetman <ddstreet@ieee.org>");
30 MODULE_DESCRIPTION("842 H/W Compression driver for IBM PowerNV processors");
31 MODULE_ALIAS_CRYPTO("842");
32 MODULE_ALIAS_CRYPTO("842-nx");
34 #define WORKMEM_ALIGN (CRB_ALIGN)
35 #define CSB_WAIT_MAX (5000) /* ms */
36 #define VAS_RETRIES (10)
38 struct nx842_workmem {
39 /* Below fields must be properly aligned */
40 struct coprocessor_request_block crb; /* CRB_ALIGN align */
41 struct data_descriptor_entry ddl_in[DDL_LEN_MAX]; /* DDE_ALIGN align */
42 struct data_descriptor_entry ddl_out[DDL_LEN_MAX]; /* DDE_ALIGN align */
43 /* Above fields must be properly aligned */
47 struct vas_window *txwin; /* Used with VAS function */
48 char padding[WORKMEM_ALIGN]; /* unused, to allow alignment */
49 } __packed __aligned(WORKMEM_ALIGN);
54 unsigned int ci; /* Coprocessor instance, used with icswx */
56 struct vas_window *rxwin;
59 struct list_head list;
63 * Send the request to NX engine on the chip for the corresponding CPU
64 * where the process is executing. Use with VAS function.
66 static DEFINE_PER_CPU(struct nx842_coproc *, coproc_inst);
68 /* no cpu hotplug on powernv, so this list never changes after init */
69 static LIST_HEAD(nx842_coprocs);
70 static unsigned int nx842_ct; /* used in icswx function */
72 static int (*nx842_powernv_exec)(const unsigned char *in,
73 unsigned int inlen, unsigned char *out,
74 unsigned int *outlenp, void *workmem, int fc);
77 * setup_indirect_dde - Setup an indirect DDE
79 * The DDE is setup with the the DDE count, byte count, and address of
80 * first direct DDE in the list.
82 static void setup_indirect_dde(struct data_descriptor_entry *dde,
83 struct data_descriptor_entry *ddl,
84 unsigned int dde_count, unsigned int byte_count)
87 dde->count = dde_count;
89 dde->length = cpu_to_be32(byte_count);
90 dde->address = cpu_to_be64(nx842_get_pa(ddl));
94 * setup_direct_dde - Setup single DDE from buffer
96 * The DDE is setup with the buffer and length. The buffer must be properly
97 * aligned. The used length is returned.
99 * N Successfully set up DDE with N bytes
101 static unsigned int setup_direct_dde(struct data_descriptor_entry *dde,
102 unsigned long pa, unsigned int len)
104 unsigned int l = min_t(unsigned int, len, LEN_ON_PAGE(pa));
109 dde->length = cpu_to_be32(l);
110 dde->address = cpu_to_be64(pa);
116 * setup_ddl - Setup DDL from buffer
119 * 0 Successfully set up DDL
121 static int setup_ddl(struct data_descriptor_entry *dde,
122 struct data_descriptor_entry *ddl,
123 unsigned char *buf, unsigned int len,
126 unsigned long pa = nx842_get_pa(buf);
127 int i, ret, total_len = len;
129 if (!IS_ALIGNED(pa, DDE_BUFFER_ALIGN)) {
130 pr_debug("%s buffer pa 0x%lx not 0x%x-byte aligned\n",
131 in ? "input" : "output", pa, DDE_BUFFER_ALIGN);
135 /* only need to check last mult; since buffer must be
136 * DDE_BUFFER_ALIGN aligned, and that is a multiple of
137 * DDE_BUFFER_SIZE_MULT, and pre-last page DDE buffers
138 * are guaranteed a multiple of DDE_BUFFER_SIZE_MULT.
140 if (len % DDE_BUFFER_LAST_MULT) {
141 pr_debug("%s buffer len 0x%x not a multiple of 0x%x\n",
142 in ? "input" : "output", len, DDE_BUFFER_LAST_MULT);
145 len = round_down(len, DDE_BUFFER_LAST_MULT);
148 /* use a single direct DDE */
149 if (len <= LEN_ON_PAGE(pa)) {
150 ret = setup_direct_dde(dde, pa, len);
156 for (i = 0; i < DDL_LEN_MAX && len > 0; i++) {
157 ret = setup_direct_dde(&ddl[i], pa, len);
160 pa = nx842_get_pa(buf);
164 pr_debug("0x%x total %s bytes 0x%x too many for DDL.\n",
165 total_len, in ? "input" : "output", len);
170 setup_indirect_dde(dde, ddl, i, total_len);
175 #define CSB_ERR(csb, msg, ...) \
176 pr_err("ERROR: " msg " : %02x %02x %02x %02x %08x\n", \
177 ##__VA_ARGS__, (csb)->flags, \
178 (csb)->cs, (csb)->cc, (csb)->ce, \
179 be32_to_cpu((csb)->count))
181 #define CSB_ERR_ADDR(csb, msg, ...) \
182 CSB_ERR(csb, msg " at %lx", ##__VA_ARGS__, \
183 (unsigned long)be64_to_cpu((csb)->address))
188 static int wait_for_csb(struct nx842_workmem *wmem,
189 struct coprocessor_status_block *csb)
191 ktime_t start = wmem->start, now = ktime_get();
192 ktime_t timeout = ktime_add_ms(start, CSB_WAIT_MAX);
194 while (!(ACCESS_ONCE(csb->flags) & CSB_V)) {
197 if (ktime_after(now, timeout))
201 /* hw has updated csb and output buffer */
204 /* check CSB flags */
205 if (!(csb->flags & CSB_V)) {
206 CSB_ERR(csb, "CSB still not valid after %ld us, giving up",
207 (long)ktime_us_delta(now, start));
210 if (csb->flags & CSB_F) {
211 CSB_ERR(csb, "Invalid CSB format");
214 if (csb->flags & CSB_CH) {
215 CSB_ERR(csb, "Invalid CSB chaining state");
219 /* verify CSB completion sequence is 0 */
221 CSB_ERR(csb, "Invalid CSB completion sequence");
225 /* check CSB Completion Code */
230 case CSB_CC_TPBC_GT_SPBC:
231 /* not an error, but the compressed data is
232 * larger than the uncompressed data :(
236 /* input data errors */
237 case CSB_CC_OPERAND_OVERLAP:
238 /* input and output buffers overlap */
239 CSB_ERR(csb, "Operand Overlap error");
241 case CSB_CC_INVALID_OPERAND:
242 CSB_ERR(csb, "Invalid operand");
245 /* output buffer too small */
248 CSB_ERR(csb, "Function aborted");
250 case CSB_CC_CRC_MISMATCH:
251 CSB_ERR(csb, "CRC mismatch");
253 case CSB_CC_TEMPL_INVALID:
254 CSB_ERR(csb, "Compressed data template invalid");
256 case CSB_CC_TEMPL_OVERFLOW:
257 CSB_ERR(csb, "Compressed data template shows data past end");
259 case CSB_CC_EXCEED_BYTE_COUNT: /* P9 or later */
261 * DDE byte count exceeds the limit specified in Maximum
262 * byte count register.
264 CSB_ERR(csb, "DDE byte count exceeds the limit");
267 /* these should not happen */
268 case CSB_CC_INVALID_ALIGN:
269 /* setup_ddl should have detected this */
270 CSB_ERR_ADDR(csb, "Invalid alignment");
272 case CSB_CC_DATA_LENGTH:
273 /* setup_ddl should have detected this */
274 CSB_ERR(csb, "Invalid data length");
276 case CSB_CC_WR_TRANSLATION:
277 case CSB_CC_TRANSLATION:
278 case CSB_CC_TRANSLATION_DUP1:
279 case CSB_CC_TRANSLATION_DUP2:
280 case CSB_CC_TRANSLATION_DUP3:
281 case CSB_CC_TRANSLATION_DUP4:
282 case CSB_CC_TRANSLATION_DUP5:
283 case CSB_CC_TRANSLATION_DUP6:
284 /* should not happen, we use physical addrs */
285 CSB_ERR_ADDR(csb, "Translation error");
287 case CSB_CC_WR_PROTECTION:
288 case CSB_CC_PROTECTION:
289 case CSB_CC_PROTECTION_DUP1:
290 case CSB_CC_PROTECTION_DUP2:
291 case CSB_CC_PROTECTION_DUP3:
292 case CSB_CC_PROTECTION_DUP4:
293 case CSB_CC_PROTECTION_DUP5:
294 case CSB_CC_PROTECTION_DUP6:
295 /* should not happen, we use physical addrs */
296 CSB_ERR_ADDR(csb, "Protection error");
298 case CSB_CC_PRIVILEGE:
299 /* shouldn't happen, we're in HYP mode */
300 CSB_ERR(csb, "Insufficient Privilege error");
302 case CSB_CC_EXCESSIVE_DDE:
303 /* shouldn't happen, setup_ddl doesn't use many dde's */
304 CSB_ERR(csb, "Too many DDEs in DDL");
306 case CSB_CC_TRANSPORT:
307 case CSB_CC_INVALID_CRB: /* P9 or later */
308 /* shouldn't happen, we setup CRB correctly */
309 CSB_ERR(csb, "Invalid CRB");
311 case CSB_CC_INVALID_DDE: /* P9 or later */
313 * shouldn't happen, setup_direct/indirect_dde creates
316 CSB_ERR(csb, "Invalid DDE");
318 case CSB_CC_SEGMENTED_DDL:
319 /* shouldn't happen, setup_ddl creates DDL right */
320 CSB_ERR(csb, "Segmented DDL error");
322 case CSB_CC_DDE_OVERFLOW:
323 /* shouldn't happen, setup_ddl creates DDL right */
324 CSB_ERR(csb, "DDE overflow error");
327 /* should not happen with ICSWX */
328 CSB_ERR(csb, "Session violation error");
331 /* should not happen, we don't use chained CRBs */
332 CSB_ERR(csb, "Chained CRB error");
334 case CSB_CC_SEQUENCE:
335 /* should not happen, we don't use chained CRBs */
336 CSB_ERR(csb, "CRB seqeunce number error");
338 case CSB_CC_UNKNOWN_CODE:
339 CSB_ERR(csb, "Unknown subfunction code");
342 /* hardware errors */
343 case CSB_CC_RD_EXTERNAL:
344 case CSB_CC_RD_EXTERNAL_DUP1:
345 case CSB_CC_RD_EXTERNAL_DUP2:
346 case CSB_CC_RD_EXTERNAL_DUP3:
347 CSB_ERR_ADDR(csb, "Read error outside coprocessor");
349 case CSB_CC_WR_EXTERNAL:
350 CSB_ERR_ADDR(csb, "Write error outside coprocessor");
352 case CSB_CC_INTERNAL:
353 CSB_ERR(csb, "Internal error in coprocessor");
355 case CSB_CC_PROVISION:
356 CSB_ERR(csb, "Storage provision error");
359 CSB_ERR(csb, "Correctable hardware error");
361 case CSB_CC_HW_EXPIRED_TIMER: /* P9 or later */
362 CSB_ERR(csb, "Job did not finish within allowed time");
366 CSB_ERR(csb, "Invalid CC %d", csb->cc);
370 /* check Completion Extension state */
371 if (csb->ce & CSB_CE_TERMINATION) {
372 CSB_ERR(csb, "CSB request was terminated");
375 if (csb->ce & CSB_CE_INCOMPLETE) {
376 CSB_ERR(csb, "CSB request not complete");
379 if (!(csb->ce & CSB_CE_TPBC)) {
380 CSB_ERR(csb, "TPBC not provided, unknown target length");
384 /* successful completion */
385 pr_debug_ratelimited("Processed %u bytes in %lu us\n",
386 be32_to_cpu(csb->count),
387 (unsigned long)ktime_us_delta(now, start));
392 static int nx842_config_crb(const unsigned char *in, unsigned int inlen,
393 unsigned char *out, unsigned int outlen,
394 struct nx842_workmem *wmem)
396 struct coprocessor_request_block *crb;
397 struct coprocessor_status_block *csb;
404 /* Clear any previous values */
405 memset(crb, 0, sizeof(*crb));
408 ret = setup_ddl(&crb->source, wmem->ddl_in,
409 (unsigned char *)in, inlen, true);
413 ret = setup_ddl(&crb->target, wmem->ddl_out,
418 /* set up CRB's CSB addr */
419 csb_addr = nx842_get_pa(csb) & CRB_CSB_ADDRESS;
420 csb_addr |= CRB_CSB_AT; /* Addrs are phys */
421 crb->csb_addr = cpu_to_be64(csb_addr);
427 * nx842_exec_icswx - compress/decompress data using the 842 algorithm
429 * (De)compression provided by the NX842 coprocessor on IBM PowerNV systems.
430 * This compresses or decompresses the provided input buffer into the provided
433 * Upon return from this function @outlen contains the length of the
434 * output data. If there is an error then @outlen will be 0 and an
435 * error will be specified by the return code from this function.
437 * The @workmem buffer should only be used by one function call at a time.
439 * @in: input buffer pointer
440 * @inlen: input buffer size
441 * @out: output buffer pointer
442 * @outlenp: output buffer size pointer
443 * @workmem: working memory buffer pointer, size determined by
444 * nx842_powernv_driver.workmem_size
445 * @fc: function code, see CCW Function Codes in nx-842.h
448 * 0 Success, output of length @outlenp stored in the buffer at @out
449 * -ENODEV Hardware unavailable
450 * -ENOSPC Output buffer is to small
451 * -EMSGSIZE Input buffer too large
452 * -EINVAL buffer constraints do not fix nx842_constraints
453 * -EPROTO hardware error during operation
454 * -ETIMEDOUT hardware did not complete operation in reasonable time
455 * -EINTR operation was aborted
457 static int nx842_exec_icswx(const unsigned char *in, unsigned int inlen,
458 unsigned char *out, unsigned int *outlenp,
459 void *workmem, int fc)
461 struct coprocessor_request_block *crb;
462 struct coprocessor_status_block *csb;
463 struct nx842_workmem *wmem;
466 unsigned int outlen = *outlenp;
468 wmem = PTR_ALIGN(workmem, WORKMEM_ALIGN);
472 /* shoudn't happen, we don't load without a coproc */
474 pr_err_ratelimited("coprocessor CT is 0");
478 ret = nx842_config_crb(in, inlen, out, outlen, wmem);
487 ccw = SET_FIELD(CCW_CT, ccw, nx842_ct);
488 ccw = SET_FIELD(CCW_CI_842, ccw, 0); /* use 0 for hw auto-selection */
489 ccw = SET_FIELD(CCW_FC_842, ccw, fc);
491 wmem->start = ktime_get();
494 ret = icswx(cpu_to_be32(ccw), crb);
496 pr_debug_ratelimited("icswx CR %x ccw %x crb->ccw %x\n", ret,
498 (unsigned int)be32_to_cpu(crb->ccw));
501 * NX842 coprocessor sets 3rd bit in CR register with XER[S0].
502 * XER[S0] is the integer summary overflow bit which is nothing
503 * to do NX. Since this bit can be set with other return values,
509 case ICSWX_INITIATED:
510 ret = wait_for_csb(wmem, csb);
513 pr_debug_ratelimited("842 Coprocessor busy\n");
517 pr_err_ratelimited("ICSWX rejected\n");
523 *outlenp = be32_to_cpu(csb->count);
529 * nx842_exec_vas - compress/decompress data using the 842 algorithm
531 * (De)compression provided by the NX842 coprocessor on IBM PowerNV systems.
532 * This compresses or decompresses the provided input buffer into the provided
535 * Upon return from this function @outlen contains the length of the
536 * output data. If there is an error then @outlen will be 0 and an
537 * error will be specified by the return code from this function.
539 * The @workmem buffer should only be used by one function call at a time.
541 * @in: input buffer pointer
542 * @inlen: input buffer size
543 * @out: output buffer pointer
544 * @outlenp: output buffer size pointer
545 * @workmem: working memory buffer pointer, size determined by
546 * nx842_powernv_driver.workmem_size
547 * @fc: function code, see CCW Function Codes in nx-842.h
550 * 0 Success, output of length @outlenp stored in the buffer
552 * -ENODEV Hardware unavailable
553 * -ENOSPC Output buffer is to small
554 * -EMSGSIZE Input buffer too large
555 * -EINVAL buffer constraints do not fix nx842_constraints
556 * -EPROTO hardware error during operation
557 * -ETIMEDOUT hardware did not complete operation in reasonable time
558 * -EINTR operation was aborted
560 static int nx842_exec_vas(const unsigned char *in, unsigned int inlen,
561 unsigned char *out, unsigned int *outlenp,
562 void *workmem, int fc)
564 struct coprocessor_request_block *crb;
565 struct coprocessor_status_block *csb;
566 struct nx842_workmem *wmem;
567 struct vas_window *txwin;
570 unsigned int outlen = *outlenp;
572 wmem = PTR_ALIGN(workmem, WORKMEM_ALIGN);
579 ret = nx842_config_crb(in, inlen, out, outlen, wmem);
584 ccw = SET_FIELD(CCW_FC_842, ccw, fc);
585 crb->ccw = cpu_to_be32(ccw);
588 /* shoudn't happen, we don't load without a coproc */
590 pr_err_ratelimited("NX-842 coprocessor is not available");
595 wmem->start = ktime_get();
598 * VAS copy CRB into L2 cache. Refer <asm/vas.h>.
601 vas_copy_crb(crb, 0);
604 * VAS paste previously copied CRB to NX.
605 * @txwin, @offset and @last (must be true).
607 ret = vas_paste_crb(txwin, 0, 1);
610 * Retry copy/paste function for VAS failures.
612 } while (ret && (i++ < VAS_RETRIES));
615 pr_err_ratelimited("VAS copy/paste failed\n");
619 ret = wait_for_csb(wmem, csb);
621 *outlenp = be32_to_cpu(csb->count);
627 * nx842_powernv_compress - Compress data using the 842 algorithm
629 * Compression provided by the NX842 coprocessor on IBM PowerNV systems.
630 * The input buffer is compressed and the result is stored in the
631 * provided output buffer.
633 * Upon return from this function @outlen contains the length of the
634 * compressed data. If there is an error then @outlen will be 0 and an
635 * error will be specified by the return code from this function.
637 * @in: input buffer pointer
638 * @inlen: input buffer size
639 * @out: output buffer pointer
640 * @outlenp: output buffer size pointer
641 * @workmem: working memory buffer pointer, size determined by
642 * nx842_powernv_driver.workmem_size
644 * Returns: see @nx842_powernv_exec()
646 static int nx842_powernv_compress(const unsigned char *in, unsigned int inlen,
647 unsigned char *out, unsigned int *outlenp,
650 return nx842_powernv_exec(in, inlen, out, outlenp,
651 wmem, CCW_FC_842_COMP_CRC);
655 * nx842_powernv_decompress - Decompress data using the 842 algorithm
657 * Decompression provided by the NX842 coprocessor on IBM PowerNV systems.
658 * The input buffer is decompressed and the result is stored in the
659 * provided output buffer.
661 * Upon return from this function @outlen contains the length of the
662 * decompressed data. If there is an error then @outlen will be 0 and an
663 * error will be specified by the return code from this function.
665 * @in: input buffer pointer
666 * @inlen: input buffer size
667 * @out: output buffer pointer
668 * @outlenp: output buffer size pointer
669 * @workmem: working memory buffer pointer, size determined by
670 * nx842_powernv_driver.workmem_size
672 * Returns: see @nx842_powernv_exec()
674 static int nx842_powernv_decompress(const unsigned char *in, unsigned int inlen,
675 unsigned char *out, unsigned int *outlenp,
678 return nx842_powernv_exec(in, inlen, out, outlenp,
679 wmem, CCW_FC_842_DECOMP_CRC);
682 static inline void nx842_add_coprocs_list(struct nx842_coproc *coproc,
685 coproc->chip_id = chipid;
686 INIT_LIST_HEAD(&coproc->list);
687 list_add(&coproc->list, &nx842_coprocs);
691 * Identify chip ID for each CPU and save coprocesor adddress for the
692 * corresponding NX engine in percpu coproc_inst.
693 * coproc_inst is used in crypto_init to open send window on the NX instance
694 * for the corresponding CPU / chip where the open request is executed.
696 static void nx842_set_per_cpu_coproc(struct nx842_coproc *coproc)
698 unsigned int i, chip_id;
700 for_each_possible_cpu(i) {
701 chip_id = cpu_to_chip_id(i);
703 if (coproc->chip_id == chip_id)
704 per_cpu(coproc_inst, i) = coproc;
709 static struct vas_window *nx842_alloc_txwin(struct nx842_coproc *coproc)
711 struct vas_window *txwin = NULL;
712 struct vas_tx_win_attr txattr;
715 * Kernel requests will be high priority. So open send
716 * windows only for high priority RxFIFO entries.
718 vas_init_tx_win_attr(&txattr, coproc->ct);
719 txattr.lpid = 0; /* lpid is 0 for kernel requests */
720 txattr.pid = 0; /* pid is 0 for kernel requests */
723 * Open a VAS send window which is used to send request to NX.
725 txwin = vas_tx_win_open(coproc->vas.id, coproc->ct, &txattr);
727 pr_err("ibm,nx-842: Can not open TX window: %ld\n",
735 static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
738 struct vas_window *rxwin = NULL;
739 struct vas_rx_win_attr rxattr;
740 struct nx842_coproc *coproc;
741 u32 lpid, pid, tid, fifo_size;
743 const char *priority;
746 ret = of_property_read_u64(dn, "rx-fifo-address", &rx_fifo);
748 pr_err("Missing rx-fifo-address property\n");
752 ret = of_property_read_u32(dn, "rx-fifo-size", &fifo_size);
754 pr_err("Missing rx-fifo-size property\n");
758 ret = of_property_read_u32(dn, "lpid", &lpid);
760 pr_err("Missing lpid property\n");
764 ret = of_property_read_u32(dn, "pid", &pid);
766 pr_err("Missing pid property\n");
770 ret = of_property_read_u32(dn, "tid", &tid);
772 pr_err("Missing tid property\n");
776 ret = of_property_read_string(dn, "priority", &priority);
778 pr_err("Missing priority property\n");
782 coproc = kzalloc(sizeof(*coproc), GFP_KERNEL);
786 if (!strcmp(priority, "High"))
787 coproc->ct = VAS_COP_TYPE_842_HIPRI;
788 else if (!strcmp(priority, "Normal"))
789 coproc->ct = VAS_COP_TYPE_842;
791 pr_err("Invalid RxFIFO priority value\n");
796 vas_init_rx_win_attr(&rxattr, coproc->ct);
797 rxattr.rx_fifo = (void *)rx_fifo;
798 rxattr.rx_fifo_size = fifo_size;
799 rxattr.lnotify_lpid = lpid;
800 rxattr.lnotify_pid = pid;
801 rxattr.lnotify_tid = tid;
803 * Maximum RX window credits can not be more than #CRBs in
804 * RxFIFO. Otherwise, can get checkstop if RxFIFO overruns.
806 rxattr.wcreds_max = fifo_size / CRB_SIZE;
809 * Open a VAS receice window which is used to configure RxFIFO
812 rxwin = vas_rx_win_open(vasid, coproc->ct, &rxattr);
814 ret = PTR_ERR(rxwin);
815 pr_err("setting RxFIFO with VAS failed: %d\n",
820 coproc->vas.rxwin = rxwin;
821 coproc->vas.id = vasid;
822 nx842_add_coprocs_list(coproc, chip_id);
825 * Kernel requests use only high priority FIFOs. So save coproc
826 * info in percpu coproc_inst which will be used to open send
827 * windows for crypto open requests later.
829 if (coproc->ct == VAS_COP_TYPE_842_HIPRI)
830 nx842_set_per_cpu_coproc(coproc);
840 static int __init nx842_powernv_probe_vas(struct device_node *pn)
842 struct device_node *dn;
843 int chip_id, vasid, ret = 0;
844 int nx_fifo_found = 0;
846 chip_id = of_get_ibm_chip_id(pn);
848 pr_err("ibm,chip-id missing\n");
852 for_each_compatible_node(dn, NULL, "ibm,power9-vas-x") {
853 if (of_get_ibm_chip_id(dn) == chip_id)
858 pr_err("Missing VAS device node\n");
862 if (of_property_read_u32(dn, "ibm,vas-id", &vasid)) {
863 pr_err("Missing ibm,vas-id device property\n");
870 for_each_child_of_node(pn, dn) {
871 if (of_device_is_compatible(dn, "ibm,p9-nx-842")) {
872 ret = vas_cfg_coproc_info(dn, chip_id, vasid);
881 if (!nx_fifo_found) {
882 pr_err("NX842 FIFO nodes are missing\n");
889 static int __init nx842_powernv_probe(struct device_node *dn)
891 struct nx842_coproc *coproc;
895 chip_id = of_get_ibm_chip_id(dn);
897 pr_err("ibm,chip-id missing\n");
901 if (of_property_read_u32(dn, "ibm,842-coprocessor-type", &ct)) {
902 pr_err("ibm,842-coprocessor-type missing\n");
906 if (of_property_read_u32(dn, "ibm,842-coprocessor-instance", &ci)) {
907 pr_err("ibm,842-coprocessor-instance missing\n");
911 coproc = kmalloc(sizeof(*coproc), GFP_KERNEL);
917 nx842_add_coprocs_list(coproc, chip_id);
919 pr_info("coprocessor found on chip %d, CT %d CI %d\n", chip_id, ct, ci);
923 else if (nx842_ct != ct)
924 pr_err("NX842 chip %d, CT %d != first found CT %d\n",
925 chip_id, ct, nx842_ct);
930 static void nx842_delete_coprocs(void)
932 struct nx842_coproc *coproc, *n;
934 list_for_each_entry_safe(coproc, n, &nx842_coprocs, list) {
935 if (coproc->vas.rxwin)
936 vas_win_close(coproc->vas.rxwin);
938 list_del(&coproc->list);
943 static struct nx842_constraints nx842_powernv_constraints = {
944 .alignment = DDE_BUFFER_ALIGN,
945 .multiple = DDE_BUFFER_LAST_MULT,
946 .minimum = DDE_BUFFER_LAST_MULT,
947 .maximum = (DDL_LEN_MAX - 1) * PAGE_SIZE,
950 static struct nx842_driver nx842_powernv_driver = {
951 .name = KBUILD_MODNAME,
952 .owner = THIS_MODULE,
953 .workmem_size = sizeof(struct nx842_workmem),
954 .constraints = &nx842_powernv_constraints,
955 .compress = nx842_powernv_compress,
956 .decompress = nx842_powernv_decompress,
959 static int nx842_powernv_crypto_init_vas(struct crypto_tfm *tfm)
961 struct nx842_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
962 struct nx842_workmem *wmem;
963 struct nx842_coproc *coproc;
966 ret = nx842_crypto_init(tfm, &nx842_powernv_driver);
971 wmem = PTR_ALIGN((struct nx842_workmem *)ctx->wmem, WORKMEM_ALIGN);
972 coproc = per_cpu(coproc_inst, smp_processor_id());
975 if (coproc && coproc->vas.rxwin) {
976 wmem->txwin = nx842_alloc_txwin(coproc);
977 if (!IS_ERR(wmem->txwin))
980 ret = PTR_ERR(wmem->txwin);
986 void nx842_powernv_crypto_exit_vas(struct crypto_tfm *tfm)
988 struct nx842_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
989 struct nx842_workmem *wmem;
991 wmem = PTR_ALIGN((struct nx842_workmem *)ctx->wmem, WORKMEM_ALIGN);
993 if (wmem && wmem->txwin)
994 vas_win_close(wmem->txwin);
996 nx842_crypto_exit(tfm);
999 static int nx842_powernv_crypto_init(struct crypto_tfm *tfm)
1001 return nx842_crypto_init(tfm, &nx842_powernv_driver);
1004 static struct crypto_alg nx842_powernv_alg = {
1006 .cra_driver_name = "842-nx",
1007 .cra_priority = 300,
1008 .cra_flags = CRYPTO_ALG_TYPE_COMPRESS,
1009 .cra_ctxsize = sizeof(struct nx842_crypto_ctx),
1010 .cra_module = THIS_MODULE,
1011 .cra_init = nx842_powernv_crypto_init,
1012 .cra_exit = nx842_crypto_exit,
1013 .cra_u = { .compress = {
1014 .coa_compress = nx842_crypto_compress,
1015 .coa_decompress = nx842_crypto_decompress } }
1018 static __init int nx842_powernv_init(void)
1020 struct device_node *dn;
1023 /* verify workmem size/align restrictions */
1024 BUILD_BUG_ON(WORKMEM_ALIGN % CRB_ALIGN);
1025 BUILD_BUG_ON(CRB_ALIGN % DDE_ALIGN);
1026 BUILD_BUG_ON(CRB_SIZE % DDE_ALIGN);
1027 /* verify buffer size/align restrictions */
1028 BUILD_BUG_ON(PAGE_SIZE % DDE_BUFFER_ALIGN);
1029 BUILD_BUG_ON(DDE_BUFFER_ALIGN % DDE_BUFFER_SIZE_MULT);
1030 BUILD_BUG_ON(DDE_BUFFER_SIZE_MULT % DDE_BUFFER_LAST_MULT);
1032 for_each_compatible_node(dn, NULL, "ibm,power9-nx") {
1033 ret = nx842_powernv_probe_vas(dn);
1035 nx842_delete_coprocs();
1040 if (list_empty(&nx842_coprocs)) {
1041 for_each_compatible_node(dn, NULL, "ibm,power-nx")
1042 nx842_powernv_probe(dn);
1047 nx842_powernv_exec = nx842_exec_icswx;
1049 nx842_powernv_exec = nx842_exec_vas;
1050 nx842_powernv_alg.cra_init = nx842_powernv_crypto_init_vas;
1051 nx842_powernv_alg.cra_exit = nx842_powernv_crypto_exit_vas;
1054 ret = crypto_register_alg(&nx842_powernv_alg);
1056 nx842_delete_coprocs();
1062 module_init(nx842_powernv_init);
1064 static void __exit nx842_powernv_exit(void)
1066 crypto_unregister_alg(&nx842_powernv_alg);
1068 nx842_delete_coprocs();
1070 module_exit(nx842_powernv_exit);