2 * This file contains low level CPU setup functions.
3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cache.h>
18 #include <asm/book3s/64/mmu-hash.h>
20 /* Entry: r3 = crap, r4 = ptr to cputable entry
22 * Note that we can be called twice for pseudo-PVRs
24 _GLOBAL(__setup_cpu_power7)
33 li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
38 _GLOBAL(__restore_cpu_power7)
47 li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
52 _GLOBAL(__setup_cpu_power8)
64 ori r3, r3, LPCR_PECEDH
65 li r4,0 /* LPES = 0 */
69 bl __init_PMU_HV_ISA207
73 _GLOBAL(__restore_cpu_power8)
86 ori r3, r3, LPCR_PECEDH
87 li r4,0 /* LPES = 0 */
91 bl __init_PMU_HV_ISA207
95 _GLOBAL(__setup_cpu_power9)
108 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
110 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
112 li r4,0 /* LPES = 0 */
113 bl __init_LPCR_ISA300
119 _GLOBAL(__restore_cpu_power9)
133 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
135 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
137 li r4,0 /* LPES = 0 */
138 bl __init_LPCR_ISA300
145 /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
149 ld r5,CPU_SPEC_FEATURES(r4)
150 LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
152 std r5,CPU_SPEC_FEATURES(r4)
156 /* Setup a sane LPCR:
157 * Called with initial LPCR in R3 and desired LPES 2-bit value in R4
159 * LPES = 0b01 (HSRR0/1 used for 0x500)
163 * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
164 * VRMASD = 0b10000 (L=1, LP=00)
166 * Other bits untouched for now
169 rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
171 /* POWER9 has no VRMASD */
173 rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
174 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
176 rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
177 clrrdi r3,r3,1 /* clear HDICE */
179 rldimi r3,r5, LPCR_VC_SH, 0
186 ori r3,r3,FSCR_TAR|FSCR_EBB
192 ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
193 HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
202 __init_PMU_HV_ISA207: