2 * This file contains low level CPU setup functions.
3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cache.h>
19 #include <asm/feature-fixups.h>
21 _GLOBAL(__setup_cpu_603)
25 mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
26 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
28 bl __init_fpu_registers
29 END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
30 bl setup_common_caches
33 _GLOBAL(__setup_cpu_604)
35 bl setup_common_caches
39 _GLOBAL(__setup_cpu_750)
41 bl __init_fpu_registers
42 bl setup_common_caches
43 bl setup_750_7400_hid0
46 _GLOBAL(__setup_cpu_750cx)
48 bl __init_fpu_registers
49 bl setup_common_caches
50 bl setup_750_7400_hid0
54 _GLOBAL(__setup_cpu_750fx)
56 bl __init_fpu_registers
57 bl setup_common_caches
58 bl setup_750_7400_hid0
62 _GLOBAL(__setup_cpu_7400)
64 bl __init_fpu_registers
65 bl setup_7400_workarounds
66 bl setup_common_caches
67 bl setup_750_7400_hid0
70 _GLOBAL(__setup_cpu_7410)
72 bl __init_fpu_registers
73 bl setup_7410_workarounds
74 bl setup_common_caches
75 bl setup_750_7400_hid0
80 _GLOBAL(__setup_cpu_745x)
82 bl setup_common_caches
83 bl setup_745x_specifics
87 /* Enable caches for 603's, 604, 750 & 7400 */
91 ori r11,r11,HID0_ICE|HID0_DCE
93 bne 1f /* don't invalidate the D-cache */
94 ori r8,r8,HID0_DCI /* unless it wasn't enabled */
96 mtspr SPRN_HID0,r8 /* enable and invalidate caches */
98 mtspr SPRN_HID0,r11 /* enable caches */
103 /* 604, 604e, 604ev, ...
104 * Enable superscalar execution & branch history table
108 ori r11,r11,HID0_SIED|HID0_BHTE
111 mtspr SPRN_HID0,r8 /* flush branch target address cache */
112 sync /* on 604e/604r */
118 /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
119 * erratas we work around here.
120 * Moto MPC710CE.pdf describes them, those are errata
122 * Note that we assume the firmware didn't choose to
123 * apply other workarounds (there are other ones documented
124 * in the .pdf). It appear that Apple firmware only works
125 * around #3 and with the same fix we use. We may want to
126 * check if the CPU is using 60x bus mode in which case
127 * the workaround for errata #4 is useless. Also, we may
128 * want to explicitly clear HID0_NOPDST as this is not
129 * needed once we have applied workaround #5 (though it's
130 * not set by Apple's firmware at least).
132 setup_7400_workarounds:
138 setup_7410_workarounds:
144 mfspr r11,SPRN_MSSSR0
145 /* Errata #3: Set L1OPQ_SIZE to 0x10 */
148 /* Errata #4: Set L2MQ_SIZE to 1 (check for MPX mode first ?) */
150 /* Errata #5: Set DRLT_SIZE to 0x01 */
154 mtspr SPRN_MSSSR0,r11
160 * Enable Store Gathering (SGE), Address Broadcast (ABE),
161 * Branch History Table (BHTE), Branch Target ICache (BTIC)
162 * Dynamic Power Management (DPM), Speculative (SPD)
163 * Clear Instruction cache throttling (ICTC)
167 ori r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
168 oris r11,r11,HID0_DPM@h
170 xori r11,r11,HID0_BTIC
171 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
173 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
174 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
176 andc r11,r11,r3 /* clear SPD: enable speculative */
178 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
186 * Looks like we have to disable NAP feature for some PLL settings...
187 * (waiting for confirmation)
191 rlwinm r10,r10,4,28,31
195 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
196 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
198 lwz r6,CPU_SPEC_FEATURES(r4)
199 li r7,CPU_FTR_CAN_NAP
201 stw r6,CPU_SPEC_FEATURES(r4)
210 * Enable Store Gathering (SGE), Branch Folding (FOLD)
211 * Branch History Table (BHTE), Branch Target ICache (BTIC)
212 * Dynamic Power Management (DPM), Speculative (SPD)
213 * Ensure our data cache instructions really operate.
214 * Timebase has to be running or we wouldn't have made it here,
215 * just ensure we don't disable it.
216 * Clear Instruction cache throttling (ICTC)
217 * Enable L2 HW prefetch
219 setup_745x_specifics:
220 /* We check for the presence of an L3 cache setup by
221 * the firmware. If any, we disable NAP capability as
222 * it's known to be bogus on rev 2.1 and earlier
226 andis. r11,r11,L3CR_L3E@h
228 END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
229 lwz r6,CPU_SPEC_FEATURES(r4)
230 andis. r0,r6,CPU_FTR_L3_DISABLE_NAP@h
232 li r7,CPU_FTR_CAN_NAP
234 stw r6,CPU_SPEC_FEATURES(r4)
238 /* All of the bits we have to set.....
240 ori r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE
241 ori r11,r11,HID0_LRSTK | HID0_BTIC
242 oris r11,r11,HID0_DPM@h
243 BEGIN_MMU_FTR_SECTION
244 oris r11,r11,HID0_HIGH_BAT@h
245 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
247 xori r11,r11,HID0_BTIC
248 END_FTR_SECTION_IFSET(CPU_FTR_NO_BTIC)
250 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
251 END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
253 /* All of the bits we have to clear....
255 li r3,HID0_SPD | HID0_NOPDST | HID0_NOPTI
256 andc r11,r11,r3 /* clear SPD: enable speculative */
259 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
265 /* Enable L2 HW prefetch, if L2 is enabled
268 andis. r3,r3,L2CR_L2E@h
279 * Initialize the FPU registers. This is needed to work around an errata
280 * in some 750 cpus where using a not yet initialized FPU register after
281 * power on reset may hang the CPU
283 _GLOBAL(__init_fpu_registers)
288 addis r9,r3,empty_zero_page@ha
289 addi r9,r9,empty_zero_page@l
297 /* Definitions for the table use to save CPU states */
309 .balign L1_CACHE_BYTES
312 .balign L1_CACHE_BYTES,0
315 /* Called in normal context to backup CPU 0 state. This
316 * does not include cache settings. This function is also
317 * called for machine sleep. This does not include the MMU
318 * setup, BATs, etc... but rather the "special" registers
319 * like HID0, HID1, MSSCR0, etc...
321 _GLOBAL(__save_cpu_setup)
322 /* Some CR fields are volatile, we back it up all */
325 /* Get storage ptr */
326 lis r5,cpu_state_storage@h
327 ori r5,r5,cpu_state_storage@l
329 /* Save HID0 (common to all CONFIG_6xx cpus) */
333 /* Now deal with CPU type dependent registers */
336 cmplwi cr0,r3,0x8000 /* 7450 */
337 cmplwi cr1,r3,0x000c /* 7400 */
338 cmplwi cr2,r3,0x800c /* 7410 */
339 cmplwi cr3,r3,0x8001 /* 7455 */
340 cmplwi cr4,r3,0x8002 /* 7457 */
341 cmplwi cr5,r3,0x8003 /* 7447A */
342 cmplwi cr6,r3,0x7000 /* 750FX */
343 cmplwi cr7,r3,0x8004 /* 7448 */
344 /* cr1 is 7400 || 7410 */
345 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
347 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
348 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
349 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
350 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
351 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
353 /* Backup 74xx specific regs */
359 /* Backup 745x specific registers */
370 /* Backup 750FX specific registers */
373 /* If rev 2.x, backup HID2 */
384 /* Called with no MMU context (typically MSR:IR/DR off) to
385 * restore CPU state as backed up by the previous
386 * function. This does not include cache setting
388 _GLOBAL(__restore_cpu_setup)
389 /* Some CR fields are volatile, we back it up all */
392 /* Get storage ptr */
393 lis r5,(cpu_state_storage-KERNELBASE)@h
394 ori r5,r5,cpu_state_storage@l
404 /* Now deal with CPU type dependent registers */
407 cmplwi cr0,r3,0x8000 /* 7450 */
408 cmplwi cr1,r3,0x000c /* 7400 */
409 cmplwi cr2,r3,0x800c /* 7410 */
410 cmplwi cr3,r3,0x8001 /* 7455 */
411 cmplwi cr4,r3,0x8002 /* 7457 */
412 cmplwi cr5,r3,0x8003 /* 7447A */
413 cmplwi cr6,r3,0x7000 /* 750FX */
414 cmplwi cr7,r3,0x8004 /* 7448 */
415 /* cr1 is 7400 || 7410 */
416 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
418 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
419 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
420 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
421 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
422 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
424 /* Restore 74xx specific regs */
436 /* Clear 7410 L2CR2 */
440 /* Restore 745x specific registers */
462 /* Restore 750FX specific registers
463 * that is restore HID2 on rev 2.x and PLL config & switch
466 /* If rev 2.x, restore HID2 with low voltage bit cleared */
479 /* Wait for PLL to stabilize */
485 /* Setup final PLL */