2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/percpu-defs.h>
39 #include <linux/perf_event.h>
41 #include <asm/branch.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <linux/uaccess.h>
47 #include <asm/cpu-info.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
51 #include <asm/mips-r2-to-r6-emul.h>
55 /* Function which emulates a floating point instruction. */
57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
60 static int fpux_emu(struct pt_regs *,
61 struct mips_fpu_struct *, mips_instruction, void __user **);
63 /* Control registers */
65 #define FPCREG_RID 0 /* $0 = revision id */
66 #define FPCREG_FCCR 25 /* $25 = fccr */
67 #define FPCREG_FEXR 26 /* $26 = fexr */
68 #define FPCREG_FENR 28 /* $28 = fenr */
69 #define FPCREG_CSR 31 /* $31 = csr */
71 /* convert condition code register number to csr bit */
72 const unsigned int fpucondbit[8] = {
83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
84 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
85 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
86 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
87 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
90 * This functions translates a 32-bit microMIPS instruction
91 * into a 32-bit MIPS32 instruction. Returns 0 on success
92 * and SIGILL otherwise.
94 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 union mips_instruction insn = *insn_ptr;
97 union mips_instruction mips32_insn = insn;
100 switch (insn.mm_i_format.opcode) {
102 mips32_insn.mm_i_format.opcode = ldc1_op;
103 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
104 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
107 mips32_insn.mm_i_format.opcode = lwc1_op;
108 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
109 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
112 mips32_insn.mm_i_format.opcode = sdc1_op;
113 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
114 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
117 mips32_insn.mm_i_format.opcode = swc1_op;
118 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
119 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
122 /* NOTE: offset is << by 1 if in microMIPS mode. */
123 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
124 (insn.mm_i_format.rt == mm_bc1t_op)) {
125 mips32_insn.fb_format.opcode = cop1_op;
126 mips32_insn.fb_format.bc = bc_op;
127 mips32_insn.fb_format.flag =
128 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
133 switch (insn.mm_fp0_format.func) {
142 op = insn.mm_fp0_format.func;
143 if (op == mm_32f_01_op)
145 else if (op == mm_32f_11_op)
147 else if (op == mm_32f_02_op)
149 else if (op == mm_32f_12_op)
151 else if (op == mm_32f_41_op)
153 else if (op == mm_32f_51_op)
155 else if (op == mm_32f_42_op)
159 mips32_insn.fp6_format.opcode = cop1x_op;
160 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
161 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
162 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
163 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
164 mips32_insn.fp6_format.func = func;
167 func = -1; /* Invalid */
168 op = insn.mm_fp5_format.op & 0x7;
169 if (op == mm_ldxc1_op)
171 else if (op == mm_sdxc1_op)
173 else if (op == mm_lwxc1_op)
175 else if (op == mm_swxc1_op)
179 mips32_insn.r_format.opcode = cop1x_op;
180 mips32_insn.r_format.rs =
181 insn.mm_fp5_format.base;
182 mips32_insn.r_format.rt =
183 insn.mm_fp5_format.index;
184 mips32_insn.r_format.rd = 0;
185 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
186 mips32_insn.r_format.func = func;
191 op = -1; /* Invalid */
192 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 else if (insn.mm_fp2_format.op == mm_fmovf_op)
197 mips32_insn.fp0_format.opcode = cop1_op;
198 mips32_insn.fp0_format.fmt =
199 sdps_format[insn.mm_fp2_format.fmt];
200 mips32_insn.fp0_format.ft =
201 (insn.mm_fp2_format.cc<<2) + op;
202 mips32_insn.fp0_format.fs =
203 insn.mm_fp2_format.fs;
204 mips32_insn.fp0_format.fd =
205 insn.mm_fp2_format.fd;
206 mips32_insn.fp0_format.func = fmovc_op;
211 func = -1; /* Invalid */
212 if (insn.mm_fp0_format.op == mm_fadd_op)
214 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 else if (insn.mm_fp0_format.op == mm_fdiv_op)
221 mips32_insn.fp0_format.opcode = cop1_op;
222 mips32_insn.fp0_format.fmt =
223 sdps_format[insn.mm_fp0_format.fmt];
224 mips32_insn.fp0_format.ft =
225 insn.mm_fp0_format.ft;
226 mips32_insn.fp0_format.fs =
227 insn.mm_fp0_format.fs;
228 mips32_insn.fp0_format.fd =
229 insn.mm_fp0_format.fd;
230 mips32_insn.fp0_format.func = func;
235 func = -1; /* Invalid */
236 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 else if (insn.mm_fp0_format.op == mm_fmovz_op)
241 mips32_insn.fp0_format.opcode = cop1_op;
242 mips32_insn.fp0_format.fmt =
243 sdps_format[insn.mm_fp0_format.fmt];
244 mips32_insn.fp0_format.ft =
245 insn.mm_fp0_format.ft;
246 mips32_insn.fp0_format.fs =
247 insn.mm_fp0_format.fs;
248 mips32_insn.fp0_format.fd =
249 insn.mm_fp0_format.fd;
250 mips32_insn.fp0_format.func = func;
254 case mm_32f_73_op: /* POOL32FXF */
255 switch (insn.mm_fp1_format.op) {
260 if ((insn.mm_fp1_format.op & 0x7f) ==
265 mips32_insn.r_format.opcode = spec_op;
266 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
267 mips32_insn.r_format.rt =
268 (insn.mm_fp4_format.cc << 2) + op;
269 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
270 mips32_insn.r_format.re = 0;
271 mips32_insn.r_format.func = movc_op;
277 if ((insn.mm_fp1_format.op & 0x7f) ==
280 fmt = swl_format[insn.mm_fp3_format.fmt];
283 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 mips32_insn.fp0_format.opcode = cop1_op;
286 mips32_insn.fp0_format.fmt = fmt;
287 mips32_insn.fp0_format.ft = 0;
288 mips32_insn.fp0_format.fs =
289 insn.mm_fp3_format.fs;
290 mips32_insn.fp0_format.fd =
291 insn.mm_fp3_format.rt;
292 mips32_insn.fp0_format.func = func;
300 if ((insn.mm_fp1_format.op & 0x7f) ==
303 else if ((insn.mm_fp1_format.op & 0x7f) ==
308 mips32_insn.fp0_format.opcode = cop1_op;
309 mips32_insn.fp0_format.fmt =
310 sdps_format[insn.mm_fp3_format.fmt];
311 mips32_insn.fp0_format.ft = 0;
312 mips32_insn.fp0_format.fs =
313 insn.mm_fp3_format.fs;
314 mips32_insn.fp0_format.fd =
315 insn.mm_fp3_format.rt;
316 mips32_insn.fp0_format.func = func;
328 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
348 mips32_insn.fp0_format.opcode = cop1_op;
349 mips32_insn.fp0_format.fmt =
350 sd_format[insn.mm_fp1_format.fmt];
351 mips32_insn.fp0_format.ft = 0;
352 mips32_insn.fp0_format.fs =
353 insn.mm_fp1_format.fs;
354 mips32_insn.fp0_format.fd =
355 insn.mm_fp1_format.rt;
356 mips32_insn.fp0_format.func = func;
361 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
367 mips32_insn.fp0_format.opcode = cop1_op;
368 mips32_insn.fp0_format.fmt =
369 sdps_format[insn.mm_fp1_format.fmt];
370 mips32_insn.fp0_format.ft = 0;
371 mips32_insn.fp0_format.fs =
372 insn.mm_fp1_format.fs;
373 mips32_insn.fp0_format.fd =
374 insn.mm_fp1_format.rt;
375 mips32_insn.fp0_format.func = func;
383 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
395 mips32_insn.fp1_format.opcode = cop1_op;
396 mips32_insn.fp1_format.op = op;
397 mips32_insn.fp1_format.rt =
398 insn.mm_fp1_format.rt;
399 mips32_insn.fp1_format.fs =
400 insn.mm_fp1_format.fs;
401 mips32_insn.fp1_format.fd = 0;
402 mips32_insn.fp1_format.func = 0;
408 case mm_32f_74_op: /* c.cond.fmt */
409 mips32_insn.fp0_format.opcode = cop1_op;
410 mips32_insn.fp0_format.fmt =
411 sdps_format[insn.mm_fp4_format.fmt];
412 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
413 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
414 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
415 mips32_insn.fp0_format.func =
416 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
426 *insn_ptr = mips32_insn;
431 * Redundant with logic already in kernel/branch.c,
432 * embedded in compute_return_epc. At some point,
433 * a single subroutine should be used across both
436 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
437 unsigned long *contpc)
439 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int bit = 0;
445 switch (insn.i_format.opcode) {
447 switch (insn.r_format.func) {
449 if (insn.r_format.rd != 0) {
450 regs->regs[insn.r_format.rd] =
451 regs->cp0_epc + dec_insn.pc_inc +
452 dec_insn.next_pc_inc;
456 /* For R6, JR already emulated in jalr_op */
457 if (NO_R6EMU && insn.r_format.func == jr_op)
459 *contpc = regs->regs[insn.r_format.rs];
464 switch (insn.i_format.rt) {
467 if (NO_R6EMU && (insn.i_format.rs ||
468 insn.i_format.rt == bltzall_op))
471 regs->regs[31] = regs->cp0_epc +
473 dec_insn.next_pc_inc;
479 if ((long)regs->regs[insn.i_format.rs] < 0)
480 *contpc = regs->cp0_epc +
482 (insn.i_format.simmediate << 2);
484 *contpc = regs->cp0_epc +
486 dec_insn.next_pc_inc;
490 if (NO_R6EMU && (insn.i_format.rs ||
491 insn.i_format.rt == bgezall_op))
494 regs->regs[31] = regs->cp0_epc +
496 dec_insn.next_pc_inc;
502 if ((long)regs->regs[insn.i_format.rs] >= 0)
503 *contpc = regs->cp0_epc +
505 (insn.i_format.simmediate << 2);
507 *contpc = regs->cp0_epc +
509 dec_insn.next_pc_inc;
516 regs->regs[31] = regs->cp0_epc +
518 dec_insn.next_pc_inc;
521 *contpc = regs->cp0_epc + dec_insn.pc_inc;
524 *contpc |= (insn.j_format.target << 2);
525 /* Set microMIPS mode bit: XOR for jalx. */
532 if (regs->regs[insn.i_format.rs] ==
533 regs->regs[insn.i_format.rt])
534 *contpc = regs->cp0_epc +
536 (insn.i_format.simmediate << 2);
538 *contpc = regs->cp0_epc +
540 dec_insn.next_pc_inc;
546 if (regs->regs[insn.i_format.rs] !=
547 regs->regs[insn.i_format.rt])
548 *contpc = regs->cp0_epc +
550 (insn.i_format.simmediate << 2);
552 *contpc = regs->cp0_epc +
554 dec_insn.next_pc_inc;
557 if (!insn.i_format.rt && NO_R6EMU)
562 * Compact branches for R6 for the
563 * blez and blezl opcodes.
564 * BLEZ | rs = 0 | rt != 0 == BLEZALC
565 * BLEZ | rs = rt != 0 == BGEZALC
566 * BLEZ | rs != 0 | rt != 0 == BGEUC
567 * BLEZL | rs = 0 | rt != 0 == BLEZC
568 * BLEZL | rs = rt != 0 == BGEZC
569 * BLEZL | rs != 0 | rt != 0 == BGEC
571 * For real BLEZ{,L}, rt is always 0.
573 if (cpu_has_mips_r6 && insn.i_format.rt) {
574 if ((insn.i_format.opcode == blez_op) &&
575 ((!insn.i_format.rs && insn.i_format.rt) ||
576 (insn.i_format.rs == insn.i_format.rt)))
577 regs->regs[31] = regs->cp0_epc +
579 *contpc = regs->cp0_epc + dec_insn.pc_inc +
580 dec_insn.next_pc_inc;
584 if ((long)regs->regs[insn.i_format.rs] <= 0)
585 *contpc = regs->cp0_epc +
587 (insn.i_format.simmediate << 2);
589 *contpc = regs->cp0_epc +
591 dec_insn.next_pc_inc;
594 if (!insn.i_format.rt && NO_R6EMU)
598 * Compact branches for R6 for the
599 * bgtz and bgtzl opcodes.
600 * BGTZ | rs = 0 | rt != 0 == BGTZALC
601 * BGTZ | rs = rt != 0 == BLTZALC
602 * BGTZ | rs != 0 | rt != 0 == BLTUC
603 * BGTZL | rs = 0 | rt != 0 == BGTZC
604 * BGTZL | rs = rt != 0 == BLTZC
605 * BGTZL | rs != 0 | rt != 0 == BLTC
607 * *ZALC varint for BGTZ &&& rt != 0
608 * For real GTZ{,L}, rt is always 0.
610 if (cpu_has_mips_r6 && insn.i_format.rt) {
611 if ((insn.i_format.opcode == blez_op) &&
612 ((!insn.i_format.rs && insn.i_format.rt) ||
613 (insn.i_format.rs == insn.i_format.rt)))
614 regs->regs[31] = regs->cp0_epc +
616 *contpc = regs->cp0_epc + dec_insn.pc_inc +
617 dec_insn.next_pc_inc;
622 if ((long)regs->regs[insn.i_format.rs] > 0)
623 *contpc = regs->cp0_epc +
625 (insn.i_format.simmediate << 2);
627 *contpc = regs->cp0_epc +
629 dec_insn.next_pc_inc;
633 if (!cpu_has_mips_r6)
635 if (insn.i_format.rt && !insn.i_format.rs)
636 regs->regs[31] = regs->cp0_epc + 4;
637 *contpc = regs->cp0_epc + dec_insn.pc_inc +
638 dec_insn.next_pc_inc;
641 #ifdef CONFIG_CPU_CAVIUM_OCTEON
642 case lwc2_op: /* This is bbit0 on Octeon */
643 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
644 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
646 *contpc = regs->cp0_epc + 8;
648 case ldc2_op: /* This is bbit032 on Octeon */
649 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
650 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
652 *contpc = regs->cp0_epc + 8;
654 case swc2_op: /* This is bbit1 on Octeon */
655 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
656 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
658 *contpc = regs->cp0_epc + 8;
660 case sdc2_op: /* This is bbit132 on Octeon */
661 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
662 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
664 *contpc = regs->cp0_epc + 8;
669 * Only valid for MIPS R6 but we can still end up
670 * here from a broken userland so just tell emulator
671 * this is not a branch and let it break later on.
673 if (!cpu_has_mips_r6)
675 *contpc = regs->cp0_epc + dec_insn.pc_inc +
676 dec_insn.next_pc_inc;
680 if (!cpu_has_mips_r6)
682 regs->regs[31] = regs->cp0_epc + 4;
683 *contpc = regs->cp0_epc + dec_insn.pc_inc +
684 dec_insn.next_pc_inc;
688 if (!cpu_has_mips_r6)
690 *contpc = regs->cp0_epc + dec_insn.pc_inc +
691 dec_insn.next_pc_inc;
695 if (!cpu_has_mips_r6)
697 if (!insn.i_format.rs)
698 regs->regs[31] = regs->cp0_epc + 4;
699 *contpc = regs->cp0_epc + dec_insn.pc_inc +
700 dec_insn.next_pc_inc;
706 /* Need to check for R6 bc1nez and bc1eqz branches */
707 if (cpu_has_mips_r6 &&
708 ((insn.i_format.rs == bc1eqz_op) ||
709 (insn.i_format.rs == bc1nez_op))) {
711 fpr = ¤t->thread.fpu.fpr[insn.i_format.rt];
712 bit0 = get_fpr32(fpr, 0) & 0x1;
713 switch (insn.i_format.rs) {
722 *contpc = regs->cp0_epc +
724 (insn.i_format.simmediate << 2);
726 *contpc = regs->cp0_epc +
728 dec_insn.next_pc_inc;
732 /* R2/R6 compatible cop1 instruction. Fall through */
735 if (insn.i_format.rs == bc_op) {
738 fcr31 = read_32bit_cp1_register(CP1_STATUS);
740 fcr31 = current->thread.fpu.fcr31;
743 bit = (insn.i_format.rt >> 2);
746 switch (insn.i_format.rt & 3) {
749 if (~fcr31 & (1 << bit))
750 *contpc = regs->cp0_epc +
752 (insn.i_format.simmediate << 2);
754 *contpc = regs->cp0_epc +
756 dec_insn.next_pc_inc;
760 if (fcr31 & (1 << bit))
761 *contpc = regs->cp0_epc +
763 (insn.i_format.simmediate << 2);
765 *contpc = regs->cp0_epc +
767 dec_insn.next_pc_inc;
777 * In the Linux kernel, we support selection of FPR format on the
778 * basis of the Status.FR bit. If an FPU is not present, the FR bit
779 * is hardwired to zero, which would imply a 32-bit FPU even for
780 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
781 * FPU emu is slow and bulky and optimizing this function offers fairly
782 * sizeable benefits so we try to be clever and make this function return
783 * a constant whenever possible, that is on 64-bit kernels without O32
784 * compatibility enabled and on 32-bit without 64-bit FPU support.
786 static inline int cop1_64bit(struct pt_regs *xcp)
788 if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32))
790 else if (IS_ENABLED(CONFIG_32BIT) &&
791 !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
794 return !test_thread_flag(TIF_32BIT_FPREGS);
797 static inline bool hybrid_fprs(void)
799 return test_thread_flag(TIF_HYBRID_FPREGS);
802 #define SIFROMREG(si, x) \
804 if (cop1_64bit(xcp) && !hybrid_fprs()) \
805 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
807 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
810 #define SITOREG(si, x) \
812 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
814 set_fpr32(&ctx->fpr[x], 0, si); \
815 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
816 set_fpr32(&ctx->fpr[x], i, 0); \
818 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
822 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
824 #define SITOHREG(si, x) \
827 set_fpr32(&ctx->fpr[x], 1, si); \
828 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
829 set_fpr32(&ctx->fpr[x], i, 0); \
832 #define DIFROMREG(di, x) \
833 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) ^ 1)], 0))
835 #define DITOREG(di, x) \
838 fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \
839 set_fpr64(&ctx->fpr[fpr], 0, di); \
840 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
841 set_fpr64(&ctx->fpr[fpr], i, 0); \
844 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
845 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
846 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
847 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
850 * Emulate a CFC1 instruction.
852 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
855 u32 fcr31 = ctx->fcr31;
858 switch (MIPSInst_RD(ir)) {
861 pr_debug("%p gpr[%d]<-csr=%08x\n",
862 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
868 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
870 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
871 pr_debug("%p gpr[%d]<-enr=%08x\n",
872 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
878 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
879 pr_debug("%p gpr[%d]<-exr=%08x\n",
880 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
886 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
888 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
889 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
890 pr_debug("%p gpr[%d]<-ccr=%08x\n",
891 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
895 value = boot_cpu_data.fpu_id;
903 xcp->regs[MIPSInst_RT(ir)] = value;
907 * Emulate a CTC1 instruction.
909 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
912 u32 fcr31 = ctx->fcr31;
916 if (MIPSInst_RT(ir) == 0)
919 value = xcp->regs[MIPSInst_RT(ir)];
921 switch (MIPSInst_RD(ir)) {
923 pr_debug("%p gpr[%d]->csr=%08x\n",
924 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
926 /* Preserve read-only bits. */
927 mask = boot_cpu_data.fpu_msk31;
928 fcr31 = (value & ~mask) | (fcr31 & mask);
934 pr_debug("%p gpr[%d]->enr=%08x\n",
935 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
936 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
937 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
939 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
945 pr_debug("%p gpr[%d]->exr=%08x\n",
946 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
947 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
948 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
954 pr_debug("%p gpr[%d]->ccr=%08x\n",
955 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
956 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
957 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
959 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
971 * Emulate the single floating point instruction pointed at by EPC.
972 * Two instructions if the instruction is in a branch delay slot.
975 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
976 struct mm_decoded_insn dec_insn, void __user **fault_addr)
978 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
979 unsigned int cond, cbit, bit0;
990 * These are giving gcc a gentle hint about what to expect in
991 * dec_inst in order to do better optimization.
993 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
996 /* XXX NEC Vr54xx bug workaround */
997 if (delay_slot(xcp)) {
998 if (dec_insn.micro_mips_mode) {
999 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
1000 clear_delay_slot(xcp);
1002 if (!isBranchInstr(xcp, dec_insn, &contpc))
1003 clear_delay_slot(xcp);
1007 if (delay_slot(xcp)) {
1009 * The instruction to be emulated is in a branch delay slot
1010 * which means that we have to emulate the branch instruction
1011 * BEFORE we do the cop1 instruction.
1013 * This branch could be a COP1 branch, but in that case we
1014 * would have had a trap for that instruction, and would not
1015 * come through this route.
1017 * Linux MIPS branch emulator operates on context, updating the
1020 ir = dec_insn.next_insn; /* process delay slot instr */
1021 pc_inc = dec_insn.next_pc_inc;
1023 ir = dec_insn.insn; /* process current instr */
1024 pc_inc = dec_insn.pc_inc;
1028 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1029 * instructions, we want to convert microMIPS FPU instructions
1030 * into MIPS32 instructions so that we could reuse all of the
1031 * FPU emulation code.
1033 * NOTE: We cannot do this for branch instructions since they
1034 * are not a subset. Example: Cannot emulate a 16-bit
1035 * aligned target address with a MIPS32 instruction.
1037 if (dec_insn.micro_mips_mode) {
1039 * If next instruction is a 16-bit instruction, then it
1040 * it cannot be a FPU instruction. This could happen
1041 * since we can be called for non-FPU instructions.
1043 if ((pc_inc == 2) ||
1044 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1050 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1051 MIPS_FPU_EMU_INC_STATS(emulated);
1052 switch (MIPSInst_OPCODE(ir)) {
1054 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1056 MIPS_FPU_EMU_INC_STATS(loads);
1058 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1059 MIPS_FPU_EMU_INC_STATS(errors);
1063 if (__get_user(dval, dva)) {
1064 MIPS_FPU_EMU_INC_STATS(errors);
1068 DITOREG(dval, MIPSInst_RT(ir));
1072 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1074 MIPS_FPU_EMU_INC_STATS(stores);
1075 DIFROMREG(dval, MIPSInst_RT(ir));
1076 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1077 MIPS_FPU_EMU_INC_STATS(errors);
1081 if (__put_user(dval, dva)) {
1082 MIPS_FPU_EMU_INC_STATS(errors);
1089 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1091 MIPS_FPU_EMU_INC_STATS(loads);
1092 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1093 MIPS_FPU_EMU_INC_STATS(errors);
1097 if (__get_user(wval, wva)) {
1098 MIPS_FPU_EMU_INC_STATS(errors);
1102 SITOREG(wval, MIPSInst_RT(ir));
1106 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1108 MIPS_FPU_EMU_INC_STATS(stores);
1109 SIFROMREG(wval, MIPSInst_RT(ir));
1110 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1111 MIPS_FPU_EMU_INC_STATS(errors);
1115 if (__put_user(wval, wva)) {
1116 MIPS_FPU_EMU_INC_STATS(errors);
1123 switch (MIPSInst_RS(ir)) {
1125 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1128 /* copregister fs -> gpr[rt] */
1129 if (MIPSInst_RT(ir) != 0) {
1130 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1136 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1139 /* copregister fs <- rt */
1140 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1144 if (!cpu_has_mips_r2_r6)
1147 /* copregister rd -> gpr[rt] */
1148 if (MIPSInst_RT(ir) != 0) {
1149 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1155 if (!cpu_has_mips_r2_r6)
1158 /* copregister rd <- gpr[rt] */
1159 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1163 /* copregister rd -> gpr[rt] */
1164 if (MIPSInst_RT(ir) != 0) {
1165 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1171 /* copregister rd <- rt */
1172 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1176 /* cop control register rd -> gpr[rt] */
1177 cop1_cfc(xcp, ctx, ir);
1181 /* copregister rd <- rt */
1182 cop1_ctc(xcp, ctx, ir);
1183 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1190 if (!cpu_has_mips_r6 || delay_slot(xcp))
1194 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
1195 bit0 = get_fpr32(fpr, 0) & 0x1;
1196 switch (MIPSInst_RS(ir)) {
1198 MIPS_FPU_EMU_INC_STATS(bc1eqz);
1202 MIPS_FPU_EMU_INC_STATS(bc1nez);
1209 if (delay_slot(xcp))
1212 if (cpu_has_mips_4_5_r)
1213 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1215 cbit = FPU_CSR_COND;
1216 cond = ctx->fcr31 & cbit;
1219 switch (MIPSInst_RT(ir) & 3) {
1221 if (cpu_has_mips_2_3_4_5_r)
1228 if (cpu_has_mips_2_3_4_5_r)
1235 MIPS_FPU_EMU_INC_STATS(branches);
1236 set_delay_slot(xcp);
1239 * Branch taken: emulate dslot instruction
1244 * Remember EPC at the branch to point back
1245 * at so that any delay-slot instruction
1246 * signal is not silently ignored.
1248 bcpc = xcp->cp0_epc;
1249 xcp->cp0_epc += dec_insn.pc_inc;
1251 contpc = MIPSInst_SIMM(ir);
1252 ir = dec_insn.next_insn;
1253 if (dec_insn.micro_mips_mode) {
1254 contpc = (xcp->cp0_epc + (contpc << 1));
1256 /* If 16-bit instruction, not FPU. */
1257 if ((dec_insn.next_pc_inc == 2) ||
1258 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1261 * Since this instruction will
1262 * be put on the stack with
1263 * 32-bit words, get around
1264 * this problem by putting a
1265 * NOP16 as the second one.
1267 if (dec_insn.next_pc_inc == 2)
1268 ir = (ir & (~0xffff)) | MM_NOP16;
1271 * Single step the non-CP1
1272 * instruction in the dslot.
1274 sig = mips_dsemul(xcp, ir,
1279 xcp->cp0_epc = bcpc;
1281 * SIGILL forces out of
1282 * the emulation loop.
1284 return sig ? sig : SIGILL;
1287 contpc = (xcp->cp0_epc + (contpc << 2));
1289 switch (MIPSInst_OPCODE(ir)) {
1296 if (cpu_has_mips_2_3_4_5_r)
1305 if (cpu_has_mips_4_5_64_r2_r6)
1306 /* its one of ours */
1312 switch (MIPSInst_FUNC(ir)) {
1314 if (cpu_has_mips_4_5_r)
1322 xcp->cp0_epc = bcpc;
1327 * Single step the non-cp1
1328 * instruction in the dslot
1330 sig = mips_dsemul(xcp, ir, bcpc, contpc);
1334 xcp->cp0_epc = bcpc;
1335 /* SIGILL forces out of the emulation loop. */
1336 return sig ? sig : SIGILL;
1337 } else if (likely) { /* branch not taken */
1339 * branch likely nullifies
1340 * dslot if not taken
1342 xcp->cp0_epc += dec_insn.pc_inc;
1343 contpc += dec_insn.pc_inc;
1345 * else continue & execute
1346 * dslot as normal insn
1352 if (!(MIPSInst_RS(ir) & 0x10))
1355 /* a real fpu computation instruction */
1356 if ((sig = fpu_emu(xcp, ctx, ir)))
1362 if (!cpu_has_mips_4_5_64_r2_r6)
1365 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1371 if (!cpu_has_mips_4_5_r)
1374 if (MIPSInst_FUNC(ir) != movc_op)
1376 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1377 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1378 xcp->regs[MIPSInst_RD(ir)] =
1379 xcp->regs[MIPSInst_RS(ir)];
1386 xcp->cp0_epc = contpc;
1387 clear_delay_slot(xcp);
1393 * Conversion table from MIPS compare ops 48-63
1394 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1396 static const unsigned char cmptab[8] = {
1397 0, /* cmp_0 (sig) cmp_sf */
1398 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1399 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1400 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1401 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1402 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1403 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1404 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1407 static const unsigned char negative_cmptab[8] = {
1409 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1410 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1411 IEEE754_CLT | IEEE754_CGT,
1417 * Additional MIPS4 instructions
1420 #define DEF3OP(name, p, f1, f2, f3) \
1421 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1422 union ieee754##p s, union ieee754##p t) \
1424 struct _ieee754_csr ieee754_csr_save; \
1426 ieee754_csr_save = ieee754_csr; \
1428 ieee754_csr_save.cx |= ieee754_csr.cx; \
1429 ieee754_csr_save.sx |= ieee754_csr.sx; \
1431 ieee754_csr.cx |= ieee754_csr_save.cx; \
1432 ieee754_csr.sx |= ieee754_csr_save.sx; \
1436 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1438 return ieee754dp_div(ieee754dp_one(0), d);
1441 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1443 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1446 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1448 return ieee754sp_div(ieee754sp_one(0), s);
1451 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1453 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1456 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1457 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1458 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1459 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1460 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1461 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1462 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1463 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1465 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1466 mips_instruction ir, void __user **fault_addr)
1468 unsigned rcsr = 0; /* resulting csr */
1470 MIPS_FPU_EMU_INC_STATS(cp1xops);
1472 switch (MIPSInst_FMA_FFMT(ir)) {
1473 case s_fmt:{ /* 0 */
1475 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1476 union ieee754sp fd, fr, fs, ft;
1480 switch (MIPSInst_FUNC(ir)) {
1482 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1483 xcp->regs[MIPSInst_FT(ir)]);
1485 MIPS_FPU_EMU_INC_STATS(loads);
1486 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1487 MIPS_FPU_EMU_INC_STATS(errors);
1491 if (__get_user(val, va)) {
1492 MIPS_FPU_EMU_INC_STATS(errors);
1496 SITOREG(val, MIPSInst_FD(ir));
1500 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1501 xcp->regs[MIPSInst_FT(ir)]);
1503 MIPS_FPU_EMU_INC_STATS(stores);
1505 SIFROMREG(val, MIPSInst_FS(ir));
1506 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1507 MIPS_FPU_EMU_INC_STATS(errors);
1511 if (put_user(val, va)) {
1512 MIPS_FPU_EMU_INC_STATS(errors);
1519 handler = fpemu_sp_madd;
1522 handler = fpemu_sp_msub;
1525 handler = fpemu_sp_nmadd;
1528 handler = fpemu_sp_nmsub;
1532 SPFROMREG(fr, MIPSInst_FR(ir));
1533 SPFROMREG(fs, MIPSInst_FS(ir));
1534 SPFROMREG(ft, MIPSInst_FT(ir));
1535 fd = (*handler) (fr, fs, ft);
1536 SPTOREG(fd, MIPSInst_FD(ir));
1539 if (ieee754_cxtest(IEEE754_INEXACT)) {
1540 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1541 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1543 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1544 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1545 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1547 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1548 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1549 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1551 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1552 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1553 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1556 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1557 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1558 /*printk ("SIGFPE: FPU csr = %08x\n",
1571 case d_fmt:{ /* 1 */
1572 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1573 union ieee754dp fd, fr, fs, ft;
1577 switch (MIPSInst_FUNC(ir)) {
1579 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1580 xcp->regs[MIPSInst_FT(ir)]);
1582 MIPS_FPU_EMU_INC_STATS(loads);
1583 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1584 MIPS_FPU_EMU_INC_STATS(errors);
1588 if (__get_user(val, va)) {
1589 MIPS_FPU_EMU_INC_STATS(errors);
1593 DITOREG(val, MIPSInst_FD(ir));
1597 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1598 xcp->regs[MIPSInst_FT(ir)]);
1600 MIPS_FPU_EMU_INC_STATS(stores);
1601 DIFROMREG(val, MIPSInst_FS(ir));
1602 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1603 MIPS_FPU_EMU_INC_STATS(errors);
1607 if (__put_user(val, va)) {
1608 MIPS_FPU_EMU_INC_STATS(errors);
1615 handler = fpemu_dp_madd;
1618 handler = fpemu_dp_msub;
1621 handler = fpemu_dp_nmadd;
1624 handler = fpemu_dp_nmsub;
1628 DPFROMREG(fr, MIPSInst_FR(ir));
1629 DPFROMREG(fs, MIPSInst_FS(ir));
1630 DPFROMREG(ft, MIPSInst_FT(ir));
1631 fd = (*handler) (fr, fs, ft);
1632 DPTOREG(fd, MIPSInst_FD(ir));
1642 if (MIPSInst_FUNC(ir) != pfetch_op)
1645 /* ignore prefx operation */
1658 * Emulate a single COP1 arithmetic instruction.
1660 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1661 mips_instruction ir)
1663 int rfmt; /* resulting format */
1664 unsigned rcsr = 0; /* resulting csr */
1673 } rv; /* resulting value */
1676 MIPS_FPU_EMU_INC_STATS(cp1ops);
1677 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1678 case s_fmt: { /* 0 */
1680 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1681 union ieee754sp(*u) (union ieee754sp);
1683 union ieee754sp fd, fs, ft;
1685 switch (MIPSInst_FUNC(ir)) {
1688 MIPS_FPU_EMU_INC_STATS(add_s);
1689 handler.b = ieee754sp_add;
1692 MIPS_FPU_EMU_INC_STATS(sub_s);
1693 handler.b = ieee754sp_sub;
1696 MIPS_FPU_EMU_INC_STATS(mul_s);
1697 handler.b = ieee754sp_mul;
1700 MIPS_FPU_EMU_INC_STATS(div_s);
1701 handler.b = ieee754sp_div;
1706 if (!cpu_has_mips_2_3_4_5_r)
1709 MIPS_FPU_EMU_INC_STATS(sqrt_s);
1710 handler.u = ieee754sp_sqrt;
1714 * Note that on some MIPS IV implementations such as the
1715 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1716 * achieve full IEEE-754 accuracy - however this emulator does.
1719 if (!cpu_has_mips_4_5_64_r2_r6)
1722 MIPS_FPU_EMU_INC_STATS(rsqrt_s);
1723 handler.u = fpemu_sp_rsqrt;
1727 if (!cpu_has_mips_4_5_64_r2_r6)
1730 MIPS_FPU_EMU_INC_STATS(recip_s);
1731 handler.u = fpemu_sp_recip;
1735 if (!cpu_has_mips_4_5_r)
1738 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1739 if (((ctx->fcr31 & cond) != 0) !=
1740 ((MIPSInst_FT(ir) & 1) != 0))
1742 SPFROMREG(rv.s, MIPSInst_FS(ir));
1746 if (!cpu_has_mips_4_5_r)
1749 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1751 SPFROMREG(rv.s, MIPSInst_FS(ir));
1755 if (!cpu_has_mips_4_5_r)
1758 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1760 SPFROMREG(rv.s, MIPSInst_FS(ir));
1764 if (!cpu_has_mips_r6)
1767 MIPS_FPU_EMU_INC_STATS(seleqz_s);
1768 SPFROMREG(rv.s, MIPSInst_FT(ir));
1772 SPFROMREG(rv.s, MIPSInst_FS(ir));
1776 if (!cpu_has_mips_r6)
1779 MIPS_FPU_EMU_INC_STATS(selnez_s);
1780 SPFROMREG(rv.s, MIPSInst_FT(ir));
1782 SPFROMREG(rv.s, MIPSInst_FS(ir));
1788 union ieee754sp ft, fs, fd;
1790 if (!cpu_has_mips_r6)
1793 MIPS_FPU_EMU_INC_STATS(maddf_s);
1794 SPFROMREG(ft, MIPSInst_FT(ir));
1795 SPFROMREG(fs, MIPSInst_FS(ir));
1796 SPFROMREG(fd, MIPSInst_FD(ir));
1797 rv.s = ieee754sp_maddf(fd, fs, ft);
1802 union ieee754sp ft, fs, fd;
1804 if (!cpu_has_mips_r6)
1807 MIPS_FPU_EMU_INC_STATS(msubf_s);
1808 SPFROMREG(ft, MIPSInst_FT(ir));
1809 SPFROMREG(fs, MIPSInst_FS(ir));
1810 SPFROMREG(fd, MIPSInst_FD(ir));
1811 rv.s = ieee754sp_msubf(fd, fs, ft);
1818 if (!cpu_has_mips_r6)
1821 MIPS_FPU_EMU_INC_STATS(rint_s);
1822 SPFROMREG(fs, MIPSInst_FS(ir));
1823 rv.s = ieee754sp_rint(fs);
1830 if (!cpu_has_mips_r6)
1833 MIPS_FPU_EMU_INC_STATS(class_s);
1834 SPFROMREG(fs, MIPSInst_FS(ir));
1835 rv.w = ieee754sp_2008class(fs);
1841 union ieee754sp fs, ft;
1843 if (!cpu_has_mips_r6)
1846 MIPS_FPU_EMU_INC_STATS(min_s);
1847 SPFROMREG(ft, MIPSInst_FT(ir));
1848 SPFROMREG(fs, MIPSInst_FS(ir));
1849 rv.s = ieee754sp_fmin(fs, ft);
1854 union ieee754sp fs, ft;
1856 if (!cpu_has_mips_r6)
1859 MIPS_FPU_EMU_INC_STATS(mina_s);
1860 SPFROMREG(ft, MIPSInst_FT(ir));
1861 SPFROMREG(fs, MIPSInst_FS(ir));
1862 rv.s = ieee754sp_fmina(fs, ft);
1867 union ieee754sp fs, ft;
1869 if (!cpu_has_mips_r6)
1872 MIPS_FPU_EMU_INC_STATS(max_s);
1873 SPFROMREG(ft, MIPSInst_FT(ir));
1874 SPFROMREG(fs, MIPSInst_FS(ir));
1875 rv.s = ieee754sp_fmax(fs, ft);
1880 union ieee754sp fs, ft;
1882 if (!cpu_has_mips_r6)
1885 MIPS_FPU_EMU_INC_STATS(maxa_s);
1886 SPFROMREG(ft, MIPSInst_FT(ir));
1887 SPFROMREG(fs, MIPSInst_FS(ir));
1888 rv.s = ieee754sp_fmaxa(fs, ft);
1893 MIPS_FPU_EMU_INC_STATS(abs_s);
1894 handler.u = ieee754sp_abs;
1898 MIPS_FPU_EMU_INC_STATS(neg_s);
1899 handler.u = ieee754sp_neg;
1904 MIPS_FPU_EMU_INC_STATS(mov_s);
1905 SPFROMREG(rv.s, MIPSInst_FS(ir));
1908 /* binary op on handler */
1910 SPFROMREG(fs, MIPSInst_FS(ir));
1911 SPFROMREG(ft, MIPSInst_FT(ir));
1913 rv.s = (*handler.b) (fs, ft);
1916 SPFROMREG(fs, MIPSInst_FS(ir));
1917 rv.s = (*handler.u) (fs);
1920 if (ieee754_cxtest(IEEE754_INEXACT)) {
1921 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1922 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1924 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1925 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1926 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1928 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1929 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1930 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1932 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1933 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1934 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1936 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1937 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1938 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1942 /* unary conv ops */
1944 return SIGILL; /* not defined */
1947 MIPS_FPU_EMU_INC_STATS(cvt_d_s);
1948 SPFROMREG(fs, MIPSInst_FS(ir));
1949 rv.d = ieee754dp_fsp(fs);
1954 MIPS_FPU_EMU_INC_STATS(cvt_w_s);
1955 SPFROMREG(fs, MIPSInst_FS(ir));
1956 rv.w = ieee754sp_tint(fs);
1964 if (!cpu_has_mips_2_3_4_5_r)
1967 if (MIPSInst_FUNC(ir) == fceil_op)
1968 MIPS_FPU_EMU_INC_STATS(ceil_w_s);
1969 if (MIPSInst_FUNC(ir) == ffloor_op)
1970 MIPS_FPU_EMU_INC_STATS(floor_w_s);
1971 if (MIPSInst_FUNC(ir) == fround_op)
1972 MIPS_FPU_EMU_INC_STATS(round_w_s);
1973 if (MIPSInst_FUNC(ir) == ftrunc_op)
1974 MIPS_FPU_EMU_INC_STATS(trunc_w_s);
1976 oldrm = ieee754_csr.rm;
1977 SPFROMREG(fs, MIPSInst_FS(ir));
1978 ieee754_csr.rm = MIPSInst_FUNC(ir);
1979 rv.w = ieee754sp_tint(fs);
1980 ieee754_csr.rm = oldrm;
1985 if (!cpu_has_mips_r6)
1988 MIPS_FPU_EMU_INC_STATS(sel_s);
1989 SPFROMREG(fd, MIPSInst_FD(ir));
1991 SPFROMREG(rv.s, MIPSInst_FT(ir));
1993 SPFROMREG(rv.s, MIPSInst_FS(ir));
1997 if (!cpu_has_mips_3_4_5_64_r2_r6)
2000 MIPS_FPU_EMU_INC_STATS(cvt_l_s);
2001 SPFROMREG(fs, MIPSInst_FS(ir));
2002 rv.l = ieee754sp_tlong(fs);
2010 if (!cpu_has_mips_3_4_5_64_r2_r6)
2013 if (MIPSInst_FUNC(ir) == fceill_op)
2014 MIPS_FPU_EMU_INC_STATS(ceil_l_s);
2015 if (MIPSInst_FUNC(ir) == ffloorl_op)
2016 MIPS_FPU_EMU_INC_STATS(floor_l_s);
2017 if (MIPSInst_FUNC(ir) == froundl_op)
2018 MIPS_FPU_EMU_INC_STATS(round_l_s);
2019 if (MIPSInst_FUNC(ir) == ftruncl_op)
2020 MIPS_FPU_EMU_INC_STATS(trunc_l_s);
2022 oldrm = ieee754_csr.rm;
2023 SPFROMREG(fs, MIPSInst_FS(ir));
2024 ieee754_csr.rm = MIPSInst_FUNC(ir);
2025 rv.l = ieee754sp_tlong(fs);
2026 ieee754_csr.rm = oldrm;
2031 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2032 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2033 union ieee754sp fs, ft;
2035 SPFROMREG(fs, MIPSInst_FS(ir));
2036 SPFROMREG(ft, MIPSInst_FT(ir));
2037 rv.w = ieee754sp_cmp(fs, ft,
2038 cmptab[cmpop & 0x7], cmpop & 0x8);
2040 if ((cmpop & 0x8) && ieee754_cxtest
2041 (IEEE754_INVALID_OPERATION))
2042 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2054 union ieee754dp fd, fs, ft;
2056 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2057 union ieee754dp(*u) (union ieee754dp);
2060 switch (MIPSInst_FUNC(ir)) {
2063 MIPS_FPU_EMU_INC_STATS(add_d);
2064 handler.b = ieee754dp_add;
2067 MIPS_FPU_EMU_INC_STATS(sub_d);
2068 handler.b = ieee754dp_sub;
2071 MIPS_FPU_EMU_INC_STATS(mul_d);
2072 handler.b = ieee754dp_mul;
2075 MIPS_FPU_EMU_INC_STATS(div_d);
2076 handler.b = ieee754dp_div;
2081 if (!cpu_has_mips_2_3_4_5_r)
2084 MIPS_FPU_EMU_INC_STATS(sqrt_d);
2085 handler.u = ieee754dp_sqrt;
2088 * Note that on some MIPS IV implementations such as the
2089 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2090 * achieve full IEEE-754 accuracy - however this emulator does.
2093 if (!cpu_has_mips_4_5_64_r2_r6)
2096 MIPS_FPU_EMU_INC_STATS(rsqrt_d);
2097 handler.u = fpemu_dp_rsqrt;
2100 if (!cpu_has_mips_4_5_64_r2_r6)
2103 MIPS_FPU_EMU_INC_STATS(recip_d);
2104 handler.u = fpemu_dp_recip;
2107 if (!cpu_has_mips_4_5_r)
2110 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2111 if (((ctx->fcr31 & cond) != 0) !=
2112 ((MIPSInst_FT(ir) & 1) != 0))
2114 DPFROMREG(rv.d, MIPSInst_FS(ir));
2117 if (!cpu_has_mips_4_5_r)
2120 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2122 DPFROMREG(rv.d, MIPSInst_FS(ir));
2125 if (!cpu_has_mips_4_5_r)
2128 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2130 DPFROMREG(rv.d, MIPSInst_FS(ir));
2134 if (!cpu_has_mips_r6)
2137 MIPS_FPU_EMU_INC_STATS(seleqz_d);
2138 DPFROMREG(rv.d, MIPSInst_FT(ir));
2142 DPFROMREG(rv.d, MIPSInst_FS(ir));
2146 if (!cpu_has_mips_r6)
2149 MIPS_FPU_EMU_INC_STATS(selnez_d);
2150 DPFROMREG(rv.d, MIPSInst_FT(ir));
2152 DPFROMREG(rv.d, MIPSInst_FS(ir));
2158 union ieee754dp ft, fs, fd;
2160 if (!cpu_has_mips_r6)
2163 MIPS_FPU_EMU_INC_STATS(maddf_d);
2164 DPFROMREG(ft, MIPSInst_FT(ir));
2165 DPFROMREG(fs, MIPSInst_FS(ir));
2166 DPFROMREG(fd, MIPSInst_FD(ir));
2167 rv.d = ieee754dp_maddf(fd, fs, ft);
2172 union ieee754dp ft, fs, fd;
2174 if (!cpu_has_mips_r6)
2177 MIPS_FPU_EMU_INC_STATS(msubf_d);
2178 DPFROMREG(ft, MIPSInst_FT(ir));
2179 DPFROMREG(fs, MIPSInst_FS(ir));
2180 DPFROMREG(fd, MIPSInst_FD(ir));
2181 rv.d = ieee754dp_msubf(fd, fs, ft);
2188 if (!cpu_has_mips_r6)
2191 MIPS_FPU_EMU_INC_STATS(rint_d);
2192 DPFROMREG(fs, MIPSInst_FS(ir));
2193 rv.d = ieee754dp_rint(fs);
2200 if (!cpu_has_mips_r6)
2203 MIPS_FPU_EMU_INC_STATS(class_d);
2204 DPFROMREG(fs, MIPSInst_FS(ir));
2205 rv.l = ieee754dp_2008class(fs);
2211 union ieee754dp fs, ft;
2213 if (!cpu_has_mips_r6)
2216 MIPS_FPU_EMU_INC_STATS(min_d);
2217 DPFROMREG(ft, MIPSInst_FT(ir));
2218 DPFROMREG(fs, MIPSInst_FS(ir));
2219 rv.d = ieee754dp_fmin(fs, ft);
2224 union ieee754dp fs, ft;
2226 if (!cpu_has_mips_r6)
2229 MIPS_FPU_EMU_INC_STATS(mina_d);
2230 DPFROMREG(ft, MIPSInst_FT(ir));
2231 DPFROMREG(fs, MIPSInst_FS(ir));
2232 rv.d = ieee754dp_fmina(fs, ft);
2237 union ieee754dp fs, ft;
2239 if (!cpu_has_mips_r6)
2242 MIPS_FPU_EMU_INC_STATS(max_d);
2243 DPFROMREG(ft, MIPSInst_FT(ir));
2244 DPFROMREG(fs, MIPSInst_FS(ir));
2245 rv.d = ieee754dp_fmax(fs, ft);
2250 union ieee754dp fs, ft;
2252 if (!cpu_has_mips_r6)
2255 MIPS_FPU_EMU_INC_STATS(maxa_d);
2256 DPFROMREG(ft, MIPSInst_FT(ir));
2257 DPFROMREG(fs, MIPSInst_FS(ir));
2258 rv.d = ieee754dp_fmaxa(fs, ft);
2263 MIPS_FPU_EMU_INC_STATS(abs_d);
2264 handler.u = ieee754dp_abs;
2268 MIPS_FPU_EMU_INC_STATS(neg_d);
2269 handler.u = ieee754dp_neg;
2274 MIPS_FPU_EMU_INC_STATS(mov_d);
2275 DPFROMREG(rv.d, MIPSInst_FS(ir));
2278 /* binary op on handler */
2280 DPFROMREG(fs, MIPSInst_FS(ir));
2281 DPFROMREG(ft, MIPSInst_FT(ir));
2283 rv.d = (*handler.b) (fs, ft);
2286 DPFROMREG(fs, MIPSInst_FS(ir));
2287 rv.d = (*handler.u) (fs);
2294 MIPS_FPU_EMU_INC_STATS(cvt_s_d);
2295 DPFROMREG(fs, MIPSInst_FS(ir));
2296 rv.s = ieee754sp_fdp(fs);
2301 return SIGILL; /* not defined */
2304 MIPS_FPU_EMU_INC_STATS(cvt_w_d);
2305 DPFROMREG(fs, MIPSInst_FS(ir));
2306 rv.w = ieee754dp_tint(fs); /* wrong */
2314 if (!cpu_has_mips_2_3_4_5_r)
2317 if (MIPSInst_FUNC(ir) == fceil_op)
2318 MIPS_FPU_EMU_INC_STATS(ceil_w_d);
2319 if (MIPSInst_FUNC(ir) == ffloor_op)
2320 MIPS_FPU_EMU_INC_STATS(floor_w_d);
2321 if (MIPSInst_FUNC(ir) == fround_op)
2322 MIPS_FPU_EMU_INC_STATS(round_w_d);
2323 if (MIPSInst_FUNC(ir) == ftrunc_op)
2324 MIPS_FPU_EMU_INC_STATS(trunc_w_d);
2326 oldrm = ieee754_csr.rm;
2327 DPFROMREG(fs, MIPSInst_FS(ir));
2328 ieee754_csr.rm = MIPSInst_FUNC(ir);
2329 rv.w = ieee754dp_tint(fs);
2330 ieee754_csr.rm = oldrm;
2335 if (!cpu_has_mips_r6)
2338 MIPS_FPU_EMU_INC_STATS(sel_d);
2339 DPFROMREG(fd, MIPSInst_FD(ir));
2341 DPFROMREG(rv.d, MIPSInst_FT(ir));
2343 DPFROMREG(rv.d, MIPSInst_FS(ir));
2347 if (!cpu_has_mips_3_4_5_64_r2_r6)
2350 MIPS_FPU_EMU_INC_STATS(cvt_l_d);
2351 DPFROMREG(fs, MIPSInst_FS(ir));
2352 rv.l = ieee754dp_tlong(fs);
2360 if (!cpu_has_mips_3_4_5_64_r2_r6)
2363 if (MIPSInst_FUNC(ir) == fceill_op)
2364 MIPS_FPU_EMU_INC_STATS(ceil_l_d);
2365 if (MIPSInst_FUNC(ir) == ffloorl_op)
2366 MIPS_FPU_EMU_INC_STATS(floor_l_d);
2367 if (MIPSInst_FUNC(ir) == froundl_op)
2368 MIPS_FPU_EMU_INC_STATS(round_l_d);
2369 if (MIPSInst_FUNC(ir) == ftruncl_op)
2370 MIPS_FPU_EMU_INC_STATS(trunc_l_d);
2372 oldrm = ieee754_csr.rm;
2373 DPFROMREG(fs, MIPSInst_FS(ir));
2374 ieee754_csr.rm = MIPSInst_FUNC(ir);
2375 rv.l = ieee754dp_tlong(fs);
2376 ieee754_csr.rm = oldrm;
2381 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2382 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2383 union ieee754dp fs, ft;
2385 DPFROMREG(fs, MIPSInst_FS(ir));
2386 DPFROMREG(ft, MIPSInst_FT(ir));
2387 rv.w = ieee754dp_cmp(fs, ft,
2388 cmptab[cmpop & 0x7], cmpop & 0x8);
2393 (IEEE754_INVALID_OPERATION))
2394 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2410 switch (MIPSInst_FUNC(ir)) {
2412 /* convert word to single precision real */
2413 MIPS_FPU_EMU_INC_STATS(cvt_s_w);
2414 SPFROMREG(fs, MIPSInst_FS(ir));
2415 rv.s = ieee754sp_fint(fs.bits);
2419 /* convert word to double precision real */
2420 MIPS_FPU_EMU_INC_STATS(cvt_d_w);
2421 SPFROMREG(fs, MIPSInst_FS(ir));
2422 rv.d = ieee754dp_fint(fs.bits);
2426 /* Emulating the new CMP.condn.fmt R6 instruction */
2427 #define CMPOP_MASK 0x7
2428 #define SIGN_BIT (0x1 << 3)
2429 #define PREDICATE_BIT (0x1 << 4)
2431 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2432 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2433 union ieee754sp fs, ft;
2435 /* This is an R6 only instruction */
2436 if (!cpu_has_mips_r6 ||
2437 (MIPSInst_FUNC(ir) & 0x20))
2441 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2444 MIPS_FPU_EMU_INC_STATS(cmp_af_s);
2447 MIPS_FPU_EMU_INC_STATS(cmp_un_s);
2450 MIPS_FPU_EMU_INC_STATS(cmp_eq_s);
2453 MIPS_FPU_EMU_INC_STATS(cmp_ueq_s);
2456 MIPS_FPU_EMU_INC_STATS(cmp_lt_s);
2459 MIPS_FPU_EMU_INC_STATS(cmp_ult_s);
2462 MIPS_FPU_EMU_INC_STATS(cmp_le_s);
2465 MIPS_FPU_EMU_INC_STATS(cmp_ule_s);
2471 MIPS_FPU_EMU_INC_STATS(cmp_or_s);
2474 MIPS_FPU_EMU_INC_STATS(cmp_une_s);
2477 MIPS_FPU_EMU_INC_STATS(cmp_ne_s);
2482 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2485 MIPS_FPU_EMU_INC_STATS(cmp_saf_s);
2488 MIPS_FPU_EMU_INC_STATS(cmp_sun_s);
2491 MIPS_FPU_EMU_INC_STATS(cmp_seq_s);
2494 MIPS_FPU_EMU_INC_STATS(cmp_sueq_s);
2497 MIPS_FPU_EMU_INC_STATS(cmp_slt_s);
2500 MIPS_FPU_EMU_INC_STATS(cmp_sult_s);
2503 MIPS_FPU_EMU_INC_STATS(cmp_sle_s);
2506 MIPS_FPU_EMU_INC_STATS(cmp_sule_s);
2512 MIPS_FPU_EMU_INC_STATS(cmp_sor_s);
2515 MIPS_FPU_EMU_INC_STATS(cmp_sune_s);
2518 MIPS_FPU_EMU_INC_STATS(cmp_sne_s);
2524 /* fmt is w_fmt for single precision so fix it */
2526 /* default to false */
2530 SPFROMREG(fs, MIPSInst_FS(ir));
2531 SPFROMREG(ft, MIPSInst_FT(ir));
2533 /* positive predicates */
2534 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2535 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2537 rv.w = -1; /* true, all 1s */
2539 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2540 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2544 /* negative predicates */
2549 if (ieee754sp_cmp(fs, ft,
2550 negative_cmptab[cmpop],
2552 rv.w = -1; /* true, all 1s */
2554 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2555 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2560 /* Reserved R6 ops */
2572 if (!cpu_has_mips_3_4_5_64_r2_r6)
2575 DIFROMREG(bits, MIPSInst_FS(ir));
2577 switch (MIPSInst_FUNC(ir)) {
2579 /* convert long to single precision real */
2580 MIPS_FPU_EMU_INC_STATS(cvt_s_l);
2581 rv.s = ieee754sp_flong(bits);
2585 /* convert long to double precision real */
2586 MIPS_FPU_EMU_INC_STATS(cvt_d_l);
2587 rv.d = ieee754dp_flong(bits);
2591 /* Emulating the new CMP.condn.fmt R6 instruction */
2592 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2593 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2594 union ieee754dp fs, ft;
2596 if (!cpu_has_mips_r6 ||
2597 (MIPSInst_FUNC(ir) & 0x20))
2601 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2604 MIPS_FPU_EMU_INC_STATS(cmp_af_d);
2607 MIPS_FPU_EMU_INC_STATS(cmp_un_d);
2610 MIPS_FPU_EMU_INC_STATS(cmp_eq_d);
2613 MIPS_FPU_EMU_INC_STATS(cmp_ueq_d);
2616 MIPS_FPU_EMU_INC_STATS(cmp_lt_d);
2619 MIPS_FPU_EMU_INC_STATS(cmp_ult_d);
2622 MIPS_FPU_EMU_INC_STATS(cmp_le_d);
2625 MIPS_FPU_EMU_INC_STATS(cmp_ule_d);
2631 MIPS_FPU_EMU_INC_STATS(cmp_or_d);
2634 MIPS_FPU_EMU_INC_STATS(cmp_une_d);
2637 MIPS_FPU_EMU_INC_STATS(cmp_ne_d);
2642 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2645 MIPS_FPU_EMU_INC_STATS(cmp_saf_d);
2648 MIPS_FPU_EMU_INC_STATS(cmp_sun_d);
2651 MIPS_FPU_EMU_INC_STATS(cmp_seq_d);
2654 MIPS_FPU_EMU_INC_STATS(cmp_sueq_d);
2657 MIPS_FPU_EMU_INC_STATS(cmp_slt_d);
2660 MIPS_FPU_EMU_INC_STATS(cmp_sult_d);
2663 MIPS_FPU_EMU_INC_STATS(cmp_sle_d);
2666 MIPS_FPU_EMU_INC_STATS(cmp_sule_d);
2672 MIPS_FPU_EMU_INC_STATS(cmp_sor_d);
2675 MIPS_FPU_EMU_INC_STATS(cmp_sune_d);
2678 MIPS_FPU_EMU_INC_STATS(cmp_sne_d);
2684 /* fmt is l_fmt for double precision so fix it */
2686 /* default to false */
2690 DPFROMREG(fs, MIPSInst_FS(ir));
2691 DPFROMREG(ft, MIPSInst_FT(ir));
2693 /* positive predicates */
2694 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2695 if (ieee754dp_cmp(fs, ft,
2696 cmptab[cmpop], sig))
2697 rv.l = -1LL; /* true, all 1s */
2699 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2700 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2704 /* negative predicates */
2709 if (ieee754dp_cmp(fs, ft,
2710 negative_cmptab[cmpop],
2712 rv.l = -1LL; /* true, all 1s */
2714 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2715 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2720 /* Reserved R6 ops */
2734 * Update the fpu CSR register for this operation.
2735 * If an exception is required, generate a tidy SIGFPE exception,
2736 * without updating the result register.
2737 * Note: cause exception bits do not accumulate, they are rewritten
2738 * for each op; only the flag/sticky bits accumulate.
2740 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2741 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2742 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2747 * Now we can safely write the result back to the register file.
2752 if (cpu_has_mips_4_5_r)
2753 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2755 cbit = FPU_CSR_COND;
2759 ctx->fcr31 &= ~cbit;
2763 DPTOREG(rv.d, MIPSInst_FD(ir));
2766 SPTOREG(rv.s, MIPSInst_FD(ir));
2769 SITOREG(rv.w, MIPSInst_FD(ir));
2772 if (!cpu_has_mips_3_4_5_64_r2_r6)
2775 DITOREG(rv.l, MIPSInst_FD(ir));
2785 * Emulate FPU instructions.
2787 * If we use FPU hardware, then we have been typically called to handle
2788 * an unimplemented operation, such as where an operand is a NaN or
2789 * denormalized. In that case exit the emulation loop after a single
2790 * iteration so as to let hardware execute any subsequent instructions.
2792 * If we have no FPU hardware or it has been disabled, then continue
2793 * emulating floating-point instructions until one of these conditions
2796 * - a non-FPU instruction has been encountered,
2798 * - an attempt to emulate has ended with a signal,
2800 * - the ISA mode has been switched.
2802 * We need to terminate the emulation loop if we got switched to the
2803 * MIPS16 mode, whether supported or not, so that we do not attempt
2804 * to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
2805 * Similarly if we got switched to the microMIPS mode and only the
2806 * regular MIPS mode is supported, so that we do not attempt to emulate
2807 * a microMIPS instruction as a regular MIPS FPU instruction. Or if
2808 * we got switched to the regular MIPS mode and only the microMIPS mode
2809 * is supported, so that we do not attempt to emulate a regular MIPS
2810 * instruction that should cause an Address Error exception instead.
2811 * For simplicity we always terminate upon an ISA mode switch.
2813 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2814 int has_fpu, void __user **fault_addr)
2816 unsigned long oldepc, prevepc;
2817 struct mm_decoded_insn dec_insn;
2822 oldepc = xcp->cp0_epc;
2824 prevepc = xcp->cp0_epc;
2826 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2828 * Get next 2 microMIPS instructions and convert them
2829 * into 32-bit instructions.
2831 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2832 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2833 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2834 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2835 MIPS_FPU_EMU_INC_STATS(errors);
2840 /* Get first instruction. */
2841 if (mm_insn_16bit(*instr_ptr)) {
2842 /* Duplicate the half-word. */
2843 dec_insn.insn = (*instr_ptr << 16) |
2845 /* 16-bit instruction. */
2846 dec_insn.pc_inc = 2;
2849 dec_insn.insn = (*instr_ptr << 16) |
2851 /* 32-bit instruction. */
2852 dec_insn.pc_inc = 4;
2855 /* Get second instruction. */
2856 if (mm_insn_16bit(*instr_ptr)) {
2857 /* Duplicate the half-word. */
2858 dec_insn.next_insn = (*instr_ptr << 16) |
2860 /* 16-bit instruction. */
2861 dec_insn.next_pc_inc = 2;
2863 dec_insn.next_insn = (*instr_ptr << 16) |
2865 /* 32-bit instruction. */
2866 dec_insn.next_pc_inc = 4;
2868 dec_insn.micro_mips_mode = 1;
2870 if ((get_user(dec_insn.insn,
2871 (mips_instruction __user *) xcp->cp0_epc)) ||
2872 (get_user(dec_insn.next_insn,
2873 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2874 MIPS_FPU_EMU_INC_STATS(errors);
2877 dec_insn.pc_inc = 4;
2878 dec_insn.next_pc_inc = 4;
2879 dec_insn.micro_mips_mode = 0;
2882 if ((dec_insn.insn == 0) ||
2883 ((dec_insn.pc_inc == 2) &&
2884 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2885 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2888 * The 'ieee754_csr' is an alias of ctx->fcr31.
2889 * No need to copy ctx->fcr31 to ieee754_csr.
2891 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2899 * We have to check for the ISA bit explicitly here,
2900 * because `get_isa16_mode' may return 0 if support
2901 * for code compression has been globally disabled,
2902 * or otherwise we may produce the wrong signal or
2903 * even proceed successfully where we must not.
2905 if ((xcp->cp0_epc ^ prevepc) & 0x1)
2909 } while (xcp->cp0_epc > prevepc);
2911 /* SIGILL indicates a non-fpu instruction */
2912 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2913 /* but if EPC has advanced, then ignore it */