2 * core.h - DesignWare USB3 DRD Core Header
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef __DRIVERS_USB_DWC3_CORE_H
20 #define __DRIVERS_USB_DWC3_CORE_H
22 #include <linux/device.h>
23 #include <linux/spinlock.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/dma-mapping.h>
28 #include <linux/debugfs.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/otg.h>
33 #include <linux/ulpi/interface.h>
35 #include <linux/phy/phy.h>
37 #define DWC3_MSG_MAX 500
39 /* Global constants */
40 #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */
41 #define DWC3_EP0_BOUNCE_SIZE 512
42 #define DWC3_ENDPOINTS_NUM 32
43 #define DWC3_XHCI_RESOURCES_NUM 2
45 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
46 #define DWC3_EVENT_BUFFERS_SIZE 4096
47 #define DWC3_EVENT_TYPE_MASK 0xfe
49 #define DWC3_EVENT_TYPE_DEV 0
50 #define DWC3_EVENT_TYPE_CARKIT 3
51 #define DWC3_EVENT_TYPE_I2C 4
53 #define DWC3_DEVICE_EVENT_DISCONNECT 0
54 #define DWC3_DEVICE_EVENT_RESET 1
55 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
56 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
57 #define DWC3_DEVICE_EVENT_WAKEUP 4
58 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
59 #define DWC3_DEVICE_EVENT_EOPF 6
60 #define DWC3_DEVICE_EVENT_SOF 7
61 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
62 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
63 #define DWC3_DEVICE_EVENT_OVERFLOW 11
65 #define DWC3_GEVNTCOUNT_MASK 0xfffc
66 #define DWC3_GSNPSID_MASK 0xffff0000
67 #define DWC3_GSNPSREV_MASK 0xffff
69 /* DWC3 registers memory space boundries */
70 #define DWC3_XHCI_REGS_START 0x0
71 #define DWC3_XHCI_REGS_END 0x7fff
72 #define DWC3_GLOBALS_REGS_START 0xc100
73 #define DWC3_GLOBALS_REGS_END 0xc6ff
74 #define DWC3_DEVICE_REGS_START 0xc700
75 #define DWC3_DEVICE_REGS_END 0xcbff
76 #define DWC3_OTG_REGS_START 0xcc00
77 #define DWC3_OTG_REGS_END 0xccff
79 /* Global Registers */
80 #define DWC3_GSBUSCFG0 0xc100
81 #define DWC3_GSBUSCFG1 0xc104
82 #define DWC3_GTXTHRCFG 0xc108
83 #define DWC3_GRXTHRCFG 0xc10c
84 #define DWC3_GCTL 0xc110
85 #define DWC3_GEVTEN 0xc114
86 #define DWC3_GSTS 0xc118
87 #define DWC3_GUCTL1 0xc11c
88 #define DWC3_GSNPSID 0xc120
89 #define DWC3_GGPIO 0xc124
90 #define DWC3_GUID 0xc128
91 #define DWC3_GUCTL 0xc12c
92 #define DWC3_GBUSERRADDR0 0xc130
93 #define DWC3_GBUSERRADDR1 0xc134
94 #define DWC3_GPRTBIMAP0 0xc138
95 #define DWC3_GPRTBIMAP1 0xc13c
96 #define DWC3_GHWPARAMS0 0xc140
97 #define DWC3_GHWPARAMS1 0xc144
98 #define DWC3_GHWPARAMS2 0xc148
99 #define DWC3_GHWPARAMS3 0xc14c
100 #define DWC3_GHWPARAMS4 0xc150
101 #define DWC3_GHWPARAMS5 0xc154
102 #define DWC3_GHWPARAMS6 0xc158
103 #define DWC3_GHWPARAMS7 0xc15c
104 #define DWC3_GDBGFIFOSPACE 0xc160
105 #define DWC3_GDBGLTSSM 0xc164
106 #define DWC3_GPRTBIMAP_HS0 0xc180
107 #define DWC3_GPRTBIMAP_HS1 0xc184
108 #define DWC3_GPRTBIMAP_FS0 0xc188
109 #define DWC3_GPRTBIMAP_FS1 0xc18c
110 #define DWC3_GUCTL2 0xc19c
112 #define DWC3_VER_NUMBER 0xc1a0
113 #define DWC3_VER_TYPE 0xc1a4
115 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
116 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
118 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
120 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
122 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
123 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
125 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
126 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
127 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
128 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
130 #define DWC3_GHWPARAMS8 0xc600
131 #define DWC3_GFLADJ 0xc630
133 /* Device Registers */
134 #define DWC3_DCFG 0xc700
135 #define DWC3_DCTL 0xc704
136 #define DWC3_DEVTEN 0xc708
137 #define DWC3_DSTS 0xc70c
138 #define DWC3_DGCMDPAR 0xc710
139 #define DWC3_DGCMD 0xc714
140 #define DWC3_DALEPENA 0xc720
142 #define DWC3_DEP_BASE(n) (0xc800 + (n * 0x10))
143 #define DWC3_DEPCMDPAR2 0x00
144 #define DWC3_DEPCMDPAR1 0x04
145 #define DWC3_DEPCMDPAR0 0x08
146 #define DWC3_DEPCMD 0x0c
149 #define DWC3_OCFG 0xcc00
150 #define DWC3_OCTL 0xcc04
151 #define DWC3_OEVT 0xcc08
152 #define DWC3_OEVTEN 0xcc0C
153 #define DWC3_OSTS 0xcc10
157 /* Global Debug Queue/FIFO Space Available Register */
158 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
159 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
160 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
162 #define DWC3_TXFIFOQ 0
163 #define DWC3_RXFIFOQ 1
164 #define DWC3_TXREQQ 2
165 #define DWC3_RXREQQ 3
166 #define DWC3_RXINFOQ 4
167 #define DWC3_PSTATQ 5
168 #define DWC3_DESCFETCHQ 6
169 #define DWC3_EVENTQ 7
170 #define DWC3_AUXEVENTQ 8
172 /* Global RX Threshold Configuration Register */
173 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
174 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
175 #define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29)
177 /* Global Configuration Register */
178 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
179 #define DWC3_GCTL_U2RSTECN (1 << 16)
180 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
181 #define DWC3_GCTL_CLK_BUS (0)
182 #define DWC3_GCTL_CLK_PIPE (1)
183 #define DWC3_GCTL_CLK_PIPEHALF (2)
184 #define DWC3_GCTL_CLK_MASK (3)
186 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
187 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
188 #define DWC3_GCTL_PRTCAP_HOST 1
189 #define DWC3_GCTL_PRTCAP_DEVICE 2
190 #define DWC3_GCTL_PRTCAP_OTG 3
192 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
193 #define DWC3_GCTL_SOFITPSYNC (1 << 10)
194 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
195 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
196 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
197 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
198 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
199 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
201 /* Global USB2 PHY Configuration Register */
202 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
203 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
204 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
205 #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
206 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
207 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
208 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
209 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
210 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
211 #define USBTRDTIM_UTMI_8_BIT 9
212 #define USBTRDTIM_UTMI_16_BIT 5
213 #define UTMI_PHYIF_16_BIT 1
214 #define UTMI_PHYIF_8_BIT 0
216 /* Global USB2 PHY Vendor Control Register */
217 #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
218 #define DWC3_GUSB2PHYACC_BUSY (1 << 23)
219 #define DWC3_GUSB2PHYACC_WRITE (1 << 22)
220 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
221 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
222 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
224 /* Global USB3 PIPE Control Register */
225 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
226 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
227 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28)
228 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX (1 << 27)
229 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
230 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
231 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
232 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
233 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
234 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
235 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
236 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
237 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
238 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
240 /* Global TX Fifo Size Register */
241 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
242 #define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff) /* DWC_usb31 only */
243 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
244 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
246 /* Global Event Size Registers */
247 #define DWC3_GEVNTSIZ_INTMASK (1 << 31)
248 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
250 /* Global HWPARAMS0 Register */
251 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
252 #define DWC3_GHWPARAMS0_MODE_GADGET 0
253 #define DWC3_GHWPARAMS0_MODE_HOST 1
254 #define DWC3_GHWPARAMS0_MODE_DRD 2
255 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
256 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
257 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
258 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
259 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
261 /* Global HWPARAMS1 Register */
262 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
263 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
264 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
265 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
266 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
267 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
269 /* Global HWPARAMS3 Register */
270 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
271 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
272 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
273 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
274 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
275 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
276 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
277 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
278 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
279 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
280 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
281 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
283 /* Global HWPARAMS4 Register */
284 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
285 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
287 /* Global HWPARAMS6 Register */
288 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
290 /* Global HWPARAMS7 Register */
291 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
292 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
294 /* Global Frame Length Adjustment Register */
295 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
296 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
298 /* Global User Control Register 2 */
299 #define DWC3_GUCTL2_RST_ACTBITLATER (1 << 14)
301 /* Device Configuration Register */
302 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
303 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
305 #define DWC3_DCFG_SPEED_MASK (7 << 0)
306 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
307 #define DWC3_DCFG_SUPERSPEED (4 << 0)
308 #define DWC3_DCFG_HIGHSPEED (0 << 0)
309 #define DWC3_DCFG_FULLSPEED (1 << 0)
310 #define DWC3_DCFG_LOWSPEED (2 << 0)
312 #define DWC3_DCFG_NUMP_SHIFT 17
313 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
314 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
315 #define DWC3_DCFG_LPM_CAP (1 << 22)
317 /* Device Control Register */
318 #define DWC3_DCTL_RUN_STOP (1 << 31)
319 #define DWC3_DCTL_CSFTRST (1 << 30)
320 #define DWC3_DCTL_LSFTRST (1 << 29)
322 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
323 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
325 #define DWC3_DCTL_APPL1RES (1 << 23)
327 /* These apply for core versions 1.87a and earlier */
328 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
329 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
330 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
331 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
332 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
333 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
334 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
336 /* These apply for core versions 1.94a and later */
337 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
338 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
340 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
341 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
342 #define DWC3_DCTL_CRS (1 << 17)
343 #define DWC3_DCTL_CSS (1 << 16)
345 #define DWC3_DCTL_INITU2ENA (1 << 12)
346 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
347 #define DWC3_DCTL_INITU1ENA (1 << 10)
348 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
349 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
351 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
352 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
354 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
355 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
356 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
357 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
358 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
359 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
360 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
362 /* Device Event Enable Register */
363 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
364 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
365 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
366 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
367 #define DWC3_DEVTEN_SOFEN (1 << 7)
368 #define DWC3_DEVTEN_EOPFEN (1 << 6)
369 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
370 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
371 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
372 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
373 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
374 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
376 /* Device Status Register */
377 #define DWC3_DSTS_DCNRD (1 << 29)
379 /* This applies for core versions 1.87a and earlier */
380 #define DWC3_DSTS_PWRUPREQ (1 << 24)
382 /* These apply for core versions 1.94a and later */
383 #define DWC3_DSTS_RSS (1 << 25)
384 #define DWC3_DSTS_SSS (1 << 24)
386 #define DWC3_DSTS_COREIDLE (1 << 23)
387 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
389 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
390 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
392 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
394 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
395 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
397 #define DWC3_DSTS_CONNECTSPD (7 << 0)
399 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
400 #define DWC3_DSTS_SUPERSPEED (4 << 0)
401 #define DWC3_DSTS_HIGHSPEED (0 << 0)
402 #define DWC3_DSTS_FULLSPEED (1 << 0)
403 #define DWC3_DSTS_LOWSPEED (2 << 0)
405 /* Device Generic Command Register */
406 #define DWC3_DGCMD_SET_LMP 0x01
407 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
408 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
410 /* These apply for core versions 1.94a and later */
411 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
412 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
414 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
415 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
416 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
417 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
419 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
420 #define DWC3_DGCMD_CMDACT (1 << 10)
421 #define DWC3_DGCMD_CMDIOC (1 << 8)
423 /* Device Generic Command Parameter Register */
424 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
425 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
426 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
427 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
428 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
429 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
431 /* Device Endpoint Command Register */
432 #define DWC3_DEPCMD_PARAM_SHIFT 16
433 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
434 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
435 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
436 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
437 #define DWC3_DEPCMD_CLEARPENDIN (1 << 11)
438 #define DWC3_DEPCMD_CMDACT (1 << 10)
439 #define DWC3_DEPCMD_CMDIOC (1 << 8)
441 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
442 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
443 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
444 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
445 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
446 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
447 /* This applies for core versions 1.90a and earlier */
448 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
449 /* This applies for core versions 1.94a and later */
450 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
451 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
452 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
454 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
455 #define DWC3_DALEPENA_EP(n) (1 << n)
457 #define DWC3_DEPCMD_TYPE_CONTROL 0
458 #define DWC3_DEPCMD_TYPE_ISOC 1
459 #define DWC3_DEPCMD_TYPE_BULK 2
460 #define DWC3_DEPCMD_TYPE_INTR 3
467 * struct dwc3_event_buffer - Software event buffer representation
469 * @length: size of this buffer
470 * @lpos: event offset
471 * @count: cache of last read event count register
472 * @flags: flags related to this event buffer
474 * @dwc: pointer to DWC controller
476 struct dwc3_event_buffer {
483 #define DWC3_EVENT_PENDING BIT(0)
490 #define DWC3_EP_FLAG_STALLED (1 << 0)
491 #define DWC3_EP_FLAG_WEDGED (1 << 1)
493 #define DWC3_EP_DIRECTION_TX true
494 #define DWC3_EP_DIRECTION_RX false
496 #define DWC3_TRB_NUM 256
499 * struct dwc3_ep - device side endpoint representation
500 * @endpoint: usb endpoint
501 * @pending_list: list of pending requests for this endpoint
502 * @started_list: list of started requests on this endpoint
503 * @lock: spinlock for endpoint request queue traversal
504 * @regs: pointer to first endpoint register
505 * @trb_pool: array of transaction buffers
506 * @trb_pool_dma: dma address of @trb_pool
507 * @trb_enqueue: enqueue 'pointer' into TRB array
508 * @trb_dequeue: dequeue 'pointer' into TRB array
509 * @desc: usb_endpoint_descriptor pointer
510 * @dwc: pointer to DWC controller
511 * @saved_state: ep state saved during hibernation
512 * @flags: endpoint flags (wedged, stalled, ...)
513 * @number: endpoint number (1 - 15)
514 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
515 * @resource_index: Resource transfer index
516 * @interval: the interval on which the ISOC transfer is started
517 * @allocated_requests: number of requests allocated
518 * @queued_requests: number of requests queued for transfer
519 * @name: a human readable name e.g. ep1out-bulk
520 * @direction: true for TX, false for RX
521 * @stream_capable: true when streams are enabled
524 struct usb_ep endpoint;
525 struct list_head pending_list;
526 struct list_head started_list;
531 struct dwc3_trb *trb_pool;
532 dma_addr_t trb_pool_dma;
533 const struct usb_ss_ep_comp_descriptor *comp_desc;
538 #define DWC3_EP_ENABLED (1 << 0)
539 #define DWC3_EP_STALL (1 << 1)
540 #define DWC3_EP_WEDGE (1 << 2)
541 #define DWC3_EP_BUSY (1 << 4)
542 #define DWC3_EP_PENDING_REQUEST (1 << 5)
543 #define DWC3_EP_MISSED_ISOC (1 << 6)
545 /* This last one is specific to EP0 */
546 #define DWC3_EP0_DIR_IN (1 << 31)
549 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
550 * use a u8 type here. If anybody decides to increase number of TRBs to
551 * anything larger than 256 - I can't see why people would want to do
552 * this though - then this type needs to be changed.
554 * By using u8 types we ensure that our % operator when incrementing
555 * enqueue and dequeue get optimized away by the compiler.
563 u32 allocated_requests;
569 unsigned direction:1;
570 unsigned stream_capable:1;
574 DWC3_PHY_UNKNOWN = 0,
580 DWC3_EP0_UNKNOWN = 0,
583 DWC3_EP0_NRDY_STATUS,
586 enum dwc3_ep0_state {
593 enum dwc3_link_state {
595 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
596 DWC3_LINK_STATE_U1 = 0x01,
597 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
598 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
599 DWC3_LINK_STATE_SS_DIS = 0x04,
600 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
601 DWC3_LINK_STATE_SS_INACT = 0x06,
602 DWC3_LINK_STATE_POLL = 0x07,
603 DWC3_LINK_STATE_RECOV = 0x08,
604 DWC3_LINK_STATE_HRESET = 0x09,
605 DWC3_LINK_STATE_CMPLY = 0x0a,
606 DWC3_LINK_STATE_LPBK = 0x0b,
607 DWC3_LINK_STATE_RESET = 0x0e,
608 DWC3_LINK_STATE_RESUME = 0x0f,
609 DWC3_LINK_STATE_MASK = 0x0f,
612 /* TRB Length, PCM and Status */
613 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
614 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
615 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
616 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
618 #define DWC3_TRBSTS_OK 0
619 #define DWC3_TRBSTS_MISSED_ISOC 1
620 #define DWC3_TRBSTS_SETUP_PENDING 2
621 #define DWC3_TRB_STS_XFER_IN_PROG 4
624 #define DWC3_TRB_CTRL_HWO (1 << 0)
625 #define DWC3_TRB_CTRL_LST (1 << 1)
626 #define DWC3_TRB_CTRL_CHN (1 << 2)
627 #define DWC3_TRB_CTRL_CSP (1 << 3)
628 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
629 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
630 #define DWC3_TRB_CTRL_IOC (1 << 11)
631 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
633 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
634 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
635 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
636 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
637 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
638 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
639 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
640 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
641 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
644 * struct dwc3_trb - transfer request block (hw format)
658 * dwc3_hwparams - copy of HWPARAMS registers
659 * @hwparams0 - GHWPARAMS0
660 * @hwparams1 - GHWPARAMS1
661 * @hwparams2 - GHWPARAMS2
662 * @hwparams3 - GHWPARAMS3
663 * @hwparams4 - GHWPARAMS4
664 * @hwparams5 - GHWPARAMS5
665 * @hwparams6 - GHWPARAMS6
666 * @hwparams7 - GHWPARAMS7
667 * @hwparams8 - GHWPARAMS8
669 struct dwc3_hwparams {
682 #define DWC3_MODE(n) ((n) & 0x7)
684 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
687 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
690 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
691 #define DWC3_NUM_EPS_MASK (0x3f << 12)
692 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
693 (DWC3_NUM_EPS_MASK)) >> 12)
694 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
695 (DWC3_NUM_IN_EPS_MASK)) >> 18)
698 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
701 * struct dwc3_request - representation of a transfer request
702 * @request: struct usb_request to be transferred
703 * @list: a list_head used for request queueing
704 * @dep: struct dwc3_ep owning this request
705 * @sg: pointer to first incomplete sg
706 * @num_pending_sgs: counter to pending sgs
707 * @first_trb_index: index to first trb used by this request
708 * @epnum: endpoint number to which this request refers
709 * @trb: pointer to struct dwc3_trb
710 * @trb_dma: DMA address of @trb
711 * @direction: IN or OUT direction flag
712 * @mapped: true when request has been dma-mapped
713 * @queued: true when request has been queued to HW
715 struct dwc3_request {
716 struct usb_request request;
717 struct list_head list;
719 struct scatterlist *sg;
721 unsigned num_pending_sgs;
724 struct dwc3_trb *trb;
727 unsigned direction:1;
733 * struct dwc3_scratchpad_array - hibernation scratchpad array
734 * (format defined by hw)
736 struct dwc3_scratchpad_array {
737 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
741 * struct dwc3 - representation of our controller
742 * @ctrl_req: usb control request which is used for ep0
743 * @ep0_trb: trb which is used for the ctrl_req
744 * @ep0_bounce: bounce buffer for ep0
745 * @zlp_buf: used when request->zero is set
746 * @setup_buf: used while precessing STD USB requests
747 * @ctrl_req_addr: dma address of ctrl_req
748 * @ep0_trb: dma address of ep0_trb
749 * @ep0_usb_req: dummy req used while handling STD USB requests
750 * @ep0_bounce_addr: dma address of ep0_bounce
751 * @scratch_addr: dma address of scratchbuf
752 * @lock: for synchronizing
753 * @dev: pointer to our struct device
754 * @xhci: pointer to our xHCI child
755 * @event_buffer_list: a list of event buffers
756 * @gadget: device side representation of the peripheral controller
757 * @gadget_driver: pointer to the gadget driver
758 * @regs: base address for our registers
759 * @regs_size: address space size
760 * @fladj: frame length adjustment
761 * @irq_gadget: peripheral controller's IRQ number
762 * @nr_scratch: number of scratch buffers
763 * @u1u2: only used on revisions <1.83a for workaround
764 * @maximum_speed: maximum speed requested (mainly for testing purposes)
765 * @revision: revision register contents
766 * @dr_mode: requested mode of operation
767 * @hsphy_mode: UTMI phy mode, one of following:
768 * - USBPHY_INTERFACE_MODE_UTMI
769 * - USBPHY_INTERFACE_MODE_UTMIW
770 * @usb2_phy: pointer to USB2 PHY
771 * @usb3_phy: pointer to USB3 PHY
772 * @usb2_generic_phy: pointer to USB2 PHY
773 * @usb3_generic_phy: pointer to USB3 PHY
774 * @ulpi: pointer to ulpi interface
775 * @dcfg: saved contents of DCFG register
776 * @gctl: saved contents of GCTL register
777 * @isoch_delay: wValue from Set Isochronous Delay request;
778 * @u2sel: parameter from Set SEL request.
779 * @u2pel: parameter from Set SEL request.
780 * @u1sel: parameter from Set SEL request.
781 * @u1pel: parameter from Set SEL request.
782 * @num_out_eps: number of out endpoints
783 * @num_in_eps: number of in endpoints
784 * @ep0_next_event: hold the next expected event
785 * @ep0state: state of endpoint zero
786 * @link_state: link state
787 * @speed: device speed (super, high, full, low)
788 * @mem: points to start of memory which is used for this struct.
789 * @hwparams: copy of hwparams registers
790 * @root: debugfs root folder pointer
791 * @regset: debugfs pointer to regdump file
792 * @test_mode: true when we're entering a USB test mode
793 * @test_mode_nr: test feature selector
794 * @lpm_nyet_threshold: LPM NYET response threshold
795 * @hird_threshold: HIRD threshold
796 * @hsphy_interface: "utmi" or "ulpi"
797 * @connected: true when we're connected to a host, false otherwise
798 * @delayed_status: true when gadget driver asks for delayed status
799 * @ep0_bounced: true when we used bounce buffer
800 * @ep0_expect_in: true when we expect a DATA IN transfer
801 * @has_hibernation: true when dwc3 was configured with Hibernation
802 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
803 * there's now way for software to detect this in runtime.
804 * @is_utmi_l1_suspend: the core asserts output signal
806 * 1 - utmi_l1_suspend_n
807 * @is_fpga: true when we are using the FPGA board
808 * @pending_events: true when we have pending IRQs to be handled
809 * @pullups_connected: true when Run/Stop bit is set
810 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
811 * @start_config_issued: true when StartConfig command has been issued
812 * @three_stage_setup: set if we perform a three phase setup
813 * @usb3_lpm_capable: set if hadrware supports Link Power Management
814 * @disable_scramble_quirk: set if we enable the disable scramble quirk
815 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
816 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
817 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
818 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
819 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
820 * @lfps_filter_quirk: set if we enable LFPS filter quirk
821 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
822 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
823 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
824 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
825 * disabling the suspend signal to the PHY.
826 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
827 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
828 * provide a free-running PHY clock.
829 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
831 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
832 * @tx_de_emphasis: Tx de-emphasis value
833 * 0 - -6dB de-emphasis
834 * 1 - -3.5dB de-emphasis
839 struct usb_ctrlrequest *ctrl_req;
840 struct dwc3_trb *ep0_trb;
845 dma_addr_t ctrl_req_addr;
846 dma_addr_t ep0_trb_addr;
847 dma_addr_t ep0_bounce_addr;
848 dma_addr_t scratch_addr;
849 struct dwc3_request ep0_usb_req;
856 struct platform_device *xhci;
857 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
859 struct dwc3_event_buffer *ev_buf;
860 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
862 struct usb_gadget gadget;
863 struct usb_gadget_driver *gadget_driver;
865 struct usb_phy *usb2_phy;
866 struct usb_phy *usb3_phy;
868 struct phy *usb2_generic_phy;
869 struct phy *usb3_generic_phy;
876 enum usb_dr_mode dr_mode;
877 enum usb_phy_interface hsphy_mode;
886 * All 3.1 IP version constants are greater than the 3.0 IP
887 * version constants. This works for most version checks in
888 * dwc3. However, in the future, this may not apply as
889 * features may be developed on newer versions of the 3.0 IP
890 * that are not in the 3.1 IP.
894 #define DWC3_REVISION_173A 0x5533173a
895 #define DWC3_REVISION_175A 0x5533175a
896 #define DWC3_REVISION_180A 0x5533180a
897 #define DWC3_REVISION_183A 0x5533183a
898 #define DWC3_REVISION_185A 0x5533185a
899 #define DWC3_REVISION_187A 0x5533187a
900 #define DWC3_REVISION_188A 0x5533188a
901 #define DWC3_REVISION_190A 0x5533190a
902 #define DWC3_REVISION_194A 0x5533194a
903 #define DWC3_REVISION_200A 0x5533200a
904 #define DWC3_REVISION_202A 0x5533202a
905 #define DWC3_REVISION_210A 0x5533210a
906 #define DWC3_REVISION_220A 0x5533220a
907 #define DWC3_REVISION_230A 0x5533230a
908 #define DWC3_REVISION_240A 0x5533240a
909 #define DWC3_REVISION_250A 0x5533250a
910 #define DWC3_REVISION_260A 0x5533260a
911 #define DWC3_REVISION_270A 0x5533270a
912 #define DWC3_REVISION_280A 0x5533280a
913 #define DWC3_REVISION_300A 0x5533300a
914 #define DWC3_REVISION_310A 0x5533310a
917 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
918 * just so dwc31 revisions are always larger than dwc3.
920 #define DWC3_REVISION_IS_DWC31 0x80000000
921 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
923 enum dwc3_ep0_next ep0_next_event;
924 enum dwc3_ep0_state ep0state;
925 enum dwc3_link_state link_state;
940 struct dwc3_hwparams hwparams;
942 struct debugfs_regset32 *regset;
946 u8 lpm_nyet_threshold;
949 const char *hsphy_interface;
951 unsigned connected:1;
952 unsigned delayed_status:1;
953 unsigned ep0_bounced:1;
954 unsigned ep0_expect_in:1;
955 unsigned has_hibernation:1;
956 unsigned has_lpm_erratum:1;
957 unsigned is_utmi_l1_suspend:1;
959 unsigned pending_events:1;
960 unsigned pullups_connected:1;
961 unsigned setup_packet_pending:1;
962 unsigned three_stage_setup:1;
963 unsigned usb3_lpm_capable:1;
965 unsigned disable_scramble_quirk:1;
966 unsigned u2exit_lfps_quirk:1;
967 unsigned u2ss_inp3_quirk:1;
968 unsigned req_p1p2p3_quirk:1;
969 unsigned del_p1p2p3_quirk:1;
970 unsigned del_phy_power_chg_quirk:1;
971 unsigned lfps_filter_quirk:1;
972 unsigned rx_detect_poll_quirk:1;
973 unsigned dis_u3_susphy_quirk:1;
974 unsigned dis_u2_susphy_quirk:1;
975 unsigned dis_enblslpm_quirk:1;
976 unsigned dis_rxdet_inp3_quirk:1;
977 unsigned dis_u2_freeclk_exists_quirk:1;
978 unsigned dis_del_phy_power_chg_quirk:1;
980 unsigned tx_de_emphasis_quirk:1;
981 unsigned tx_de_emphasis:2;
984 /* -------------------------------------------------------------------------- */
986 /* -------------------------------------------------------------------------- */
988 struct dwc3_event_type {
994 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
995 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
996 #define DWC3_DEPEVT_XFERNOTREADY 0x03
997 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
998 #define DWC3_DEPEVT_STREAMEVT 0x06
999 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1002 * struct dwc3_event_depvt - Device Endpoint Events
1003 * @one_bit: indicates this is an endpoint event (not used)
1004 * @endpoint_number: number of the endpoint
1005 * @endpoint_event: The event we have:
1007 * 0x01 - XferComplete
1008 * 0x02 - XferInProgress
1009 * 0x03 - XferNotReady
1010 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1014 * @reserved11_10: Reserved, don't use.
1015 * @status: Indicates the status of the event. Refer to databook for
1017 * @parameters: Parameters of the current event. Refer to databook for
1020 struct dwc3_event_depevt {
1022 u32 endpoint_number:5;
1023 u32 endpoint_event:4;
1024 u32 reserved11_10:2;
1027 /* Within XferNotReady */
1028 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
1030 /* Within XferComplete */
1031 #define DEPEVT_STATUS_BUSERR (1 << 0)
1032 #define DEPEVT_STATUS_SHORT (1 << 1)
1033 #define DEPEVT_STATUS_IOC (1 << 2)
1034 #define DEPEVT_STATUS_LST (1 << 3)
1036 /* Stream event only */
1037 #define DEPEVT_STREAMEVT_FOUND 1
1038 #define DEPEVT_STREAMEVT_NOTFOUND 2
1040 /* Control-only Status */
1041 #define DEPEVT_STATUS_CONTROL_DATA 1
1042 #define DEPEVT_STATUS_CONTROL_STATUS 2
1044 /* In response to Start Transfer */
1045 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1046 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1052 * struct dwc3_event_devt - Device Events
1053 * @one_bit: indicates this is a non-endpoint event (not used)
1054 * @device_event: indicates it's a device event. Should read as 0x00
1055 * @type: indicates the type of device event.
1068 * 12 - VndrDevTstRcved
1069 * @reserved15_12: Reserved, not used
1070 * @event_info: Information about this event
1071 * @reserved31_25: Reserved, not used
1073 struct dwc3_event_devt {
1077 u32 reserved15_12:4;
1079 u32 reserved31_25:7;
1083 * struct dwc3_event_gevt - Other Core Events
1084 * @one_bit: indicates this is a non-endpoint event (not used)
1085 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1086 * @phy_port_number: self-explanatory
1087 * @reserved31_12: Reserved, not used.
1089 struct dwc3_event_gevt {
1092 u32 phy_port_number:4;
1093 u32 reserved31_12:20;
1097 * union dwc3_event - representation of Event Buffer contents
1098 * @raw: raw 32-bit event
1099 * @type: the type of the event
1100 * @depevt: Device Endpoint Event
1101 * @devt: Device Event
1102 * @gevt: Global Event
1106 struct dwc3_event_type type;
1107 struct dwc3_event_depevt depevt;
1108 struct dwc3_event_devt devt;
1109 struct dwc3_event_gevt gevt;
1113 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1115 * @param2: third parameter
1116 * @param1: second parameter
1117 * @param0: first parameter
1119 struct dwc3_gadget_ep_cmd_params {
1126 * DWC3 Features to be used as Driver Data
1129 #define DWC3_HAS_PERIPHERAL BIT(0)
1130 #define DWC3_HAS_XHCI BIT(1)
1131 #define DWC3_HAS_OTG BIT(3)
1134 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1135 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1137 /* check whether we are on the DWC_usb31 core */
1138 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1140 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1143 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1144 int dwc3_host_init(struct dwc3 *dwc);
1145 void dwc3_host_exit(struct dwc3 *dwc);
1147 static inline int dwc3_host_init(struct dwc3 *dwc)
1149 static inline void dwc3_host_exit(struct dwc3 *dwc)
1153 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1154 int dwc3_gadget_init(struct dwc3 *dwc);
1155 void dwc3_gadget_exit(struct dwc3 *dwc);
1156 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1157 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1158 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1159 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1160 struct dwc3_gadget_ep_cmd_params *params);
1161 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1163 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1165 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1167 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1169 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1171 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1172 enum dwc3_link_state state)
1175 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1176 struct dwc3_gadget_ep_cmd_params *params)
1178 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1183 /* power management interface */
1184 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1185 int dwc3_gadget_suspend(struct dwc3 *dwc);
1186 int dwc3_gadget_resume(struct dwc3 *dwc);
1187 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1189 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1194 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1199 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1202 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1204 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1205 int dwc3_ulpi_init(struct dwc3 *dwc);
1206 void dwc3_ulpi_exit(struct dwc3 *dwc);
1208 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1210 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1214 #endif /* __DRIVERS_USB_DWC3_CORE_H */