core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38
  39 #include "debug.h"
  40
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81
  82                 /*
  83                  * dwc_usb31 does not support OTG mode. If the controller
  84                  * supports DRD but the dr_mode is not specified or set to OTG,
  85                  * then set the mode to peripheral.
  86                  */
  87                 if (mode == USB_DR_MODE_OTG && dwc3_is_usb31(dwc))
  88                         mode = USB_DR_MODE_PERIPHERAL;
  89         }
  90
  91         if (mode != dwc->dr_mode) {
  92                 dev_warn(dev,
  93                          "Configuration mismatch. dr_mode forced to %s\n",
  94                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  95
  96                 dwc->dr_mode = mode;
  97         }
  98
  99         return 0;
 100 }
 101
 102 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 103 {
 104         u32 reg;
 105
 106         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 107         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 108         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 109         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 110
 111         dwc->current_dr_role = mode;
 112 }
 113
 114 static void __dwc3_set_mode(struct work_struct *work)
 115 {
 116         struct dwc3 *dwc = work_to_dwc(work);
 117         unsigned long flags;
 118         int ret;
 119
 120         if (dwc->dr_mode != USB_DR_MODE_OTG)
 121                 return;
 122
 123         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 124                 dwc3_otg_update(dwc, 0);
 125
 126         if (!dwc->desired_dr_role)
 127                 return;
 128
 129         if (dwc->desired_dr_role == dwc->current_dr_role)
 130                 return;
 131
 132         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 133                 return;
 134
 135         switch (dwc->current_dr_role) {
 136         case DWC3_GCTL_PRTCAP_HOST:
 137                 dwc3_host_exit(dwc);
 138                 break;
 139         case DWC3_GCTL_PRTCAP_DEVICE:
 140                 dwc3_gadget_exit(dwc);
 141                 dwc3_event_buffers_cleanup(dwc);
 142                 break;
 143         case DWC3_GCTL_PRTCAP_OTG:
 144                 dwc3_otg_exit(dwc);
 145                 spin_lock_irqsave(&dwc->lock, flags);
 146                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 147                 spin_unlock_irqrestore(&dwc->lock, flags);
 148                 dwc3_otg_update(dwc, 1);
 149                 break;
 150         default:
 151                 break;
 152         }
 153
 154         spin_lock_irqsave(&dwc->lock, flags);
 155
 156         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 157
 158         spin_unlock_irqrestore(&dwc->lock, flags);
 159
 160         switch (dwc->desired_dr_role) {
 161         case DWC3_GCTL_PRTCAP_HOST:
 162                 ret = dwc3_host_init(dwc);
 163                 if (ret) {
 164                         dev_err(dwc->dev, "failed to initialize host\n");
 165                 } else {
 166                         if (dwc->usb2_phy)
 167                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 168                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 169                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 170                         phy_calibrate(dwc->usb2_generic_phy);
 171                 }
 172                 break;
 173         case DWC3_GCTL_PRTCAP_DEVICE:
 174                 dwc3_event_buffers_setup(dwc);
 175
 176                 if (dwc->usb2_phy)
 177                         otg_set_vbus(dwc->usb2_phy->otg, false);
 178                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 179                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 180
 181                 ret = dwc3_gadget_init(dwc);
 182                 if (ret)
 183                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 184                 break;
 185         case DWC3_GCTL_PRTCAP_OTG:
 186                 dwc3_otg_init(dwc);
 187                 dwc3_otg_update(dwc, 0);
 188                 break;
 189         default:
 190                 break;
 191         }
 192
 193 }
 194
 195 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 196 {
 197         unsigned long flags;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         dwc->desired_dr_role = mode;
 201         spin_unlock_irqrestore(&dwc->lock, flags);
 202
 203         queue_work(system_freezable_wq, &dwc->drd_work);
 204 }
 205
 206 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 207 {
 208         struct dwc3             *dwc = dep->dwc;
 209         u32                     reg;
 210
 211         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 212                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 213                         DWC3_GDBGFIFOSPACE_TYPE(type));
 214
 215         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 216
 217         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 218 }
 219
 220 /**
 221  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 222  * @dwc: pointer to our context structure
 223  */
 224 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 225 {
 226         u32             reg;
 227         int             retries = 1000;
 228         int             ret;
 229
 230         usb_phy_init(dwc->usb2_phy);
 231         usb_phy_init(dwc->usb3_phy);
 232         ret = phy_init(dwc->usb2_generic_phy);
 233         if (ret < 0)
 234                 return ret;
 235
 236         ret = phy_init(dwc->usb3_generic_phy);
 237         if (ret < 0) {
 238                 phy_exit(dwc->usb2_generic_phy);
 239                 return ret;
 240         }
 241
 242         /*
 243          * We're resetting only the device side because, if we're in host mode,
 244          * XHCI driver will reset the host block. If dwc3 was configured for
 245          * host-only mode, then we can return early.
 246          */
 247         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 248                 return 0;
 249
 250         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 251         reg |= DWC3_DCTL_CSFTRST;
 252         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 253
 254         do {
 255                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 256                 if (!(reg & DWC3_DCTL_CSFTRST))
 257                         goto done;
 258
 259                 udelay(1);
 260         } while (--retries);
 261
 262         phy_exit(dwc->usb3_generic_phy);
 263         phy_exit(dwc->usb2_generic_phy);
 264
 265         return -ETIMEDOUT;
 266
 267 done:
 268         /*
 269          * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
 270          * we must wait at least 50ms before accessing the PHY domain
 271          * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
 272          */
 273         if (dwc3_is_usb31(dwc))
 274                 msleep(50);
 275
 276         return 0;
 277 }
 278
 279 static const struct clk_bulk_data dwc3_core_clks[] = {
 280         { .id = "ref" },
 281         { .id = "bus_early" },
 282         { .id = "suspend" },
 283 };
 284
 285 /*
 286  * dwc3_frame_length_adjustment - Adjusts frame length if required
 287  * @dwc3: Pointer to our controller context structure
 288  */
 289 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 290 {
 291         u32 reg;
 292         u32 dft;
 293
 294         if (dwc->revision < DWC3_REVISION_250A)
 295                 return;
 296
 297         if (dwc->fladj == 0)
 298                 return;
 299
 300         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 301         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 302         if (dft != dwc->fladj) {
 303                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 304                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 305                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 306         }
 307 }
 308
 309 /**
 310  * dwc3_free_one_event_buffer - Frees one event buffer
 311  * @dwc: Pointer to our controller context structure
 312  * @evt: Pointer to event buffer to be freed
 313  */
 314 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 315                 struct dwc3_event_buffer *evt)
 316 {
 317         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 318 }
 319
 320 /**
 321  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 322  * @dwc: Pointer to our controller context structure
 323  * @length: size of the event buffer
 324  *
 325  * Returns a pointer to the allocated event buffer structure on success
 326  * otherwise ERR_PTR(errno).
 327  */
 328 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 329                 unsigned length)
 330 {
 331         struct dwc3_event_buffer        *evt;
 332
 333         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 334         if (!evt)
 335                 return ERR_PTR(-ENOMEM);
 336
 337         evt->dwc        = dwc;
 338         evt->length     = length;
 339         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 340         if (!evt->cache)
 341                 return ERR_PTR(-ENOMEM);
 342
 343         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 344                         &evt->dma, GFP_KERNEL);
 345         if (!evt->buf)
 346                 return ERR_PTR(-ENOMEM);
 347
 348         return evt;
 349 }
 350
 351 /**
 352  * dwc3_free_event_buffers - frees all allocated event buffers
 353  * @dwc: Pointer to our controller context structure
 354  */
 355 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 356 {
 357         struct dwc3_event_buffer        *evt;
 358
 359         evt = dwc->ev_buf;
 360         if (evt)
 361                 dwc3_free_one_event_buffer(dwc, evt);
 362 }
 363
 364 /**
 365  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 366  * @dwc: pointer to our controller context structure
 367  * @length: size of event buffer
 368  *
 369  * Returns 0 on success otherwise negative errno. In the error case, dwc
 370  * may contain some buffers allocated but not all which were requested.
 371  */
 372 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 373 {
 374         struct dwc3_event_buffer *evt;
 375
 376         evt = dwc3_alloc_one_event_buffer(dwc, length);
 377         if (IS_ERR(evt)) {
 378                 dev_err(dwc->dev, "can't allocate event buffer\n");
 379                 return PTR_ERR(evt);
 380         }
 381         dwc->ev_buf = evt;
 382
 383         return 0;
 384 }
 385
 386 /**
 387  * dwc3_event_buffers_setup - setup our allocated event buffers
 388  * @dwc: pointer to our controller context structure
 389  *
 390  * Returns 0 on success otherwise negative errno.
 391  */
 392 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 393 {
 394         struct dwc3_event_buffer        *evt;
 395
 396         evt = dwc->ev_buf;
 397         evt->lpos = 0;
 398         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 399                         lower_32_bits(evt->dma));
 400         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 401                         upper_32_bits(evt->dma));
 402         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 403                         DWC3_GEVNTSIZ_SIZE(evt->length));
 404         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 405
 406         return 0;
 407 }
 408
 409 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 410 {
 411         struct dwc3_event_buffer        *evt;
 412
 413         evt = dwc->ev_buf;
 414
 415         evt->lpos = 0;
 416
 417         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 418         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 419         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 420                         | DWC3_GEVNTSIZ_SIZE(0));
 421         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 422 }
 423
 424 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 425 {
 426         if (!dwc->has_hibernation)
 427                 return 0;
 428
 429         if (!dwc->nr_scratch)
 430                 return 0;
 431
 432         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 433                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 434         if (!dwc->scratchbuf)
 435                 return -ENOMEM;
 436
 437         return 0;
 438 }
 439
 440 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 441 {
 442         dma_addr_t scratch_addr;
 443         u32 param;
 444         int ret;
 445
 446         if (!dwc->has_hibernation)
 447                 return 0;
 448
 449         if (!dwc->nr_scratch)
 450                 return 0;
 451
 452          /* should never fall here */
 453         if (!WARN_ON(dwc->scratchbuf))
 454                 return 0;
 455
 456         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 457                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 458                         DMA_BIDIRECTIONAL);
 459         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 460                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 461                 ret = -EFAULT;
 462                 goto err0;
 463         }
 464
 465         dwc->scratch_addr = scratch_addr;
 466
 467         param = lower_32_bits(scratch_addr);
 468
 469         ret = dwc3_send_gadget_generic_command(dwc,
 470                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 471         if (ret < 0)
 472                 goto err1;
 473
 474         param = upper_32_bits(scratch_addr);
 475
 476         ret = dwc3_send_gadget_generic_command(dwc,
 477                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 478         if (ret < 0)
 479                 goto err1;
 480
 481         return 0;
 482
 483 err1:
 484         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 485                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 486
 487 err0:
 488         return ret;
 489 }
 490
 491 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 492 {
 493         if (!dwc->has_hibernation)
 494                 return;
 495
 496         if (!dwc->nr_scratch)
 497                 return;
 498
 499          /* should never fall here */
 500         if (!WARN_ON(dwc->scratchbuf))
 501                 return;
 502
 503         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 504                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 505         kfree(dwc->scratchbuf);
 506 }
 507
 508 static void dwc3_core_num_eps(struct dwc3 *dwc)
 509 {
 510         struct dwc3_hwparams    *parms = &dwc->hwparams;
 511
 512         dwc->num_eps = DWC3_NUM_EPS(parms);
 513 }
 514
 515 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 516 {
 517         struct dwc3_hwparams    *parms = &dwc->hwparams;
 518
 519         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 520         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 521         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 522         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 523         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 524         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 525         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 526         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 527         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 528 }
 529
 530 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 531 {
 532         int intf;
 533         int ret = 0;
 534
 535         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 536
 537         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 538             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 539              dwc->hsphy_interface &&
 540              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 541                 ret = dwc3_ulpi_init(dwc);
 542
 543         return ret;
 544 }
 545
 546 /**
 547  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 548  * @dwc: Pointer to our controller context structure
 549  *
 550  * Returns 0 on success. The USB PHY interfaces are configured but not
 551  * initialized. The PHY interfaces and the PHYs get initialized together with
 552  * the core in dwc3_core_init.
 553  */
 554 static int dwc3_phy_setup(struct dwc3 *dwc)
 555 {
 556         u32 reg;
 557
 558         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 559
 560         /*
 561          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 562          * PHYs. Also, this bit is not supposed to be used in normal operation.
 563          */
 564         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 565
 566         /*
 567          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 568          * to '0' during coreConsultant configuration. So default value
 569          * will be '0' when the core is reset. Application needs to set it
 570          * to '1' after the core initialization is completed.
 571          */
 572         if (dwc->revision > DWC3_REVISION_194A)
 573                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 574
 575         if (dwc->u2ss_inp3_quirk)
 576                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 577
 578         if (dwc->dis_rxdet_inp3_quirk)
 579                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 580
 581         if (dwc->req_p1p2p3_quirk)
 582                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 583
 584         if (dwc->del_p1p2p3_quirk)
 585                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 586
 587         if (dwc->del_phy_power_chg_quirk)
 588                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 589
 590         if (dwc->lfps_filter_quirk)
 591                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 592
 593         if (dwc->rx_detect_poll_quirk)
 594                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 595
 596         if (dwc->tx_de_emphasis_quirk)
 597                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 598
 599         if (dwc->dis_u3_susphy_quirk)
 600                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 601
 602         if (dwc->dis_del_phy_power_chg_quirk)
 603                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 604
 605         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 606
 607         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 608
 609         /* Select the HS PHY interface */
 610         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 611         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 612                 if (dwc->hsphy_interface &&
 613                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 614                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 615                         break;
 616                 } else if (dwc->hsphy_interface &&
 617                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 618                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 619                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 620                 } else {
 621                         /* Relying on default value. */
 622                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 623                                 break;
 624                 }
 625                 /* FALLTHROUGH */
 626         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 627                 /* FALLTHROUGH */
 628         default:
 629                 break;
 630         }
 631
 632         switch (dwc->hsphy_mode) {
 633         case USBPHY_INTERFACE_MODE_UTMI:
 634                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 635                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 636                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 637                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 638                 break;
 639         case USBPHY_INTERFACE_MODE_UTMIW:
 640                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 641                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 642                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 643                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 644                 break;
 645         default:
 646                 break;
 647         }
 648
 649         /*
 650          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 651          * '0' during coreConsultant configuration. So default value will
 652          * be '0' when the core is reset. Application needs to set it to
 653          * '1' after the core initialization is completed.
 654          */
 655         if (dwc->revision > DWC3_REVISION_194A)
 656                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 657
 658         if (dwc->dis_u2_susphy_quirk)
 659                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 660
 661         if (dwc->dis_enblslpm_quirk)
 662                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 663
 664         if (dwc->dis_u2_freeclk_exists_quirk)
 665                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 666
 667         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 668
 669         return 0;
 670 }
 671
 672 static void dwc3_core_exit(struct dwc3 *dwc)
 673 {
 674         dwc3_event_buffers_cleanup(dwc);
 675
 676         usb_phy_shutdown(dwc->usb2_phy);
 677         usb_phy_shutdown(dwc->usb3_phy);
 678         phy_exit(dwc->usb2_generic_phy);
 679         phy_exit(dwc->usb3_generic_phy);
 680
 681         usb_phy_set_suspend(dwc->usb2_phy, 1);
 682         usb_phy_set_suspend(dwc->usb3_phy, 1);
 683         phy_power_off(dwc->usb2_generic_phy);
 684         phy_power_off(dwc->usb3_generic_phy);
 685         clk_bulk_disable(dwc->num_clks, dwc->clks);
 686         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
 687         reset_control_assert(dwc->reset);
 688 }
 689
 690 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 691 {
 692         u32 reg;
 693
 694         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 695
 696         /* This should read as U3 followed by revision number */
 697         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 698                 /* Detected DWC_usb3 IP */
 699                 dwc->revision = reg;
 700         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 701                 /* Detected DWC_usb31 IP */
 702                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 703                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 704         } else {
 705                 return false;
 706         }
 707
 708         return true;
 709 }
 710
 711 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 712 {
 713         u32 hwparams4 = dwc->hwparams.hwparams4;
 714         u32 reg;
 715
 716         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 717         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 718
 719         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 720         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 721                 /**
 722                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 723                  * issue which would cause xHCI compliance tests to fail.
 724                  *
 725                  * Because of that we cannot enable clock gating on such
 726                  * configurations.
 727                  *
 728                  * Refers to:
 729                  *
 730                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 731                  * SOF/ITP Mode Used
 732                  */
 733                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 734                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 735                                 (dwc->revision >= DWC3_REVISION_210A &&
 736                                 dwc->revision <= DWC3_REVISION_250A))
 737                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 738                 else
 739                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 740                 break;
 741         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 742                 /* enable hibernation here */
 743                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 744
 745                 /*
 746                  * REVISIT Enabling this bit so that host-mode hibernation
 747                  * will work. Device-mode hibernation is not yet implemented.
 748                  */
 749                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 750                 break;
 751         default:
 752                 /* nothing */
 753                 break;
 754         }
 755
 756         /* check if current dwc3 is on simulation board */
 757         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 758                 dev_info(dwc->dev, "Running with FPGA optmizations\n");
 759                 dwc->is_fpga = true;
 760         }
 761
 762         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 763                         "disable_scramble cannot be used on non-FPGA builds\n");
 764
 765         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 766                 reg |= DWC3_GCTL_DISSCRAMBLE;
 767         else
 768                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 769
 770         if (dwc->u2exit_lfps_quirk)
 771                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 772
 773         /*
 774          * WORKAROUND: DWC3 revisions <1.90a have a bug
 775          * where the device can fail to connect at SuperSpeed
 776          * and falls back to high-speed mode which causes
 777          * the device to enter a Connect/Disconnect loop
 778          */
 779         if (dwc->revision < DWC3_REVISION_190A)
 780                 reg |= DWC3_GCTL_U2RSTECN;
 781
 782         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 783 }
 784
 785 static int dwc3_core_get_phy(struct dwc3 *dwc);
 786 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 787
 788 /* set global incr burst type configuration registers */
 789 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 790 {
 791         struct device *dev = dwc->dev;
 792         /* incrx_mode : for INCR burst type. */
 793         bool incrx_mode;
 794         /* incrx_size : for size of INCRX burst. */
 795         u32 incrx_size;
 796         u32 *vals;
 797         u32 cfg;
 798         int ntype;
 799         int ret;
 800         int i;
 801
 802         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 803
 804         /*
 805          * Handle property "snps,incr-burst-type-adjustment".
 806          * Get the number of value from this property:
 807          * result <= 0, means this property is not supported.
 808          * result = 1, means INCRx burst mode supported.
 809          * result > 1, means undefined length burst mode supported.
 810          */
 811         ntype = device_property_read_u32_array(dev,
 812                         "snps,incr-burst-type-adjustment", NULL, 0);
 813         if (ntype <= 0)
 814                 return;
 815
 816         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 817         if (!vals) {
 818                 dev_err(dev, "Error to get memory\n");
 819                 return;
 820         }
 821
 822         /* Get INCR burst type, and parse it */
 823         ret = device_property_read_u32_array(dev,
 824                         "snps,incr-burst-type-adjustment", vals, ntype);
 825         if (ret) {
 826                 dev_err(dev, "Error to get property\n");
 827                 return;
 828         }
 829
 830         incrx_size = *vals;
 831
 832         if (ntype > 1) {
 833                 /* INCRX (undefined length) burst mode */
 834                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 835                 for (i = 1; i < ntype; i++) {
 836                         if (vals[i] > incrx_size)
 837                                 incrx_size = vals[i];
 838                 }
 839         } else {
 840                 /* INCRX burst mode */
 841                 incrx_mode = INCRX_BURST_MODE;
 842         }
 843
 844         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 845         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 846         if (incrx_mode)
 847                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 848         switch (incrx_size) {
 849         case 256:
 850                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 851                 break;
 852         case 128:
 853                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 854                 break;
 855         case 64:
 856                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 857                 break;
 858         case 32:
 859                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 860                 break;
 861         case 16:
 862                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 863                 break;
 864         case 8:
 865                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 866                 break;
 867         case 4:
 868                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 869                 break;
 870         case 1:
 871                 break;
 872         default:
 873                 dev_err(dev, "Invalid property\n");
 874                 break;
 875         }
 876
 877         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 878 }
 879
 880 /**
 881  * dwc3_core_init - Low-level initialization of DWC3 Core
 882  * @dwc: Pointer to our controller context structure
 883  *
 884  * Returns 0 on success otherwise negative errno.
 885  */
 886 static int dwc3_core_init(struct dwc3 *dwc)
 887 {
 888         u32                     reg;
 889         int                     ret;
 890
 891         if (!dwc3_core_is_valid(dwc)) {
 892                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 893                 ret = -ENODEV;
 894                 goto err0;
 895         }
 896
 897         /*
 898          * Write Linux Version Code to our GUID register so it's easy to figure
 899          * out which kernel version a bug was found.
 900          */
 901         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 902
 903         /* Handle USB2.0-only core configuration */
 904         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 905                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 906                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 907                         dwc->maximum_speed = USB_SPEED_HIGH;
 908         }
 909
 910         ret = dwc3_phy_setup(dwc);
 911         if (ret)
 912                 goto err0;
 913
 914         if (!dwc->ulpi_ready) {
 915                 ret = dwc3_core_ulpi_init(dwc);
 916                 if (ret)
 917                         goto err0;
 918                 dwc->ulpi_ready = true;
 919         }
 920
 921         if (!dwc->phys_ready) {
 922                 ret = dwc3_core_get_phy(dwc);
 923                 if (ret)
 924                         goto err0a;
 925                 dwc->phys_ready = true;
 926         }
 927
 928         ret = dwc3_core_soft_reset(dwc);
 929         if (ret)
 930                 goto err0a;
 931
 932         dwc3_core_setup_global_control(dwc);
 933         dwc3_core_num_eps(dwc);
 934
 935         ret = dwc3_setup_scratch_buffers(dwc);
 936         if (ret)
 937                 goto err1;
 938
 939         /* Adjust Frame Length */
 940         dwc3_frame_length_adjustment(dwc);
 941
 942         dwc3_set_incr_burst_type(dwc);
 943
 944         usb_phy_set_suspend(dwc->usb2_phy, 0);
 945         usb_phy_set_suspend(dwc->usb3_phy, 0);
 946         ret = phy_power_on(dwc->usb2_generic_phy);
 947         if (ret < 0)
 948                 goto err2;
 949
 950         ret = phy_power_on(dwc->usb3_generic_phy);
 951         if (ret < 0)
 952                 goto err3;
 953
 954         ret = dwc3_event_buffers_setup(dwc);
 955         if (ret) {
 956                 dev_err(dwc->dev, "failed to setup event buffers\n");
 957                 goto err4;
 958         }
 959
 960         /*
 961          * ENDXFER polling is available on version 3.10a and later of
 962          * the DWC_usb3 controller. It is NOT available in the
 963          * DWC_usb31 controller.
 964          */
 965         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
 966                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
 967                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
 968                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
 969         }
 970
 971         if (dwc->revision >= DWC3_REVISION_250A) {
 972                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
 973
 974                 /*
 975                  * Enable hardware control of sending remote wakeup
 976                  * in HS when the device is in the L1 state.
 977                  */
 978                 if (dwc->revision >= DWC3_REVISION_290A)
 979                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
 980
 981                 if (dwc->dis_tx_ipgap_linecheck_quirk)
 982                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
 983
 984                 if (dwc->parkmode_disable_ss_quirk)
 985                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
 986
 987                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 988         }
 989
 990         if (dwc->dr_mode == USB_DR_MODE_HOST ||
 991             dwc->dr_mode == USB_DR_MODE_OTG) {
 992                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 993
 994                 /*
 995                  * Enable Auto retry Feature to make the controller operating in
 996                  * Host mode on seeing transaction errors(CRC errors or internal
 997                  * overrun scenerios) on IN transfers to reply to the device
 998                  * with a non-terminating retry ACK (i.e, an ACK transcation
 999                  * packet with Retry=1 & Nump != 0)
1000                  */
1001                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1002
1003                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1004         }
1005
1006         /*
1007          * Must config both number of packets and max burst settings to enable
1008          * RX and/or TX threshold.
1009          */
1010         if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1011                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1012                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1013                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1014                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1015
1016                 if (rx_thr_num && rx_maxburst) {
1017                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1018                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1019
1020                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1021                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1022
1023                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1024                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1025
1026                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1027                 }
1028
1029                 if (tx_thr_num && tx_maxburst) {
1030                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1031                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1032
1033                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1034                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1035
1036                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1037                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1038
1039                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1040                 }
1041         }
1042
1043         return 0;
1044
1045 err4:
1046         phy_power_off(dwc->usb3_generic_phy);
1047
1048 err3:
1049         phy_power_off(dwc->usb2_generic_phy);
1050
1051 err2:
1052         usb_phy_set_suspend(dwc->usb2_phy, 1);
1053         usb_phy_set_suspend(dwc->usb3_phy, 1);
1054
1055 err1:
1056         usb_phy_shutdown(dwc->usb2_phy);
1057         usb_phy_shutdown(dwc->usb3_phy);
1058         phy_exit(dwc->usb2_generic_phy);
1059         phy_exit(dwc->usb3_generic_phy);
1060
1061 err0a:
1062         dwc3_ulpi_exit(dwc);
1063
1064 err0:
1065         return ret;
1066 }
1067
1068 static int dwc3_core_get_phy(struct dwc3 *dwc)
1069 {
1070         struct device           *dev = dwc->dev;
1071         struct device_node      *node = dev->of_node;
1072         int ret;
1073
1074         if (node) {
1075                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1076                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1077         } else {
1078                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1079                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1080         }
1081
1082         if (IS_ERR(dwc->usb2_phy)) {
1083                 ret = PTR_ERR(dwc->usb2_phy);
1084                 if (ret == -ENXIO || ret == -ENODEV) {
1085                         dwc->usb2_phy = NULL;
1086                 } else if (ret == -EPROBE_DEFER) {
1087                         return ret;
1088                 } else {
1089                         dev_err(dev, "no usb2 phy configured\n");
1090                         return ret;
1091                 }
1092         }
1093
1094         if (IS_ERR(dwc->usb3_phy)) {
1095                 ret = PTR_ERR(dwc->usb3_phy);
1096                 if (ret == -ENXIO || ret == -ENODEV) {
1097                         dwc->usb3_phy = NULL;
1098                 } else if (ret == -EPROBE_DEFER) {
1099                         return ret;
1100                 } else {
1101                         dev_err(dev, "no usb3 phy configured\n");
1102                         return ret;
1103                 }
1104         }
1105
1106         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1107         if (IS_ERR(dwc->usb2_generic_phy)) {
1108                 ret = PTR_ERR(dwc->usb2_generic_phy);
1109                 if (ret == -ENOSYS || ret == -ENODEV) {
1110                         dwc->usb2_generic_phy = NULL;
1111                 } else if (ret == -EPROBE_DEFER) {
1112                         return ret;
1113                 } else {
1114                         dev_err(dev, "no usb2 phy configured\n");
1115                         return ret;
1116                 }
1117         }
1118
1119         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1120         if (IS_ERR(dwc->usb3_generic_phy)) {
1121                 ret = PTR_ERR(dwc->usb3_generic_phy);
1122                 if (ret == -ENOSYS || ret == -ENODEV) {
1123                         dwc->usb3_generic_phy = NULL;
1124                 } else if (ret == -EPROBE_DEFER) {
1125                         return ret;
1126                 } else {
1127                         dev_err(dev, "no usb3 phy configured\n");
1128                         return ret;
1129                 }
1130         }
1131
1132         return 0;
1133 }
1134
1135 static int dwc3_core_init_mode(struct dwc3 *dwc)
1136 {
1137         struct device *dev = dwc->dev;
1138         int ret;
1139
1140         switch (dwc->dr_mode) {
1141         case USB_DR_MODE_PERIPHERAL:
1142                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1143
1144                 if (dwc->usb2_phy)
1145                         otg_set_vbus(dwc->usb2_phy->otg, false);
1146                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1147                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1148
1149                 ret = dwc3_gadget_init(dwc);
1150                 if (ret) {
1151                         if (ret != -EPROBE_DEFER)
1152                                 dev_err(dev, "failed to initialize gadget\n");
1153                         return ret;
1154                 }
1155                 break;
1156         case USB_DR_MODE_HOST:
1157                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1158
1159                 if (dwc->usb2_phy)
1160                         otg_set_vbus(dwc->usb2_phy->otg, true);
1161                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1162                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1163
1164                 ret = dwc3_host_init(dwc);
1165                 if (ret) {
1166                         if (ret != -EPROBE_DEFER)
1167                                 dev_err(dev, "failed to initialize host\n");
1168                         return ret;
1169                 }
1170                 phy_calibrate(dwc->usb2_generic_phy);
1171                 break;
1172         case USB_DR_MODE_OTG:
1173                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1174                 ret = dwc3_drd_init(dwc);
1175                 if (ret) {
1176                         if (ret != -EPROBE_DEFER)
1177                                 dev_err(dev, "failed to initialize dual-role\n");
1178                         return ret;
1179                 }
1180                 break;
1181         default:
1182                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1183                 return -EINVAL;
1184         }
1185
1186         return 0;
1187 }
1188
1189 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1190 {
1191         switch (dwc->dr_mode) {
1192         case USB_DR_MODE_PERIPHERAL:
1193                 dwc3_gadget_exit(dwc);
1194                 break;
1195         case USB_DR_MODE_HOST:
1196                 dwc3_host_exit(dwc);
1197                 break;
1198         case USB_DR_MODE_OTG:
1199                 dwc3_drd_exit(dwc);
1200                 break;
1201         default:
1202                 /* do nothing */
1203                 break;
1204         }
1205
1206         /* de-assert DRVVBUS for HOST and OTG mode */
1207         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1208 }
1209
1210 static void dwc3_get_properties(struct dwc3 *dwc)
1211 {
1212         struct device           *dev = dwc->dev;
1213         u8                      lpm_nyet_threshold;
1214         u8                      tx_de_emphasis;
1215         u8                      hird_threshold;
1216         u8                      rx_thr_num_pkt_prd;
1217         u8                      rx_max_burst_prd;
1218         u8                      tx_thr_num_pkt_prd;
1219         u8                      tx_max_burst_prd;
1220
1221         /* default to highest possible threshold */
1222         lpm_nyet_threshold = 0xf;
1223
1224         /* default to -3.5dB de-emphasis */
1225         tx_de_emphasis = 1;
1226
1227         /*
1228          * default to assert utmi_sleep_n and use maximum allowed HIRD
1229          * threshold value of 0b1100
1230          */
1231         hird_threshold = 12;
1232
1233         dwc->maximum_speed = usb_get_maximum_speed(dev);
1234         dwc->dr_mode = usb_get_dr_mode(dev);
1235         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1236
1237         dwc->sysdev_is_parent = device_property_read_bool(dev,
1238                                 "linux,sysdev_is_parent");
1239         if (dwc->sysdev_is_parent)
1240                 dwc->sysdev = dwc->dev->parent;
1241         else
1242                 dwc->sysdev = dwc->dev;
1243
1244         dwc->has_lpm_erratum = device_property_read_bool(dev,
1245                                 "snps,has-lpm-erratum");
1246         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1247                                 &lpm_nyet_threshold);
1248         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1249                                 "snps,is-utmi-l1-suspend");
1250         device_property_read_u8(dev, "snps,hird-threshold",
1251                                 &hird_threshold);
1252         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1253                                 "snps,usb3_lpm_capable");
1254         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1255                                 &rx_thr_num_pkt_prd);
1256         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1257                                 &rx_max_burst_prd);
1258         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1259                                 &tx_thr_num_pkt_prd);
1260         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1261                                 &tx_max_burst_prd);
1262
1263         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1264                                 "snps,disable_scramble_quirk");
1265         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1266                                 "snps,u2exit_lfps_quirk");
1267         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1268                                 "snps,u2ss_inp3_quirk");
1269         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1270                                 "snps,req_p1p2p3_quirk");
1271         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1272                                 "snps,del_p1p2p3_quirk");
1273         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1274                                 "snps,del_phy_power_chg_quirk");
1275         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1276                                 "snps,lfps_filter_quirk");
1277         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1278                                 "snps,rx_detect_poll_quirk");
1279         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1280                                 "snps,dis_u3_susphy_quirk");
1281         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1282                                 "snps,dis_u2_susphy_quirk");
1283         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1284                                 "snps,dis_enblslpm_quirk");
1285         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1286                                 "snps,dis_rxdet_inp3_quirk");
1287         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1288                                 "snps,dis-u2-freeclk-exists-quirk");
1289         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1290                                 "snps,dis-del-phy-power-chg-quirk");
1291         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1292                                 "snps,dis-tx-ipgap-linecheck-quirk");
1293         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1294                                 "snps,parkmode-disable-ss-quirk");
1295
1296         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1297                                 "snps,tx_de_emphasis_quirk");
1298         device_property_read_u8(dev, "snps,tx_de_emphasis",
1299                                 &tx_de_emphasis);
1300         device_property_read_string(dev, "snps,hsphy_interface",
1301                                     &dwc->hsphy_interface);
1302         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1303                                  &dwc->fladj);
1304
1305         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1306                                 "snps,dis_metastability_quirk");
1307
1308         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1309         dwc->tx_de_emphasis = tx_de_emphasis;
1310
1311         dwc->hird_threshold = hird_threshold
1312                 | (dwc->is_utmi_l1_suspend << 4);
1313
1314         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1315         dwc->rx_max_burst_prd = rx_max_burst_prd;
1316
1317         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1318         dwc->tx_max_burst_prd = tx_max_burst_prd;
1319
1320         dwc->imod_interval = 0;
1321 }
1322
1323 /* check whether the core supports IMOD */
1324 bool dwc3_has_imod(struct dwc3 *dwc)
1325 {
1326         return ((dwc3_is_usb3(dwc) &&
1327                  dwc->revision >= DWC3_REVISION_300A) ||
1328                 (dwc3_is_usb31(dwc) &&
1329                  dwc->revision >= DWC3_USB31_REVISION_120A));
1330 }
1331
1332 static void dwc3_check_params(struct dwc3 *dwc)
1333 {
1334         struct device *dev = dwc->dev;
1335
1336         /* Check for proper value of imod_interval */
1337         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1338                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1339                 dwc->imod_interval = 0;
1340         }
1341
1342         /*
1343          * Workaround for STAR 9000961433 which affects only version
1344          * 3.00a of the DWC_usb3 core. This prevents the controller
1345          * interrupt from being masked while handling events. IMOD
1346          * allows us to work around this issue. Enable it for the
1347          * affected version.
1348          */
1349         if (!dwc->imod_interval &&
1350             (dwc->revision == DWC3_REVISION_300A))
1351                 dwc->imod_interval = 1;
1352
1353         /* Check the maximum_speed parameter */
1354         switch (dwc->maximum_speed) {
1355         case USB_SPEED_LOW:
1356         case USB_SPEED_FULL:
1357         case USB_SPEED_HIGH:
1358         case USB_SPEED_SUPER:
1359         case USB_SPEED_SUPER_PLUS:
1360                 break;
1361         default:
1362                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1363                         dwc->maximum_speed);
1364                 /* fall through */
1365         case USB_SPEED_UNKNOWN:
1366                 /* default to superspeed */
1367                 dwc->maximum_speed = USB_SPEED_SUPER;
1368
1369                 /*
1370                  * default to superspeed plus if we are capable.
1371                  */
1372                 if (dwc3_is_usb31(dwc) &&
1373                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1374                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1375                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1376
1377                 break;
1378         }
1379 }
1380
1381 static int dwc3_probe(struct platform_device *pdev)
1382 {
1383         struct device           *dev = &pdev->dev;
1384         struct resource         *res, dwc_res;
1385         struct dwc3             *dwc;
1386
1387         int                     ret;
1388
1389         void __iomem            *regs;
1390
1391         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1392         if (!dwc)
1393                 return -ENOMEM;
1394
1395         dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1396                                  GFP_KERNEL);
1397         if (!dwc->clks)
1398                 return -ENOMEM;
1399
1400         dwc->dev = dev;
1401
1402         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1403         if (!res) {
1404                 dev_err(dev, "missing memory resource\n");
1405                 return -ENODEV;
1406         }
1407
1408         dwc->xhci_resources[0].start = res->start;
1409         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1410                                         DWC3_XHCI_REGS_END;
1411         dwc->xhci_resources[0].flags = res->flags;
1412         dwc->xhci_resources[0].name = res->name;
1413
1414         /*
1415          * Request memory region but exclude xHCI regs,
1416          * since it will be requested by the xhci-plat driver.
1417          */
1418         dwc_res = *res;
1419         dwc_res.start += DWC3_GLOBALS_REGS_START;
1420
1421         regs = devm_ioremap_resource(dev, &dwc_res);
1422         if (IS_ERR(regs))
1423                 return PTR_ERR(regs);
1424
1425         dwc->regs       = regs;
1426         dwc->regs_size  = resource_size(&dwc_res);
1427
1428         dwc3_get_properties(dwc);
1429
1430         dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1431         if (IS_ERR(dwc->reset))
1432                 return PTR_ERR(dwc->reset);
1433
1434         if (dev->of_node) {
1435                 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1436
1437                 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1438                 if (ret == -EPROBE_DEFER)
1439                         return ret;
1440                 /*
1441                  * Clocks are optional, but new DT platforms should support all
1442                  * clocks as required by the DT-binding.
1443                  */
1444                 if (ret)
1445                         dwc->num_clks = 0;
1446         }
1447
1448         ret = reset_control_deassert(dwc->reset);
1449         if (ret)
1450                 goto put_clks;
1451
1452         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1453         if (ret)
1454                 goto assert_reset;
1455
1456         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1457         if (ret)
1458                 goto unprepare_clks;
1459
1460         platform_set_drvdata(pdev, dwc);
1461         dwc3_cache_hwparams(dwc);
1462
1463         spin_lock_init(&dwc->lock);
1464
1465         pm_runtime_set_active(dev);
1466         pm_runtime_use_autosuspend(dev);
1467         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1468         pm_runtime_enable(dev);
1469         ret = pm_runtime_get_sync(dev);
1470         if (ret < 0)
1471                 goto err1;
1472
1473         pm_runtime_forbid(dev);
1474
1475         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1476         if (ret) {
1477                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1478                 ret = -ENOMEM;
1479                 goto err2;
1480         }
1481
1482         ret = dwc3_get_dr_mode(dwc);
1483         if (ret)
1484                 goto err3;
1485
1486         ret = dwc3_alloc_scratch_buffers(dwc);
1487         if (ret)
1488                 goto err3;
1489
1490         ret = dwc3_core_init(dwc);
1491         if (ret) {
1492                 if (ret != -EPROBE_DEFER)
1493                         dev_err(dev, "failed to initialize core: %d\n", ret);
1494                 goto err4;
1495         }
1496
1497         dwc3_check_params(dwc);
1498         dwc3_debugfs_init(dwc);
1499
1500         ret = dwc3_core_init_mode(dwc);
1501         if (ret)
1502                 goto err5;
1503
1504         pm_runtime_put(dev);
1505
1506         return 0;
1507
1508 err5:
1509         dwc3_debugfs_exit(dwc);
1510         dwc3_event_buffers_cleanup(dwc);
1511
1512         usb_phy_shutdown(dwc->usb2_phy);
1513         usb_phy_shutdown(dwc->usb3_phy);
1514         phy_exit(dwc->usb2_generic_phy);
1515         phy_exit(dwc->usb3_generic_phy);
1516
1517         usb_phy_set_suspend(dwc->usb2_phy, 1);
1518         usb_phy_set_suspend(dwc->usb3_phy, 1);
1519         phy_power_off(dwc->usb2_generic_phy);
1520         phy_power_off(dwc->usb3_generic_phy);
1521
1522         dwc3_ulpi_exit(dwc);
1523
1524 err4:
1525         dwc3_free_scratch_buffers(dwc);
1526
1527 err3:
1528         dwc3_free_event_buffers(dwc);
1529
1530 err2:
1531         pm_runtime_allow(&pdev->dev);
1532
1533 err1:
1534         pm_runtime_put_sync(&pdev->dev);
1535         pm_runtime_disable(&pdev->dev);
1536
1537         clk_bulk_disable(dwc->num_clks, dwc->clks);
1538 unprepare_clks:
1539         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1540 assert_reset:
1541         reset_control_assert(dwc->reset);
1542 put_clks:
1543         clk_bulk_put(dwc->num_clks, dwc->clks);
1544
1545         return ret;
1546 }
1547
1548 static int dwc3_remove(struct platform_device *pdev)
1549 {
1550         struct dwc3     *dwc = platform_get_drvdata(pdev);
1551
1552         pm_runtime_get_sync(&pdev->dev);
1553
1554         dwc3_core_exit_mode(dwc);
1555         dwc3_debugfs_exit(dwc);
1556
1557         dwc3_core_exit(dwc);
1558         dwc3_ulpi_exit(dwc);
1559
1560         pm_runtime_disable(&pdev->dev);
1561         pm_runtime_put_noidle(&pdev->dev);
1562         pm_runtime_set_suspended(&pdev->dev);
1563
1564         dwc3_free_event_buffers(dwc);
1565         dwc3_free_scratch_buffers(dwc);
1566         clk_bulk_put(dwc->num_clks, dwc->clks);
1567
1568         return 0;
1569 }
1570
1571 #ifdef CONFIG_PM
1572 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1573 {
1574         int ret;
1575
1576         ret = reset_control_deassert(dwc->reset);
1577         if (ret)
1578                 return ret;
1579
1580         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1581         if (ret)
1582                 goto assert_reset;
1583
1584         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1585         if (ret)
1586                 goto unprepare_clks;
1587
1588         ret = dwc3_core_init(dwc);
1589         if (ret)
1590                 goto disable_clks;
1591
1592         return 0;
1593
1594 disable_clks:
1595         clk_bulk_disable(dwc->num_clks, dwc->clks);
1596 unprepare_clks:
1597         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1598 assert_reset:
1599         reset_control_assert(dwc->reset);
1600
1601         return ret;
1602 }
1603
1604 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1605 {
1606         unsigned long   flags;
1607         u32 reg;
1608
1609         switch (dwc->current_dr_role) {
1610         case DWC3_GCTL_PRTCAP_DEVICE:
1611                 spin_lock_irqsave(&dwc->lock, flags);
1612                 dwc3_gadget_suspend(dwc);
1613                 spin_unlock_irqrestore(&dwc->lock, flags);
1614                 synchronize_irq(dwc->irq_gadget);
1615                 dwc3_core_exit(dwc);
1616                 break;
1617         case DWC3_GCTL_PRTCAP_HOST:
1618                 if (!PMSG_IS_AUTO(msg)) {
1619                         dwc3_core_exit(dwc);
1620                         break;
1621                 }
1622
1623                 /* Let controller to suspend HSPHY before PHY driver suspends */
1624                 if (dwc->dis_u2_susphy_quirk ||
1625                     dwc->dis_enblslpm_quirk) {
1626                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1627                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1628                                 DWC3_GUSB2PHYCFG_SUSPHY;
1629                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1630
1631                         /* Give some time for USB2 PHY to suspend */
1632                         usleep_range(5000, 6000);
1633                 }
1634
1635                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1636                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1637                 break;
1638         case DWC3_GCTL_PRTCAP_OTG:
1639                 /* do nothing during runtime_suspend */
1640                 if (PMSG_IS_AUTO(msg))
1641                         break;
1642
1643                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1644                         spin_lock_irqsave(&dwc->lock, flags);
1645                         dwc3_gadget_suspend(dwc);
1646                         spin_unlock_irqrestore(&dwc->lock, flags);
1647                         synchronize_irq(dwc->irq_gadget);
1648                 }
1649
1650                 dwc3_otg_exit(dwc);
1651                 dwc3_core_exit(dwc);
1652                 break;
1653         default:
1654                 /* do nothing */
1655                 break;
1656         }
1657
1658         return 0;
1659 }
1660
1661 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1662 {
1663         unsigned long   flags;
1664         int             ret;
1665         u32             reg;
1666
1667         switch (dwc->current_dr_role) {
1668         case DWC3_GCTL_PRTCAP_DEVICE:
1669                 ret = dwc3_core_init_for_resume(dwc);
1670                 if (ret)
1671                         return ret;
1672
1673                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1674                 spin_lock_irqsave(&dwc->lock, flags);
1675                 dwc3_gadget_resume(dwc);
1676                 spin_unlock_irqrestore(&dwc->lock, flags);
1677                 break;
1678         case DWC3_GCTL_PRTCAP_HOST:
1679                 if (!PMSG_IS_AUTO(msg)) {
1680                         ret = dwc3_core_init_for_resume(dwc);
1681                         if (ret)
1682                                 return ret;
1683                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1684                         break;
1685                 }
1686                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1687                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1688                 if (dwc->dis_u2_susphy_quirk)
1689                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1690
1691                 if (dwc->dis_enblslpm_quirk)
1692                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1693
1694                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1695
1696                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1697                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1698                 break;
1699         case DWC3_GCTL_PRTCAP_OTG:
1700                 /* nothing to do on runtime_resume */
1701                 if (PMSG_IS_AUTO(msg))
1702                         break;
1703
1704                 ret = dwc3_core_init_for_resume(dwc);
1705                 if (ret)
1706                         return ret;
1707
1708                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1709
1710                 dwc3_otg_init(dwc);
1711                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1712                         dwc3_otg_host_init(dwc);
1713                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1714                         spin_lock_irqsave(&dwc->lock, flags);
1715                         dwc3_gadget_resume(dwc);
1716                         spin_unlock_irqrestore(&dwc->lock, flags);
1717                 }
1718
1719                 break;
1720         default:
1721                 /* do nothing */
1722                 break;
1723         }
1724
1725         return 0;
1726 }
1727
1728 static int dwc3_runtime_checks(struct dwc3 *dwc)
1729 {
1730         switch (dwc->current_dr_role) {
1731         case DWC3_GCTL_PRTCAP_DEVICE:
1732                 if (dwc->connected)
1733                         return -EBUSY;
1734                 break;
1735         case DWC3_GCTL_PRTCAP_HOST:
1736         default:
1737                 /* do nothing */
1738                 break;
1739         }
1740
1741         return 0;
1742 }
1743
1744 static int dwc3_runtime_suspend(struct device *dev)
1745 {
1746         struct dwc3     *dwc = dev_get_drvdata(dev);
1747         int             ret;
1748
1749         if (dwc3_runtime_checks(dwc))
1750                 return -EBUSY;
1751
1752         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1753         if (ret)
1754                 return ret;
1755
1756         device_init_wakeup(dev, true);
1757
1758         return 0;
1759 }
1760
1761 static int dwc3_runtime_resume(struct device *dev)
1762 {
1763         struct dwc3     *dwc = dev_get_drvdata(dev);
1764         int             ret;
1765
1766         device_init_wakeup(dev, false);
1767
1768         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1769         if (ret)
1770                 return ret;
1771
1772         switch (dwc->current_dr_role) {
1773         case DWC3_GCTL_PRTCAP_DEVICE:
1774                 dwc3_gadget_process_pending_events(dwc);
1775                 break;
1776         case DWC3_GCTL_PRTCAP_HOST:
1777         default:
1778                 /* do nothing */
1779                 break;
1780         }
1781
1782         pm_runtime_mark_last_busy(dev);
1783
1784         return 0;
1785 }
1786
1787 static int dwc3_runtime_idle(struct device *dev)
1788 {
1789         struct dwc3     *dwc = dev_get_drvdata(dev);
1790
1791         switch (dwc->current_dr_role) {
1792         case DWC3_GCTL_PRTCAP_DEVICE:
1793                 if (dwc3_runtime_checks(dwc))
1794                         return -EBUSY;
1795                 break;
1796         case DWC3_GCTL_PRTCAP_HOST:
1797         default:
1798                 /* do nothing */
1799                 break;
1800         }
1801
1802         pm_runtime_mark_last_busy(dev);
1803         pm_runtime_autosuspend(dev);
1804
1805         return 0;
1806 }
1807 #endif /* CONFIG_PM */
1808
1809 #ifdef CONFIG_PM_SLEEP
1810 static int dwc3_suspend(struct device *dev)
1811 {
1812         struct dwc3     *dwc = dev_get_drvdata(dev);
1813         int             ret;
1814
1815         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1816         if (ret)
1817                 return ret;
1818
1819         pinctrl_pm_select_sleep_state(dev);
1820
1821         return 0;
1822 }
1823
1824 static int dwc3_resume(struct device *dev)
1825 {
1826         struct dwc3     *dwc = dev_get_drvdata(dev);
1827         int             ret;
1828
1829         pinctrl_pm_select_default_state(dev);
1830
1831         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1832         if (ret)
1833                 return ret;
1834
1835         pm_runtime_disable(dev);
1836         pm_runtime_set_active(dev);
1837         pm_runtime_enable(dev);
1838
1839         return 0;
1840 }
1841 #endif /* CONFIG_PM_SLEEP */
1842
1843 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1844         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1845         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1846                         dwc3_runtime_idle)
1847 };
1848
1849 #ifdef CONFIG_OF
1850 static const struct of_device_id of_dwc3_match[] = {
1851         {
1852                 .compatible = "snps,dwc3"
1853         },
1854         {
1855                 .compatible = "synopsys,dwc3"
1856         },
1857         { },
1858 };
1859 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1860 #endif
1861
1862 #ifdef CONFIG_ACPI
1863
1864 #define ACPI_ID_INTEL_BSW       "808622B7"
1865
1866 static const struct acpi_device_id dwc3_acpi_match[] = {
1867         { ACPI_ID_INTEL_BSW, 0 },
1868         { },
1869 };
1870 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1871 #endif
1872
1873 static struct platform_driver dwc3_driver = {
1874         .probe          = dwc3_probe,
1875         .remove         = dwc3_remove,
1876         .driver         = {
1877                 .name   = "dwc3",
1878                 .of_match_table = of_match_ptr(of_dwc3_match),
1879                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1880                 .pm     = &dwc3_dev_pm_ops,
1881         },
1882 };
1883
1884 module_platform_driver(dwc3_driver);
1885
1886 MODULE_ALIAS("platform:dwc3");
1887 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1888 MODULE_LICENSE("GPL v2");
1889 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");