1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Performance event support - Freescale Embedded Performance Monitor
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * Copyright 2010 Freescale Semiconductor, Inc.
8 #include <linux/kernel.h>
9 #include <linux/sched.h>
10 #include <linux/perf_event.h>
11 #include <linux/percpu.h>
12 #include <linux/hardirq.h>
13 #include <asm/reg_fsl_emb.h>
15 #include <asm/machdep.h>
16 #include <asm/firmware.h>
17 #include <asm/ptrace.h>
19 struct cpu_hw_events {
23 struct perf_event *event[MAX_HWEVENTS];
25 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
27 static struct fsl_emb_pmu *ppmu;
29 /* Number of perf_events counting hardware events */
30 static atomic_t num_events;
31 /* Used to avoid races in calling reserve/release_pmc_hardware */
32 static DEFINE_MUTEX(pmc_reserve_mutex);
34 static void perf_event_interrupt(struct pt_regs *regs);
37 * Read one performance monitor counter (PMC).
39 static unsigned long read_pmc(int idx)
45 val = mfpmr(PMRN_PMC0);
48 val = mfpmr(PMRN_PMC1);
51 val = mfpmr(PMRN_PMC2);
54 val = mfpmr(PMRN_PMC3);
57 val = mfpmr(PMRN_PMC4);
60 val = mfpmr(PMRN_PMC5);
63 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
72 static void write_pmc(int idx, unsigned long val)
76 mtpmr(PMRN_PMC0, val);
79 mtpmr(PMRN_PMC1, val);
82 mtpmr(PMRN_PMC2, val);
85 mtpmr(PMRN_PMC3, val);
88 mtpmr(PMRN_PMC4, val);
91 mtpmr(PMRN_PMC5, val);
94 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
101 * Write one local control A register
103 static void write_pmlca(int idx, unsigned long val)
107 mtpmr(PMRN_PMLCA0, val);
110 mtpmr(PMRN_PMLCA1, val);
113 mtpmr(PMRN_PMLCA2, val);
116 mtpmr(PMRN_PMLCA3, val);
119 mtpmr(PMRN_PMLCA4, val);
122 mtpmr(PMRN_PMLCA5, val);
125 printk(KERN_ERR "oops trying to write PMLCA%d\n", idx);
132 * Write one local control B register
134 static void write_pmlcb(int idx, unsigned long val)
138 mtpmr(PMRN_PMLCB0, val);
141 mtpmr(PMRN_PMLCB1, val);
144 mtpmr(PMRN_PMLCB2, val);
147 mtpmr(PMRN_PMLCB3, val);
150 mtpmr(PMRN_PMLCB4, val);
153 mtpmr(PMRN_PMLCB5, val);
156 printk(KERN_ERR "oops trying to write PMLCB%d\n", idx);
162 static void fsl_emb_pmu_read(struct perf_event *event)
164 s64 val, delta, prev;
166 if (event->hw.state & PERF_HES_STOPPED)
170 * Performance monitor interrupts come even when interrupts
171 * are soft-disabled, as long as interrupts are hard-enabled.
172 * Therefore we treat them like NMIs.
175 prev = local64_read(&event->hw.prev_count);
177 val = read_pmc(event->hw.idx);
178 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
180 /* The counters are only 32 bits wide */
181 delta = (val - prev) & 0xfffffffful;
182 local64_add(delta, &event->count);
183 local64_sub(delta, &event->hw.period_left);
187 * Disable all events to prevent PMU interrupts and to allow
188 * events to be added or removed.
190 static void fsl_emb_pmu_disable(struct pmu *pmu)
192 struct cpu_hw_events *cpuhw;
195 local_irq_save(flags);
196 cpuhw = this_cpu_ptr(&cpu_hw_events);
198 if (!cpuhw->disabled) {
202 * Check if we ever enabled the PMU on this cpu.
204 if (!cpuhw->pmcs_enabled) {
206 cpuhw->pmcs_enabled = 1;
209 if (atomic_read(&num_events)) {
211 * Set the 'freeze all counters' bit, and disable
212 * interrupts. The barrier is to make sure the
213 * mtpmr has been executed and the PMU has frozen
214 * the events before we return.
217 mtpmr(PMRN_PMGC0, PMGC0_FAC);
221 local_irq_restore(flags);
225 * Re-enable all events if disable == 0.
226 * If we were previously disabled and events were added, then
227 * put the new config on the PMU.
229 static void fsl_emb_pmu_enable(struct pmu *pmu)
231 struct cpu_hw_events *cpuhw;
234 local_irq_save(flags);
235 cpuhw = this_cpu_ptr(&cpu_hw_events);
236 if (!cpuhw->disabled)
240 ppc_set_pmu_inuse(cpuhw->n_events != 0);
242 if (cpuhw->n_events > 0) {
243 mtpmr(PMRN_PMGC0, PMGC0_PMIE | PMGC0_FCECE);
248 local_irq_restore(flags);
251 static int collect_events(struct perf_event *group, int max_count,
252 struct perf_event *ctrs[])
255 struct perf_event *event;
257 if (!is_software_event(group)) {
263 for_each_sibling_event(event, group) {
264 if (!is_software_event(event) &&
265 event->state != PERF_EVENT_STATE_OFF) {
275 /* context locked on entry */
276 static int fsl_emb_pmu_add(struct perf_event *event, int flags)
278 struct cpu_hw_events *cpuhw;
280 int num_counters = ppmu->n_counter;
284 perf_pmu_disable(event->pmu);
285 cpuhw = &get_cpu_var(cpu_hw_events);
287 if (event->hw.config & FSL_EMB_EVENT_RESTRICTED)
288 num_counters = ppmu->n_restricted;
291 * Allocate counters from top-down, so that restricted-capable
292 * counters are kept free as long as possible.
294 for (i = num_counters - 1; i >= 0; i--) {
305 cpuhw->event[i] = event;
309 if (event->hw.sample_period) {
310 s64 left = local64_read(&event->hw.period_left);
311 if (left < 0x80000000L)
312 val = 0x80000000L - left;
314 local64_set(&event->hw.prev_count, val);
316 if (unlikely(!(flags & PERF_EF_START))) {
317 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
320 event->hw.state &= ~(PERF_HES_STOPPED | PERF_HES_UPTODATE);
324 perf_event_update_userpage(event);
326 write_pmlcb(i, event->hw.config >> 32);
327 write_pmlca(i, event->hw.config_base);
331 put_cpu_var(cpu_hw_events);
332 perf_pmu_enable(event->pmu);
336 /* context locked on entry */
337 static void fsl_emb_pmu_del(struct perf_event *event, int flags)
339 struct cpu_hw_events *cpuhw;
340 int i = event->hw.idx;
342 perf_pmu_disable(event->pmu);
346 fsl_emb_pmu_read(event);
348 cpuhw = &get_cpu_var(cpu_hw_events);
350 WARN_ON(event != cpuhw->event[event->hw.idx]);
356 cpuhw->event[i] = NULL;
360 * TODO: if at least one restricted event exists, and we
361 * just freed up a non-restricted-capable counter, and
362 * there is a restricted-capable counter occupied by
363 * a non-restricted event, migrate that event to the
370 perf_pmu_enable(event->pmu);
371 put_cpu_var(cpu_hw_events);
374 static void fsl_emb_pmu_start(struct perf_event *event, int ef_flags)
380 if (event->hw.idx < 0 || !event->hw.sample_period)
383 if (!(event->hw.state & PERF_HES_STOPPED))
386 if (ef_flags & PERF_EF_RELOAD)
387 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
389 local_irq_save(flags);
390 perf_pmu_disable(event->pmu);
393 left = local64_read(&event->hw.period_left);
395 if (left < 0x80000000L)
396 val = 0x80000000L - left;
397 write_pmc(event->hw.idx, val);
399 perf_event_update_userpage(event);
400 perf_pmu_enable(event->pmu);
401 local_irq_restore(flags);
404 static void fsl_emb_pmu_stop(struct perf_event *event, int ef_flags)
408 if (event->hw.idx < 0 || !event->hw.sample_period)
411 if (event->hw.state & PERF_HES_STOPPED)
414 local_irq_save(flags);
415 perf_pmu_disable(event->pmu);
417 fsl_emb_pmu_read(event);
418 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
419 write_pmc(event->hw.idx, 0);
421 perf_event_update_userpage(event);
422 perf_pmu_enable(event->pmu);
423 local_irq_restore(flags);
427 * Release the PMU if this is the last perf_event.
429 static void hw_perf_event_destroy(struct perf_event *event)
431 if (!atomic_add_unless(&num_events, -1, 1)) {
432 mutex_lock(&pmc_reserve_mutex);
433 if (atomic_dec_return(&num_events) == 0)
434 release_pmc_hardware();
435 mutex_unlock(&pmc_reserve_mutex);
440 * Translate a generic cache event_id config to a raw event_id code.
442 static int hw_perf_cache_event(u64 config, u64 *eventp)
444 unsigned long type, op, result;
447 if (!ppmu->cache_events)
451 type = config & 0xff;
452 op = (config >> 8) & 0xff;
453 result = (config >> 16) & 0xff;
455 if (type >= PERF_COUNT_HW_CACHE_MAX ||
456 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
457 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
460 ev = (*ppmu->cache_events)[type][op][result];
469 static int fsl_emb_pmu_event_init(struct perf_event *event)
472 struct perf_event *events[MAX_HWEVENTS];
478 if (ppmu->n_counter > MAX_HWEVENTS) {
479 WARN(1, "No. of perf counters (%d) is higher than max array size(%d)\n",
480 ppmu->n_counter, MAX_HWEVENTS);
481 ppmu->n_counter = MAX_HWEVENTS;
484 switch (event->attr.type) {
485 case PERF_TYPE_HARDWARE:
486 ev = event->attr.config;
487 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
489 ev = ppmu->generic_events[ev];
492 case PERF_TYPE_HW_CACHE:
493 err = hw_perf_cache_event(event->attr.config, &ev);
499 ev = event->attr.config;
506 event->hw.config = ppmu->xlate_event(ev);
507 if (!(event->hw.config & FSL_EMB_EVENT_VALID))
511 * If this is in a group, check if it can go on with all the
512 * other hardware events in the group. We assume the event
513 * hasn't been linked into its leader's sibling list at this point.
516 if (event->group_leader != event) {
517 n = collect_events(event->group_leader,
518 ppmu->n_counter - 1, events);
523 if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) {
525 for (i = 0; i < n; i++) {
526 if (events[i]->hw.config & FSL_EMB_EVENT_RESTRICTED)
530 if (num_restricted >= ppmu->n_restricted)
536 event->hw.config_base = PMLCA_CE | PMLCA_FCM1 |
537 (u32)((ev << 16) & PMLCA_EVENT_MASK);
539 if (event->attr.exclude_user)
540 event->hw.config_base |= PMLCA_FCU;
541 if (event->attr.exclude_kernel)
542 event->hw.config_base |= PMLCA_FCS;
543 if (event->attr.exclude_idle)
546 event->hw.last_period = event->hw.sample_period;
547 local64_set(&event->hw.period_left, event->hw.last_period);
550 * See if we need to reserve the PMU.
551 * If no events are currently in use, then we have to take a
552 * mutex to ensure that we don't race with another task doing
553 * reserve_pmc_hardware or release_pmc_hardware.
556 if (!atomic_inc_not_zero(&num_events)) {
557 mutex_lock(&pmc_reserve_mutex);
558 if (atomic_read(&num_events) == 0 &&
559 reserve_pmc_hardware(perf_event_interrupt))
562 atomic_inc(&num_events);
563 mutex_unlock(&pmc_reserve_mutex);
565 mtpmr(PMRN_PMGC0, PMGC0_FAC);
568 event->destroy = hw_perf_event_destroy;
573 static struct pmu fsl_emb_pmu = {
574 .pmu_enable = fsl_emb_pmu_enable,
575 .pmu_disable = fsl_emb_pmu_disable,
576 .event_init = fsl_emb_pmu_event_init,
577 .add = fsl_emb_pmu_add,
578 .del = fsl_emb_pmu_del,
579 .start = fsl_emb_pmu_start,
580 .stop = fsl_emb_pmu_stop,
581 .read = fsl_emb_pmu_read,
585 * A counter has overflowed; update its count and record
586 * things if requested. Note that interrupts are hard-disabled
587 * here so there is no possibility of being interrupted.
589 static void record_and_restart(struct perf_event *event, unsigned long val,
590 struct pt_regs *regs)
592 u64 period = event->hw.sample_period;
593 s64 prev, delta, left;
596 if (event->hw.state & PERF_HES_STOPPED) {
597 write_pmc(event->hw.idx, 0);
601 /* we don't have to worry about interrupts here */
602 prev = local64_read(&event->hw.prev_count);
603 delta = (val - prev) & 0xfffffffful;
604 local64_add(delta, &event->count);
607 * See if the total period for this event has expired,
608 * and update for the next period.
611 left = local64_read(&event->hw.period_left) - delta;
618 event->hw.last_period = event->hw.sample_period;
620 if (left < 0x80000000LL)
621 val = 0x80000000LL - left;
624 write_pmc(event->hw.idx, val);
625 local64_set(&event->hw.prev_count, val);
626 local64_set(&event->hw.period_left, left);
627 perf_event_update_userpage(event);
630 * Finally record data if requested.
633 struct perf_sample_data data;
635 perf_sample_data_init(&data, 0, event->hw.last_period);
637 if (perf_event_overflow(event, &data, regs))
638 fsl_emb_pmu_stop(event, 0);
642 static void perf_event_interrupt(struct pt_regs *regs)
645 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
646 struct perf_event *event;
650 for (i = 0; i < ppmu->n_counter; ++i) {
651 event = cpuhw->event[i];
656 /* event has overflowed */
658 record_and_restart(event, val, regs);
661 * Disabled counter is negative,
662 * reset it just in case.
669 /* PMM will keep counters frozen until we return from the interrupt. */
670 mtmsr(mfmsr() | MSR_PMM);
671 mtpmr(PMRN_PMGC0, PMGC0_PMIE | PMGC0_FCECE);
675 void hw_perf_event_setup(int cpu)
677 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
679 memset(cpuhw, 0, sizeof(*cpuhw));
682 int register_fsl_emb_pmu(struct fsl_emb_pmu *pmu)
685 return -EBUSY; /* something's already registered */
688 pr_info("%s performance monitor hardware support registered\n",
691 perf_pmu_register(&fsl_emb_pmu, "cpu", PERF_TYPE_RAW);