2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #include "mlx5_core.h"
53 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
54 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRIVER_VERSION);
58 int mlx5_core_debug_mask;
59 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
60 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
62 #define MLX5_DEFAULT_PROF 2
63 static int prof_sel = MLX5_DEFAULT_PROF;
64 module_param_named(prof_sel, prof_sel, int, 0444);
65 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
67 static LIST_HEAD(intf_list);
68 static LIST_HEAD(dev_list);
69 static DEFINE_MUTEX(intf_mutex);
71 struct mlx5_device_context {
72 struct list_head list;
73 struct mlx5_interface *intf;
77 static struct mlx5_profile profile[] = {
82 .mask = MLX5_PROF_MASK_QP_SIZE,
86 .mask = MLX5_PROF_MASK_QP_SIZE |
87 MLX5_PROF_MASK_MR_CACHE,
156 #define FW_INIT_TIMEOUT_MILI 2000
157 #define FW_INIT_WAIT_MS 2
158 #define FW_PRE_INIT_TIMEOUT_MILI 10000
160 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
162 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
165 while (fw_initializing(dev)) {
166 if (time_after(jiffies, end)) {
170 msleep(FW_INIT_WAIT_MS);
176 static int set_dma_caps(struct pci_dev *pdev)
180 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
182 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
183 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
185 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
190 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
193 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
194 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
197 "Can't set consistent PCI DMA mask, aborting\n");
202 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
206 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
208 struct pci_dev *pdev = dev->pdev;
211 mutex_lock(&dev->pci_status_mutex);
212 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
213 err = pci_enable_device(pdev);
215 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
217 mutex_unlock(&dev->pci_status_mutex);
222 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
224 struct pci_dev *pdev = dev->pdev;
226 mutex_lock(&dev->pci_status_mutex);
227 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
228 pci_disable_device(pdev);
229 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
231 mutex_unlock(&dev->pci_status_mutex);
234 static int request_bar(struct pci_dev *pdev)
238 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
239 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
243 err = pci_request_regions(pdev, DRIVER_NAME);
245 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
250 static void release_bar(struct pci_dev *pdev)
252 pci_release_regions(pdev);
255 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
257 struct mlx5_priv *priv = &dev->priv;
258 struct mlx5_eq_table *table = &priv->eq_table;
259 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
263 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
264 MLX5_EQ_VEC_COMP_BASE;
265 nvec = min_t(int, nvec, num_eqs);
266 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
269 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
271 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
272 if (!priv->msix_arr || !priv->irq_info)
275 for (i = 0; i < nvec; i++)
276 priv->msix_arr[i].entry = i;
278 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
279 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
283 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
288 kfree(priv->irq_info);
289 kfree(priv->msix_arr);
293 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
295 struct mlx5_priv *priv = &dev->priv;
297 pci_disable_msix(dev->pdev);
298 kfree(priv->irq_info);
299 kfree(priv->msix_arr);
302 struct mlx5_reg_host_endianess {
308 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
311 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
312 MLX5_DEV_CAP_FLAG_DCT,
315 static u16 to_fw_pkey_sz(u32 size)
331 pr_warn("invalid pkey table size %d\n", size);
336 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
337 enum mlx5_cap_mode cap_mode)
339 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
340 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
341 void *out, *hca_caps;
342 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
345 memset(in, 0, sizeof(in));
346 out = kzalloc(out_sz, GFP_KERNEL);
350 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
351 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
352 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
356 err = mlx5_cmd_status_to_err_v2(out);
359 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
360 cap_type, cap_mode, err);
364 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
367 case HCA_CAP_OPMOD_GET_MAX:
368 memcpy(dev->hca_caps_max[cap_type], hca_caps,
369 MLX5_UN_SZ_BYTES(hca_cap_union));
371 case HCA_CAP_OPMOD_GET_CUR:
372 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
373 MLX5_UN_SZ_BYTES(hca_cap_union));
377 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
387 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
389 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
392 memset(out, 0, sizeof(out));
394 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
395 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
399 err = mlx5_cmd_status_to_err_v2(out);
404 static int handle_hca_cap(struct mlx5_core_dev *dev)
406 void *set_ctx = NULL;
407 struct mlx5_profile *prof = dev->profile;
409 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
412 set_ctx = kzalloc(set_sz, GFP_KERNEL);
416 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
420 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
424 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
426 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
427 MLX5_ST_SZ_BYTES(cmd_hca_cap));
429 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
430 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
432 /* we limit the size of the pkey table to 128 entries for now */
433 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
436 /* Check log_max_qp from HCA caps to set in current profile */
437 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
438 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
439 profile[prof_sel].log_max_qp,
440 MLX5_CAP_GEN_MAX(dev, log_max_qp));
441 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
443 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
444 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
447 /* disable cmdif checksum */
448 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
450 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
452 err = set_caps(dev, set_ctx, set_sz);
459 static int set_hca_ctrl(struct mlx5_core_dev *dev)
461 struct mlx5_reg_host_endianess he_in;
462 struct mlx5_reg_host_endianess he_out;
465 memset(&he_in, 0, sizeof(he_in));
466 he_in.he = MLX5_SET_HOST_ENDIANNESS;
467 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
468 &he_out, sizeof(he_out),
469 MLX5_REG_HOST_ENDIANNESS, 0, 1);
473 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
476 struct mlx5_enable_hca_mbox_in in;
477 struct mlx5_enable_hca_mbox_out out;
479 memset(&in, 0, sizeof(in));
480 memset(&out, 0, sizeof(out));
481 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
482 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
487 return mlx5_cmd_status_to_err(&out.hdr);
492 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
495 struct mlx5_disable_hca_mbox_in in;
496 struct mlx5_disable_hca_mbox_out out;
498 memset(&in, 0, sizeof(in));
499 memset(&out, 0, sizeof(out));
500 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
501 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
506 return mlx5_cmd_status_to_err(&out.hdr);
511 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
513 struct mlx5_priv *priv = &mdev->priv;
514 struct msix_entry *msix = priv->msix_arr;
515 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
517 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
518 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
522 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
523 priv->irq_info[i].mask);
525 if (IS_ENABLED(CONFIG_SMP) &&
526 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
527 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
532 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
534 struct mlx5_priv *priv = &mdev->priv;
535 struct msix_entry *msix = priv->msix_arr;
536 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
538 irq_set_affinity_hint(irq, NULL);
539 free_cpumask_var(priv->irq_info[i].mask);
542 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
547 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
548 err = mlx5_irq_set_affinity_hint(mdev, i);
556 for (i--; i >= 0; i--)
557 mlx5_irq_clear_affinity_hint(mdev, i);
562 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
566 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
567 mlx5_irq_clear_affinity_hint(mdev, i);
570 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
573 struct mlx5_eq_table *table = &dev->priv.eq_table;
574 struct mlx5_eq *eq, *n;
577 spin_lock(&table->lock);
578 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
579 if (eq->index == vector) {
586 spin_unlock(&table->lock);
590 EXPORT_SYMBOL(mlx5_vector2eqn);
592 static void free_comp_eqs(struct mlx5_core_dev *dev)
594 struct mlx5_eq_table *table = &dev->priv.eq_table;
595 struct mlx5_eq *eq, *n;
597 spin_lock(&table->lock);
598 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
600 spin_unlock(&table->lock);
601 if (mlx5_destroy_unmap_eq(dev, eq))
602 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
605 spin_lock(&table->lock);
607 spin_unlock(&table->lock);
610 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
612 struct mlx5_eq_table *table = &dev->priv.eq_table;
613 char name[MLX5_MAX_IRQ_NAME];
620 INIT_LIST_HEAD(&table->comp_eqs_list);
621 ncomp_vec = table->num_comp_vectors;
622 nent = MLX5_COMP_EQ_SIZE;
623 for (i = 0; i < ncomp_vec; i++) {
624 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
630 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
631 err = mlx5_create_map_eq(dev, eq,
632 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
633 name, &dev->priv.uuari.uars[0]);
638 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
640 spin_lock(&table->lock);
641 list_add_tail(&eq->list, &table->comp_eqs_list);
642 spin_unlock(&table->lock);
652 #ifdef CONFIG_MLX5_CORE_EN
653 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
655 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
656 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
657 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
658 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
662 memset(query_in, 0, sizeof(query_in));
663 memset(query_out, 0, sizeof(query_out));
665 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
667 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
668 query_out, sizeof(query_out));
670 if (((struct mlx5_outbox_hdr *)query_out)->status ==
671 MLX5_CMD_STAT_BAD_OP_ERR) {
672 pr_debug("Only ISSI 0 is supported\n");
676 pr_err("failed to query ISSI\n");
680 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
682 if (sup_issi & (1 << 1)) {
683 memset(set_in, 0, sizeof(set_in));
684 memset(set_out, 0, sizeof(set_out));
686 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
687 MLX5_SET(set_issi_in, set_in, current_issi, 1);
689 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
690 set_out, sizeof(set_out));
692 pr_err("failed to set ISSI=1\n");
699 } else if (sup_issi & (1 << 0) || !sup_issi) {
707 static int map_bf_area(struct mlx5_core_dev *dev)
709 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
710 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
712 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
714 return dev->priv.bf_mapping ? 0 : -ENOMEM;
717 static void unmap_bf_area(struct mlx5_core_dev *dev)
719 if (dev->priv.bf_mapping)
720 io_mapping_free(dev->priv.bf_mapping);
723 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
725 struct mlx5_device_context *dev_ctx;
726 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
728 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
732 dev_ctx->intf = intf;
733 dev_ctx->context = intf->add(dev);
735 if (dev_ctx->context) {
736 spin_lock_irq(&priv->ctx_lock);
737 list_add_tail(&dev_ctx->list, &priv->ctx_list);
738 spin_unlock_irq(&priv->ctx_lock);
744 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
746 struct mlx5_device_context *dev_ctx;
747 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
749 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
750 if (dev_ctx->intf == intf) {
751 spin_lock_irq(&priv->ctx_lock);
752 list_del(&dev_ctx->list);
753 spin_unlock_irq(&priv->ctx_lock);
755 intf->remove(dev, dev_ctx->context);
761 static int mlx5_register_device(struct mlx5_core_dev *dev)
763 struct mlx5_priv *priv = &dev->priv;
764 struct mlx5_interface *intf;
766 mutex_lock(&intf_mutex);
767 list_add_tail(&priv->dev_list, &dev_list);
768 list_for_each_entry(intf, &intf_list, list)
769 mlx5_add_device(intf, priv);
770 mutex_unlock(&intf_mutex);
775 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
777 struct mlx5_priv *priv = &dev->priv;
778 struct mlx5_interface *intf;
780 mutex_lock(&intf_mutex);
781 list_for_each_entry_reverse(intf, &intf_list, list)
782 mlx5_remove_device(intf, priv);
783 list_del(&priv->dev_list);
784 mutex_unlock(&intf_mutex);
787 int mlx5_register_interface(struct mlx5_interface *intf)
789 struct mlx5_priv *priv;
791 if (!intf->add || !intf->remove)
794 mutex_lock(&intf_mutex);
795 list_add_tail(&intf->list, &intf_list);
796 list_for_each_entry(priv, &dev_list, dev_list)
797 mlx5_add_device(intf, priv);
798 mutex_unlock(&intf_mutex);
802 EXPORT_SYMBOL(mlx5_register_interface);
804 void mlx5_unregister_interface(struct mlx5_interface *intf)
806 struct mlx5_priv *priv;
808 mutex_lock(&intf_mutex);
809 list_for_each_entry(priv, &dev_list, dev_list)
810 mlx5_remove_device(intf, priv);
811 list_del(&intf->list);
812 mutex_unlock(&intf_mutex);
814 EXPORT_SYMBOL(mlx5_unregister_interface);
816 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
818 struct mlx5_priv *priv = &mdev->priv;
819 struct mlx5_device_context *dev_ctx;
823 spin_lock_irqsave(&priv->ctx_lock, flags);
825 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
826 if ((dev_ctx->intf->protocol == protocol) &&
827 dev_ctx->intf->get_dev) {
828 result = dev_ctx->intf->get_dev(dev_ctx->context);
832 spin_unlock_irqrestore(&priv->ctx_lock, flags);
836 EXPORT_SYMBOL(mlx5_get_protocol_dev);
838 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
840 struct pci_dev *pdev = dev->pdev;
843 pci_set_drvdata(dev->pdev, dev);
844 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
845 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
847 mutex_init(&priv->pgdir_mutex);
848 INIT_LIST_HEAD(&priv->pgdir_list);
849 spin_lock_init(&priv->mkey_lock);
851 mutex_init(&priv->alloc_mutex);
853 priv->numa_node = dev_to_node(&dev->pdev->dev);
855 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
859 err = mlx5_pci_enable_device(dev);
861 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
865 err = request_bar(pdev);
867 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
871 pci_set_master(pdev);
873 err = set_dma_caps(pdev);
875 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
879 dev->iseg_base = pci_resource_start(dev->pdev, 0);
880 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
883 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
890 pci_clear_master(dev->pdev);
891 release_bar(dev->pdev);
893 mlx5_pci_disable_device(dev);
896 debugfs_remove(priv->dbg_root);
900 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
903 pci_clear_master(dev->pdev);
904 release_bar(dev->pdev);
905 mlx5_pci_disable_device(dev);
906 debugfs_remove(priv->dbg_root);
909 #define MLX5_IB_MOD "mlx5_ib"
910 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
912 struct pci_dev *pdev = dev->pdev;
915 mutex_lock(&dev->intf_state_mutex);
916 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
917 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
922 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
923 fw_rev_min(dev), fw_rev_sub(dev));
925 /* on load removing any previous indication of internal error, device is
928 dev->state = MLX5_DEVICE_STATE_UP;
930 /* wait for firmware to accept initialization segments configurations
932 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
934 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
935 FW_PRE_INIT_TIMEOUT_MILI);
939 err = mlx5_cmd_init(dev);
941 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
945 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
947 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
948 FW_INIT_TIMEOUT_MILI);
952 mlx5_pagealloc_init(dev);
954 err = mlx5_core_enable_hca(dev);
956 dev_err(&pdev->dev, "enable hca failed\n");
957 goto err_pagealloc_cleanup;
960 #ifdef CONFIG_MLX5_CORE_EN
961 err = mlx5_core_set_issi(dev);
963 dev_err(&pdev->dev, "failed to set issi\n");
964 goto err_disable_hca;
968 err = mlx5_satisfy_startup_pages(dev, 1);
970 dev_err(&pdev->dev, "failed to allocate boot pages\n");
971 goto err_disable_hca;
974 err = set_hca_ctrl(dev);
976 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
977 goto reclaim_boot_pages;
980 err = handle_hca_cap(dev);
982 dev_err(&pdev->dev, "handle_hca_cap failed\n");
983 goto reclaim_boot_pages;
986 err = mlx5_satisfy_startup_pages(dev, 0);
988 dev_err(&pdev->dev, "failed to allocate init pages\n");
989 goto reclaim_boot_pages;
992 err = mlx5_pagealloc_start(dev);
994 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
995 goto reclaim_boot_pages;
998 err = mlx5_cmd_init_hca(dev);
1000 dev_err(&pdev->dev, "init hca failed\n");
1001 goto err_pagealloc_stop;
1004 mlx5_start_health_poll(dev);
1006 err = mlx5_query_hca_caps(dev);
1008 dev_err(&pdev->dev, "query hca failed\n");
1012 err = mlx5_query_board_id(dev);
1014 dev_err(&pdev->dev, "query board id failed\n");
1018 err = mlx5_enable_msix(dev);
1020 dev_err(&pdev->dev, "enable msix failed\n");
1024 err = mlx5_eq_init(dev);
1026 dev_err(&pdev->dev, "failed to initialize eq\n");
1030 err = mlx5_alloc_uuars(dev, &priv->uuari);
1032 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1033 goto err_eq_cleanup;
1036 err = mlx5_start_eqs(dev);
1038 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1042 err = alloc_comp_eqs(dev);
1044 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1048 if (map_bf_area(dev))
1049 dev_err(&pdev->dev, "Failed to map blue flame area\n");
1051 err = mlx5_irq_set_affinity_hints(dev);
1053 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1054 goto err_unmap_bf_area;
1057 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1059 mlx5_init_cq_table(dev);
1060 mlx5_init_qp_table(dev);
1061 mlx5_init_srq_table(dev);
1062 mlx5_init_mr_table(dev);
1064 err = mlx5_register_device(dev);
1066 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1070 err = request_module_nowait(MLX5_IB_MOD);
1072 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1074 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1076 mutex_unlock(&dev->intf_state_mutex);
1081 mlx5_cleanup_mr_table(dev);
1082 mlx5_cleanup_srq_table(dev);
1083 mlx5_cleanup_qp_table(dev);
1084 mlx5_cleanup_cq_table(dev);
1085 mlx5_irq_clear_affinity_hints(dev);
1096 mlx5_free_uuars(dev, &priv->uuari);
1099 mlx5_eq_cleanup(dev);
1102 mlx5_disable_msix(dev);
1105 mlx5_stop_health_poll(dev);
1106 if (mlx5_cmd_teardown_hca(dev)) {
1107 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1112 mlx5_pagealloc_stop(dev);
1115 mlx5_reclaim_startup_pages(dev);
1118 mlx5_core_disable_hca(dev);
1120 err_pagealloc_cleanup:
1121 mlx5_pagealloc_cleanup(dev);
1122 mlx5_cmd_cleanup(dev);
1125 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1126 mutex_unlock(&dev->intf_state_mutex);
1131 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1135 mutex_lock(&dev->intf_state_mutex);
1136 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1137 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1141 mlx5_unregister_device(dev);
1142 mlx5_cleanup_mr_table(dev);
1143 mlx5_cleanup_srq_table(dev);
1144 mlx5_cleanup_qp_table(dev);
1145 mlx5_cleanup_cq_table(dev);
1146 mlx5_irq_clear_affinity_hints(dev);
1150 mlx5_free_uuars(dev, &priv->uuari);
1151 mlx5_eq_cleanup(dev);
1152 mlx5_disable_msix(dev);
1153 mlx5_stop_health_poll(dev);
1154 err = mlx5_cmd_teardown_hca(dev);
1156 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1159 mlx5_pagealloc_stop(dev);
1160 mlx5_reclaim_startup_pages(dev);
1161 mlx5_core_disable_hca(dev);
1162 mlx5_pagealloc_cleanup(dev);
1163 mlx5_cmd_cleanup(dev);
1166 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1167 mutex_unlock(&dev->intf_state_mutex);
1171 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1172 unsigned long param)
1174 struct mlx5_priv *priv = &dev->priv;
1175 struct mlx5_device_context *dev_ctx;
1176 unsigned long flags;
1178 spin_lock_irqsave(&priv->ctx_lock, flags);
1180 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1181 if (dev_ctx->intf->event)
1182 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1184 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1187 struct mlx5_core_event_handler {
1188 void (*event)(struct mlx5_core_dev *dev,
1189 enum mlx5_dev_event event,
1194 static int init_one(struct pci_dev *pdev,
1195 const struct pci_device_id *id)
1197 struct mlx5_core_dev *dev;
1198 struct mlx5_priv *priv;
1201 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1203 dev_err(&pdev->dev, "kzalloc failed\n");
1208 pci_set_drvdata(pdev, dev);
1210 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1211 pr_warn("selected profile out of range, selecting default (%d)\n",
1213 prof_sel = MLX5_DEFAULT_PROF;
1215 dev->profile = &profile[prof_sel];
1217 dev->event = mlx5_core_event;
1219 INIT_LIST_HEAD(&priv->ctx_list);
1220 spin_lock_init(&priv->ctx_lock);
1221 mutex_init(&dev->pci_status_mutex);
1222 mutex_init(&dev->intf_state_mutex);
1223 err = mlx5_pci_init(dev, priv);
1225 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1229 err = mlx5_health_init(dev);
1231 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1235 err = mlx5_load_one(dev, priv);
1237 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1244 mlx5_health_cleanup(dev);
1246 mlx5_pci_close(dev, priv);
1248 pci_set_drvdata(pdev, NULL);
1254 static void remove_one(struct pci_dev *pdev)
1256 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1257 struct mlx5_priv *priv = &dev->priv;
1259 if (mlx5_unload_one(dev, priv)) {
1260 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1261 mlx5_health_cleanup(dev);
1264 mlx5_health_cleanup(dev);
1265 mlx5_pci_close(dev, priv);
1266 pci_set_drvdata(pdev, NULL);
1270 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1271 pci_channel_state_t state)
1273 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1274 struct mlx5_priv *priv = &dev->priv;
1276 dev_info(&pdev->dev, "%s was called\n", __func__);
1277 mlx5_enter_error_state(dev);
1278 mlx5_unload_one(dev, priv);
1279 pci_save_state(pdev);
1280 mlx5_pci_disable_device(dev);
1281 return state == pci_channel_io_perm_failure ?
1282 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1285 /* wait for the device to show vital signs by waiting
1286 * for the health counter to start counting.
1288 static int wait_vital(struct pci_dev *pdev)
1290 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1291 struct mlx5_core_health *health = &dev->priv.health;
1292 const int niter = 100;
1297 for (i = 0; i < niter; i++) {
1298 count = ioread32be(health->health_counter);
1299 if (count && count != 0xffffffff) {
1300 if (last_count && last_count != count) {
1301 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1312 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1314 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1317 dev_info(&pdev->dev, "%s was called\n", __func__);
1319 err = mlx5_pci_enable_device(dev);
1321 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1323 return PCI_ERS_RESULT_DISCONNECT;
1326 pci_set_master(pdev);
1327 pci_restore_state(pdev);
1329 if (wait_vital(pdev)) {
1330 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1331 return PCI_ERS_RESULT_DISCONNECT;
1334 return PCI_ERS_RESULT_RECOVERED;
1337 void mlx5_disable_device(struct mlx5_core_dev *dev)
1339 mlx5_pci_err_detected(dev->pdev, 0);
1342 static void mlx5_pci_resume(struct pci_dev *pdev)
1344 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1345 struct mlx5_priv *priv = &dev->priv;
1348 dev_info(&pdev->dev, "%s was called\n", __func__);
1350 err = mlx5_load_one(dev, priv);
1352 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1355 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1358 static const struct pci_error_handlers mlx5_err_handler = {
1359 .error_detected = mlx5_pci_err_detected,
1360 .slot_reset = mlx5_pci_slot_reset,
1361 .resume = mlx5_pci_resume
1364 static const struct pci_device_id mlx5_core_pci_table[] = {
1365 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1366 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1367 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1368 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1369 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1370 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
1374 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1376 static struct pci_driver mlx5_core_driver = {
1377 .name = DRIVER_NAME,
1378 .id_table = mlx5_core_pci_table,
1380 .remove = remove_one,
1381 .err_handler = &mlx5_err_handler
1384 static int __init init(void)
1388 mlx5_register_debugfs();
1390 err = pci_register_driver(&mlx5_core_driver);
1394 #ifdef CONFIG_MLX5_CORE_EN
1401 mlx5_unregister_debugfs();
1405 static void __exit cleanup(void)
1407 #ifdef CONFIG_MLX5_CORE_EN
1410 pci_unregister_driver(&mlx5_core_driver);
1411 mlx5_unregister_debugfs();
1415 module_exit(cleanup);