2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
37 #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
38 #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
41 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
43 struct mlx5_wq_cyc *wq = &sq->wq;
45 u16 pi = sq->pc & wq->sz_m1;
46 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
48 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
50 memset(cseg, 0, sizeof(*cseg));
52 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
53 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | 0x01);
59 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
60 mlx5e_tx_notify_hw(sq, wqe, 0);
64 static inline void mlx5e_tx_dma_unmap(struct device *pdev,
65 struct mlx5e_sq_dma *dma)
68 case MLX5E_DMA_MAP_SINGLE:
69 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
71 case MLX5E_DMA_MAP_PAGE:
72 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
75 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
79 static inline void mlx5e_dma_push(struct mlx5e_sq *sq,
82 enum mlx5e_dma_map_type map_type)
84 sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
85 sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
86 sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].type = map_type;
90 static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_sq *sq, u32 i)
92 return &sq->dma_fifo[i & sq->dma_fifo_mask];
95 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, struct sk_buff *skb)
99 for (i = 0; i < MLX5E_TX_SKB_CB(skb)->num_dma; i++) {
100 struct mlx5e_sq_dma *last_pushed_dma =
101 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
103 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
107 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
108 void *accel_priv, select_queue_fallback_t fallback)
110 struct mlx5e_priv *priv = netdev_priv(dev);
111 int channel_ix = fallback(dev, skb);
112 int up = skb_vlan_tag_present(skb) ?
113 skb->vlan_tci >> VLAN_PRIO_SHIFT :
114 priv->default_vlan_prio;
115 int tc = netdev_get_prio_tc_map(dev, up);
117 return priv->channeltc_to_txq_map[channel_ix][tc];
120 static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
121 struct sk_buff *skb, bool bf)
123 /* Some NIC TX decisions, e.g loopback, are based on the packet
124 * headers and occur before the data gather.
125 * Therefore these headers must be copied into the WQE
127 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
130 u16 ihs = skb_headlen(skb);
132 if (skb_vlan_tag_present(skb))
135 if (ihs <= sq->max_inline)
136 return skb_headlen(skb);
139 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
142 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs)
144 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
145 int cpy1_sz = 2 * ETH_ALEN;
146 int cpy2_sz = ihs - cpy1_sz;
148 skb_copy_from_linear_data(skb, vhdr, cpy1_sz);
149 skb_pull_inline(skb, cpy1_sz);
150 vhdr->h_vlan_proto = skb->vlan_proto;
151 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
152 skb_copy_from_linear_data(skb, &vhdr->h_vlan_encapsulated_proto,
154 skb_pull_inline(skb, cpy2_sz);
157 static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq *sq, struct sk_buff *skb)
159 struct mlx5_wq_cyc *wq = &sq->wq;
161 u16 pi = sq->pc & wq->sz_m1;
162 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
164 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
165 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
166 struct mlx5_wqe_data_seg *dseg;
168 u8 opcode = MLX5_OPCODE_SEND;
169 dma_addr_t dma_addr = 0;
176 memset(wqe, 0, sizeof(*wqe));
178 if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
179 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
181 sq->stats.csum_offload_none++;
183 if (sq->cc != sq->prev_cc) {
184 sq->prev_cc = sq->cc;
185 sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0;
188 if (skb_is_gso(skb)) {
191 eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
192 opcode = MLX5_OPCODE_LSO;
193 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
194 payload_len = skb->len - ihs;
195 MLX5E_TX_SKB_CB(skb)->num_bytes = skb->len +
196 (skb_shinfo(skb)->gso_segs - 1) * ihs;
197 sq->stats.tso_packets++;
198 sq->stats.tso_bytes += payload_len;
200 bf = sq->bf_budget &&
202 !skb_shinfo(skb)->nr_frags;
203 ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
204 MLX5E_TX_SKB_CB(skb)->num_bytes = max_t(unsigned int, skb->len,
208 if (skb_vlan_tag_present(skb)) {
209 mlx5e_insert_vlan(eseg->inline_hdr_start, skb, ihs);
212 skb_copy_from_linear_data(skb, eseg->inline_hdr_start, ihs);
213 skb_pull_inline(skb, ihs);
216 eseg->inline_hdr_sz = cpu_to_be16(ihs);
218 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
219 ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
221 dseg = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;
223 MLX5E_TX_SKB_CB(skb)->num_dma = 0;
225 headlen = skb_headlen(skb);
227 dma_addr = dma_map_single(sq->pdev, skb->data, headlen,
229 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
230 goto dma_unmap_wqe_err;
232 dseg->addr = cpu_to_be64(dma_addr);
233 dseg->lkey = sq->mkey_be;
234 dseg->byte_count = cpu_to_be32(headlen);
236 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
237 MLX5E_TX_SKB_CB(skb)->num_dma++;
242 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
243 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
244 int fsz = skb_frag_size(frag);
246 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
248 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
249 goto dma_unmap_wqe_err;
251 dseg->addr = cpu_to_be64(dma_addr);
252 dseg->lkey = sq->mkey_be;
253 dseg->byte_count = cpu_to_be32(fsz);
255 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
256 MLX5E_TX_SKB_CB(skb)->num_dma++;
261 ds_cnt += MLX5E_TX_SKB_CB(skb)->num_dma;
263 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
264 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
268 MLX5E_TX_SKB_CB(skb)->num_wqebbs = DIV_ROUND_UP(ds_cnt,
269 MLX5_SEND_WQEBB_NUM_DS);
270 sq->pc += MLX5E_TX_SKB_CB(skb)->num_wqebbs;
272 netdev_tx_sent_queue(sq->txq, MLX5E_TX_SKB_CB(skb)->num_bytes);
274 if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
275 netif_tx_stop_queue(sq->txq);
279 if (!skb->xmit_more || netif_xmit_stopped(sq->txq)) {
282 if (bf && sq->uar_bf_map)
283 bf_sz = MLX5E_TX_SKB_CB(skb)->num_wqebbs << 3;
285 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
286 mlx5e_tx_notify_hw(sq, wqe, bf_sz);
289 /* fill sq edge with nops to avoid wqe wrap around */
290 while ((sq->pc & wq->sz_m1) > sq->edge)
291 mlx5e_send_nop(sq, false);
301 mlx5e_dma_unmap_wqe_err(sq, skb);
303 dev_kfree_skb_any(skb);
308 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
310 struct mlx5e_priv *priv = netdev_priv(dev);
311 struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];
313 return mlx5e_sq_xmit(sq, skb);
316 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq)
325 /* avoid accessing cq (dma coherent memory) if not needed */
326 if (!test_and_clear_bit(MLX5E_CQ_HAS_CQES, &cq->flags))
329 sq = container_of(cq, struct mlx5e_sq, cq);
334 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
335 * otherwise a cq overrun may occur
339 /* avoid dirtying sq cache line every cqe */
340 dma_fifo_cc = sq->dma_fifo_cc;
342 for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
343 struct mlx5_cqe64 *cqe;
347 cqe = mlx5e_get_cqe(cq);
351 mlx5_cqwq_pop(&cq->wq);
353 wqe_counter = be16_to_cpu(cqe->wqe_counter);
360 last_wqe = (sqcc == wqe_counter);
362 ci = sqcc & sq->wq.sz_m1;
365 if (unlikely(!skb)) { /* nop */
371 for (j = 0; j < MLX5E_TX_SKB_CB(skb)->num_dma; j++) {
372 struct mlx5e_sq_dma *dma =
373 mlx5e_dma_get(sq, dma_fifo_cc++);
375 mlx5e_tx_dma_unmap(sq->pdev, dma);
379 nbytes += MLX5E_TX_SKB_CB(skb)->num_bytes;
380 sqcc += MLX5E_TX_SKB_CB(skb)->num_wqebbs;
385 mlx5_cqwq_update_db_record(&cq->wq);
387 /* ensure cq space is freed before enabling more cqes */
390 sq->dma_fifo_cc = dma_fifo_cc;
393 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
395 if (netif_tx_queue_stopped(sq->txq) &&
396 mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
397 likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
398 netif_tx_wake_queue(sq->txq);
401 if (i == MLX5E_TX_CQ_POLL_BUDGET) {
402 set_bit(MLX5E_CQ_HAS_CQES, &cq->flags);