2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/mlx5/flow_table.h>
36 struct mlx5e_rq_param {
37 u32 rqc[MLX5_ST_SZ_DW(rqc)];
38 struct mlx5_wq_param wq;
41 struct mlx5e_sq_param {
42 u32 sqc[MLX5_ST_SZ_DW(sqc)];
43 struct mlx5_wq_param wq;
47 struct mlx5e_cq_param {
48 u32 cqc[MLX5_ST_SZ_DW(cqc)];
49 struct mlx5_wq_param wq;
53 struct mlx5e_channel_param {
54 struct mlx5e_rq_param rq;
55 struct mlx5e_sq_param sq;
56 struct mlx5e_cq_param rx_cq;
57 struct mlx5e_cq_param tx_cq;
60 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
62 struct mlx5_core_dev *mdev = priv->mdev;
65 port_state = mlx5_query_vport_state(mdev,
66 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
68 if (port_state == VPORT_STATE_UP)
69 netif_carrier_on(priv->netdev);
71 netif_carrier_off(priv->netdev);
74 static void mlx5e_update_carrier_work(struct work_struct *work)
76 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
79 mutex_lock(&priv->state_lock);
80 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
81 mlx5e_update_carrier(priv);
82 mutex_unlock(&priv->state_lock);
85 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
87 struct mlx5_core_dev *mdev = priv->mdev;
88 struct mlx5e_pport_stats *s = &priv->stats.pport;
91 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
93 in = mlx5_vzalloc(sz);
94 out = mlx5_vzalloc(sz);
98 MLX5_SET(ppcnt_reg, in, local_port, 1);
100 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
101 mlx5_core_access_reg(mdev, in, sz, out,
102 sz, MLX5_REG_PPCNT, 0, 0);
103 memcpy(s->IEEE_802_3_counters,
104 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
105 sizeof(s->IEEE_802_3_counters));
107 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
108 mlx5_core_access_reg(mdev, in, sz, out,
109 sz, MLX5_REG_PPCNT, 0, 0);
110 memcpy(s->RFC_2863_counters,
111 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
112 sizeof(s->RFC_2863_counters));
114 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
115 mlx5_core_access_reg(mdev, in, sz, out,
116 sz, MLX5_REG_PPCNT, 0, 0);
117 memcpy(s->RFC_2819_counters,
118 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
119 sizeof(s->RFC_2819_counters));
126 void mlx5e_update_stats(struct mlx5e_priv *priv)
128 struct mlx5_core_dev *mdev = priv->mdev;
129 struct mlx5e_vport_stats *s = &priv->stats.vport;
130 struct mlx5e_rq_stats *rq_stats;
131 struct mlx5e_sq_stats *sq_stats;
132 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
134 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
138 out = mlx5_vzalloc(outlen);
142 /* Collect firts the SW counters and then HW for consistency */
145 s->tx_queue_stopped = 0;
146 s->tx_queue_wake = 0;
147 s->tx_queue_dropped = 0;
154 for (i = 0; i < priv->params.num_channels; i++) {
155 rq_stats = &priv->channel[i]->rq.stats;
157 s->lro_packets += rq_stats->lro_packets;
158 s->lro_bytes += rq_stats->lro_bytes;
159 s->rx_csum_none += rq_stats->csum_none;
160 s->rx_csum_sw += rq_stats->csum_sw;
161 s->rx_wqe_err += rq_stats->wqe_err;
163 for (j = 0; j < priv->params.num_tc; j++) {
164 sq_stats = &priv->channel[i]->sq[j].stats;
166 s->tso_packets += sq_stats->tso_packets;
167 s->tso_bytes += sq_stats->tso_bytes;
168 s->tx_queue_stopped += sq_stats->stopped;
169 s->tx_queue_wake += sq_stats->wake;
170 s->tx_queue_dropped += sq_stats->dropped;
171 tx_offload_none += sq_stats->csum_offload_none;
176 memset(in, 0, sizeof(in));
178 MLX5_SET(query_vport_counter_in, in, opcode,
179 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
180 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
181 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
183 memset(out, 0, outlen);
185 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
188 #define MLX5_GET_CTR(p, x) \
189 MLX5_GET64(query_vport_counter_out, p, x)
191 s->rx_error_packets =
192 MLX5_GET_CTR(out, received_errors.packets);
194 MLX5_GET_CTR(out, received_errors.octets);
195 s->tx_error_packets =
196 MLX5_GET_CTR(out, transmit_errors.packets);
198 MLX5_GET_CTR(out, transmit_errors.octets);
200 s->rx_unicast_packets =
201 MLX5_GET_CTR(out, received_eth_unicast.packets);
202 s->rx_unicast_bytes =
203 MLX5_GET_CTR(out, received_eth_unicast.octets);
204 s->tx_unicast_packets =
205 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
206 s->tx_unicast_bytes =
207 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
209 s->rx_multicast_packets =
210 MLX5_GET_CTR(out, received_eth_multicast.packets);
211 s->rx_multicast_bytes =
212 MLX5_GET_CTR(out, received_eth_multicast.octets);
213 s->tx_multicast_packets =
214 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
215 s->tx_multicast_bytes =
216 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
218 s->rx_broadcast_packets =
219 MLX5_GET_CTR(out, received_eth_broadcast.packets);
220 s->rx_broadcast_bytes =
221 MLX5_GET_CTR(out, received_eth_broadcast.octets);
222 s->tx_broadcast_packets =
223 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
224 s->tx_broadcast_bytes =
225 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
228 s->rx_unicast_packets +
229 s->rx_multicast_packets +
230 s->rx_broadcast_packets;
232 s->rx_unicast_bytes +
233 s->rx_multicast_bytes +
234 s->rx_broadcast_bytes;
236 s->tx_unicast_packets +
237 s->tx_multicast_packets +
238 s->tx_broadcast_packets;
240 s->tx_unicast_bytes +
241 s->tx_multicast_bytes +
242 s->tx_broadcast_bytes;
244 /* Update calculated offload counters */
245 s->tx_csum_offload = s->tx_packets - tx_offload_none;
246 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
249 mlx5e_update_pport_counters(priv);
254 static void mlx5e_update_stats_work(struct work_struct *work)
256 struct delayed_work *dwork = to_delayed_work(work);
257 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
259 mutex_lock(&priv->state_lock);
260 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
261 mlx5e_update_stats(priv);
262 schedule_delayed_work(dwork,
264 MLX5E_UPDATE_STATS_INTERVAL));
266 mutex_unlock(&priv->state_lock);
269 static void __mlx5e_async_event(struct mlx5e_priv *priv,
270 enum mlx5_dev_event event)
273 case MLX5_DEV_EVENT_PORT_UP:
274 case MLX5_DEV_EVENT_PORT_DOWN:
275 schedule_work(&priv->update_carrier_work);
283 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
284 enum mlx5_dev_event event, unsigned long param)
286 struct mlx5e_priv *priv = vpriv;
288 spin_lock(&priv->async_events_spinlock);
289 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
290 __mlx5e_async_event(priv, event);
291 spin_unlock(&priv->async_events_spinlock);
294 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
296 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
299 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
301 spin_lock_irq(&priv->async_events_spinlock);
302 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
303 spin_unlock_irq(&priv->async_events_spinlock);
306 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
307 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
309 static int mlx5e_create_rq(struct mlx5e_channel *c,
310 struct mlx5e_rq_param *param,
313 struct mlx5e_priv *priv = c->priv;
314 struct mlx5_core_dev *mdev = priv->mdev;
315 void *rqc = param->rqc;
316 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
321 param->wq.db_numa_node = cpu_to_node(c->cpu);
323 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
328 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
330 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
331 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
332 cpu_to_node(c->cpu));
335 goto err_rq_wq_destroy;
338 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
339 MLX5E_SW2HW_MTU(priv->netdev->mtu);
340 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
342 for (i = 0; i < wq_sz; i++) {
343 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
344 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
346 wqe->data.lkey = c->mkey_be;
347 wqe->data.byte_count =
348 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
352 rq->netdev = c->netdev;
360 mlx5_wq_destroy(&rq->wq_ctrl);
365 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
368 mlx5_wq_destroy(&rq->wq_ctrl);
371 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
373 struct mlx5e_priv *priv = rq->priv;
374 struct mlx5_core_dev *mdev = priv->mdev;
382 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
383 sizeof(u64) * rq->wq_ctrl.buf.npages;
384 in = mlx5_vzalloc(inlen);
388 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
389 wq = MLX5_ADDR_OF(rqc, rqc, wq);
391 memcpy(rqc, param->rqc, sizeof(param->rqc));
393 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
394 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
395 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
396 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
397 MLX5_ADAPTER_PAGE_SHIFT);
398 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
400 mlx5_fill_page_array(&rq->wq_ctrl.buf,
401 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
403 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
410 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
412 struct mlx5e_channel *c = rq->channel;
413 struct mlx5e_priv *priv = c->priv;
414 struct mlx5_core_dev *mdev = priv->mdev;
421 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
422 in = mlx5_vzalloc(inlen);
426 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
428 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
429 MLX5_SET(rqc, rqc, state, next_state);
431 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
438 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
440 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
443 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
445 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
446 struct mlx5e_channel *c = rq->channel;
447 struct mlx5e_priv *priv = c->priv;
448 struct mlx5_wq_ll *wq = &rq->wq;
450 while (time_before(jiffies, exp_time)) {
451 if (wq->cur_sz >= priv->params.min_rx_wqes)
460 static int mlx5e_open_rq(struct mlx5e_channel *c,
461 struct mlx5e_rq_param *param,
466 err = mlx5e_create_rq(c, param, rq);
470 err = mlx5e_enable_rq(rq, param);
474 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
478 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
479 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
484 mlx5e_disable_rq(rq);
486 mlx5e_destroy_rq(rq);
491 static void mlx5e_close_rq(struct mlx5e_rq *rq)
493 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
494 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
496 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
497 while (!mlx5_wq_ll_is_empty(&rq->wq))
500 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
501 napi_synchronize(&rq->channel->napi);
503 mlx5e_disable_rq(rq);
504 mlx5e_destroy_rq(rq);
507 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
513 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
515 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
516 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
518 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
519 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
522 if (!sq->skb || !sq->dma_fifo) {
523 mlx5e_free_sq_db(sq);
527 sq->dma_fifo_mask = df_sz - 1;
532 static int mlx5e_create_sq(struct mlx5e_channel *c,
534 struct mlx5e_sq_param *param,
537 struct mlx5e_priv *priv = c->priv;
538 struct mlx5_core_dev *mdev = priv->mdev;
540 void *sqc = param->sqc;
541 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
545 err = mlx5_alloc_map_uar(mdev, &sq->uar);
549 param->wq.db_numa_node = cpu_to_node(c->cpu);
551 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
554 goto err_unmap_free_uar;
556 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
557 sq->uar_map = sq->uar.map;
558 sq->uar_bf_map = sq->uar.bf_map;
559 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
560 sq->max_inline = param->max_inline;
562 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
564 goto err_sq_wq_destroy;
566 txq_ix = c->ix + tc * priv->params.num_channels;
567 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
570 sq->mkey_be = c->mkey_be;
573 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
574 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
575 priv->txq_to_sq_map[txq_ix] = sq;
580 mlx5_wq_destroy(&sq->wq_ctrl);
583 mlx5_unmap_free_uar(mdev, &sq->uar);
588 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
590 struct mlx5e_channel *c = sq->channel;
591 struct mlx5e_priv *priv = c->priv;
593 mlx5e_free_sq_db(sq);
594 mlx5_wq_destroy(&sq->wq_ctrl);
595 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
598 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
600 struct mlx5e_channel *c = sq->channel;
601 struct mlx5e_priv *priv = c->priv;
602 struct mlx5_core_dev *mdev = priv->mdev;
610 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
611 sizeof(u64) * sq->wq_ctrl.buf.npages;
612 in = mlx5_vzalloc(inlen);
616 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
617 wq = MLX5_ADDR_OF(sqc, sqc, wq);
619 memcpy(sqc, param->sqc, sizeof(param->sqc));
621 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
622 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
623 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
624 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
625 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
627 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
628 MLX5_SET(wq, wq, uar_page, sq->uar.index);
629 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
630 MLX5_ADAPTER_PAGE_SHIFT);
631 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
633 mlx5_fill_page_array(&sq->wq_ctrl.buf,
634 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
636 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
643 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
645 struct mlx5e_channel *c = sq->channel;
646 struct mlx5e_priv *priv = c->priv;
647 struct mlx5_core_dev *mdev = priv->mdev;
654 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
655 in = mlx5_vzalloc(inlen);
659 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
661 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
662 MLX5_SET(sqc, sqc, state, next_state);
664 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
671 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
673 struct mlx5e_channel *c = sq->channel;
674 struct mlx5e_priv *priv = c->priv;
675 struct mlx5_core_dev *mdev = priv->mdev;
677 mlx5_core_destroy_sq(mdev, sq->sqn);
680 static int mlx5e_open_sq(struct mlx5e_channel *c,
682 struct mlx5e_sq_param *param,
687 err = mlx5e_create_sq(c, tc, param, sq);
691 err = mlx5e_enable_sq(sq, param);
695 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
699 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
700 netdev_tx_reset_queue(sq->txq);
701 netif_tx_start_queue(sq->txq);
706 mlx5e_disable_sq(sq);
708 mlx5e_destroy_sq(sq);
713 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
715 __netif_tx_lock_bh(txq);
716 netif_tx_stop_queue(txq);
717 __netif_tx_unlock_bh(txq);
720 static void mlx5e_close_sq(struct mlx5e_sq *sq)
722 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
723 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
724 netif_tx_disable_queue(sq->txq);
726 /* ensure hw is notified of all pending wqes */
727 if (mlx5e_sq_has_room_for(sq, 1))
728 mlx5e_send_nop(sq, true);
730 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
731 while (sq->cc != sq->pc) /* wait till sq is empty */
734 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
735 napi_synchronize(&sq->channel->napi);
737 mlx5e_disable_sq(sq);
738 mlx5e_destroy_sq(sq);
741 static int mlx5e_create_cq(struct mlx5e_channel *c,
742 struct mlx5e_cq_param *param,
745 struct mlx5e_priv *priv = c->priv;
746 struct mlx5_core_dev *mdev = priv->mdev;
747 struct mlx5_core_cq *mcq = &cq->mcq;
753 param->wq.buf_numa_node = cpu_to_node(c->cpu);
754 param->wq.db_numa_node = cpu_to_node(c->cpu);
755 param->eq_ix = c->ix;
757 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
762 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
767 mcq->set_ci_db = cq->wq_ctrl.db.db;
768 mcq->arm_db = cq->wq_ctrl.db.db + 1;
771 mcq->vector = param->eq_ix;
772 mcq->comp = mlx5e_completion_event;
773 mcq->event = mlx5e_cq_error_event;
775 mcq->uar = &priv->cq_uar;
777 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
778 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
789 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
791 mlx5_wq_destroy(&cq->wq_ctrl);
794 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
796 struct mlx5e_priv *priv = cq->priv;
797 struct mlx5_core_dev *mdev = priv->mdev;
798 struct mlx5_core_cq *mcq = &cq->mcq;
803 unsigned int irqn_not_used;
807 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
808 sizeof(u64) * cq->wq_ctrl.buf.npages;
809 in = mlx5_vzalloc(inlen);
813 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
815 memcpy(cqc, param->cqc, sizeof(param->cqc));
817 mlx5_fill_page_array(&cq->wq_ctrl.buf,
818 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
820 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
822 MLX5_SET(cqc, cqc, c_eqn, eqn);
823 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
824 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
825 MLX5_ADAPTER_PAGE_SHIFT);
826 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
828 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
840 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
842 struct mlx5e_priv *priv = cq->priv;
843 struct mlx5_core_dev *mdev = priv->mdev;
845 mlx5_core_destroy_cq(mdev, &cq->mcq);
848 static int mlx5e_open_cq(struct mlx5e_channel *c,
849 struct mlx5e_cq_param *param,
851 u16 moderation_usecs,
852 u16 moderation_frames)
855 struct mlx5e_priv *priv = c->priv;
856 struct mlx5_core_dev *mdev = priv->mdev;
858 err = mlx5e_create_cq(c, param, cq);
862 err = mlx5e_enable_cq(cq, param);
866 if (MLX5_CAP_GEN(mdev, cq_moderation))
867 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
873 mlx5e_destroy_cq(cq);
878 static void mlx5e_close_cq(struct mlx5e_cq *cq)
880 mlx5e_disable_cq(cq);
881 mlx5e_destroy_cq(cq);
884 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
886 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
889 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
890 struct mlx5e_channel_param *cparam)
892 struct mlx5e_priv *priv = c->priv;
896 for (tc = 0; tc < c->num_tc; tc++) {
897 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
898 priv->params.tx_cq_moderation_usec,
899 priv->params.tx_cq_moderation_pkts);
901 goto err_close_tx_cqs;
907 for (tc--; tc >= 0; tc--)
908 mlx5e_close_cq(&c->sq[tc].cq);
913 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
917 for (tc = 0; tc < c->num_tc; tc++)
918 mlx5e_close_cq(&c->sq[tc].cq);
921 static int mlx5e_open_sqs(struct mlx5e_channel *c,
922 struct mlx5e_channel_param *cparam)
927 for (tc = 0; tc < c->num_tc; tc++) {
928 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
936 for (tc--; tc >= 0; tc--)
937 mlx5e_close_sq(&c->sq[tc]);
942 static void mlx5e_close_sqs(struct mlx5e_channel *c)
946 for (tc = 0; tc < c->num_tc; tc++)
947 mlx5e_close_sq(&c->sq[tc]);
950 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
954 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
955 priv->channeltc_to_txq_map[ix][i] =
956 ix + i * priv->params.num_channels;
959 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
960 struct mlx5e_channel_param *cparam,
961 struct mlx5e_channel **cp)
963 struct net_device *netdev = priv->netdev;
964 int cpu = mlx5e_get_cpu(priv, ix);
965 struct mlx5e_channel *c;
968 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
975 c->pdev = &priv->mdev->pdev->dev;
976 c->netdev = priv->netdev;
977 c->mkey_be = cpu_to_be32(priv->mr.key);
978 c->num_tc = priv->params.num_tc;
980 mlx5e_build_channeltc_to_txq_map(priv, ix);
982 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
984 err = mlx5e_open_tx_cqs(c, cparam);
988 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
989 priv->params.rx_cq_moderation_usec,
990 priv->params.rx_cq_moderation_pkts);
992 goto err_close_tx_cqs;
994 napi_enable(&c->napi);
996 err = mlx5e_open_sqs(c, cparam);
998 goto err_disable_napi;
1000 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1004 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1013 napi_disable(&c->napi);
1014 mlx5e_close_cq(&c->rq.cq);
1017 mlx5e_close_tx_cqs(c);
1020 netif_napi_del(&c->napi);
1026 static void mlx5e_close_channel(struct mlx5e_channel *c)
1028 mlx5e_close_rq(&c->rq);
1030 napi_disable(&c->napi);
1031 mlx5e_close_cq(&c->rq.cq);
1032 mlx5e_close_tx_cqs(c);
1033 netif_napi_del(&c->napi);
1037 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1038 struct mlx5e_rq_param *param)
1040 void *rqc = param->rqc;
1041 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1043 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1044 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1045 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1046 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1047 MLX5_SET(wq, wq, pd, priv->pdn);
1049 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1050 param->wq.linear = 1;
1053 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1054 struct mlx5e_sq_param *param)
1056 void *sqc = param->sqc;
1057 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1059 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1060 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1061 MLX5_SET(wq, wq, pd, priv->pdn);
1063 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1064 param->max_inline = priv->params.tx_max_inline;
1067 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1068 struct mlx5e_cq_param *param)
1070 void *cqc = param->cqc;
1072 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1075 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1076 struct mlx5e_cq_param *param)
1078 void *cqc = param->cqc;
1080 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1082 mlx5e_build_common_cq_param(priv, param);
1085 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1086 struct mlx5e_cq_param *param)
1088 void *cqc = param->cqc;
1090 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1092 mlx5e_build_common_cq_param(priv, param);
1095 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1096 struct mlx5e_channel_param *cparam)
1098 memset(cparam, 0, sizeof(*cparam));
1100 mlx5e_build_rq_param(priv, &cparam->rq);
1101 mlx5e_build_sq_param(priv, &cparam->sq);
1102 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1103 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1106 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1108 struct mlx5e_channel_param cparam;
1109 int nch = priv->params.num_channels;
1114 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1117 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1118 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1120 if (!priv->channel || !priv->txq_to_sq_map)
1121 goto err_free_txq_to_sq_map;
1123 mlx5e_build_channel_param(priv, &cparam);
1124 for (i = 0; i < nch; i++) {
1125 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1127 goto err_close_channels;
1130 for (j = 0; j < nch; j++) {
1131 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1133 goto err_close_channels;
1139 for (i--; i >= 0; i--)
1140 mlx5e_close_channel(priv->channel[i]);
1142 err_free_txq_to_sq_map:
1143 kfree(priv->txq_to_sq_map);
1144 kfree(priv->channel);
1149 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1153 for (i = 0; i < priv->params.num_channels; i++)
1154 mlx5e_close_channel(priv->channel[i]);
1156 kfree(priv->txq_to_sq_map);
1157 kfree(priv->channel);
1160 static int mlx5e_rx_hash_fn(int hfunc)
1162 return (hfunc == ETH_RSS_HASH_TOP) ?
1163 MLX5_RX_HASH_FN_TOEPLITZ :
1164 MLX5_RX_HASH_FN_INVERTED_XOR8;
1167 static int mlx5e_bits_invert(unsigned long a, int size)
1172 for (i = 0; i < size; i++)
1173 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1178 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1182 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1185 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1186 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1188 ix = priv->params.indirection_rqt[ix];
1189 MLX5_SET(rqtc, rqtc, rq_num[i],
1190 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1191 priv->channel[ix]->rq.rqn :
1196 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1197 enum mlx5e_rqt_ix rqt_ix)
1201 case MLX5E_INDIRECTION_RQT:
1202 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1206 default: /* MLX5E_SINGLE_RQ_RQT */
1207 MLX5_SET(rqtc, rqtc, rq_num[0],
1208 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1209 priv->channel[0]->rq.rqn :
1216 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1218 struct mlx5_core_dev *mdev = priv->mdev;
1225 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1227 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1228 in = mlx5_vzalloc(inlen);
1232 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1234 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1235 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1237 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1239 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1246 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1248 struct mlx5_core_dev *mdev = priv->mdev;
1255 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1257 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1258 in = mlx5_vzalloc(inlen);
1262 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1264 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1266 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1268 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1270 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1277 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1279 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1282 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1284 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1285 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1288 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1290 if (!priv->params.lro_en)
1293 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1295 MLX5_SET(tirc, tirc, lro_enable_mask,
1296 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1297 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1298 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1299 (priv->params.lro_wqe_sz -
1300 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1301 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1302 MLX5_CAP_ETH(priv->mdev,
1303 lro_timer_supported_periods[2]));
1306 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1308 struct mlx5_core_dev *mdev = priv->mdev;
1316 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1317 in = mlx5_vzalloc(inlen);
1321 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1322 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1324 mlx5e_build_tir_ctx_lro(tirc, priv);
1326 for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1327 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1337 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1344 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1345 in = mlx5_vzalloc(inlen);
1349 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1351 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1358 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1363 for (i = 0; i < MLX5E_NUM_TT; i++) {
1364 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1373 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1375 struct mlx5e_priv *priv = netdev_priv(netdev);
1376 struct mlx5_core_dev *mdev = priv->mdev;
1380 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1384 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1386 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1387 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1388 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1390 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1394 int mlx5e_open_locked(struct net_device *netdev)
1396 struct mlx5e_priv *priv = netdev_priv(netdev);
1400 set_bit(MLX5E_STATE_OPENED, &priv->state);
1402 num_txqs = priv->params.num_channels * priv->params.num_tc;
1403 netif_set_real_num_tx_queues(netdev, num_txqs);
1404 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1406 err = mlx5e_set_dev_port_mtu(netdev);
1408 goto err_clear_state_opened_flag;
1410 err = mlx5e_open_channels(priv);
1412 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1414 goto err_clear_state_opened_flag;
1417 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1419 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1421 goto err_close_channels;
1424 mlx5e_update_carrier(priv);
1425 mlx5e_redirect_rqts(priv);
1427 schedule_delayed_work(&priv->update_stats_work, 0);
1432 mlx5e_close_channels(priv);
1433 err_clear_state_opened_flag:
1434 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1438 static int mlx5e_open(struct net_device *netdev)
1440 struct mlx5e_priv *priv = netdev_priv(netdev);
1443 mutex_lock(&priv->state_lock);
1444 err = mlx5e_open_locked(netdev);
1445 mutex_unlock(&priv->state_lock);
1450 int mlx5e_close_locked(struct net_device *netdev)
1452 struct mlx5e_priv *priv = netdev_priv(netdev);
1454 /* May already be CLOSED in case a previous configuration operation
1455 * (e.g RX/TX queue size change) that involves close&open failed.
1457 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1460 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1462 mlx5e_redirect_rqts(priv);
1463 netif_carrier_off(priv->netdev);
1464 mlx5e_close_channels(priv);
1469 static int mlx5e_close(struct net_device *netdev)
1471 struct mlx5e_priv *priv = netdev_priv(netdev);
1474 mutex_lock(&priv->state_lock);
1475 err = mlx5e_close_locked(netdev);
1476 mutex_unlock(&priv->state_lock);
1481 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1482 struct mlx5e_rq *rq,
1483 struct mlx5e_rq_param *param)
1485 struct mlx5_core_dev *mdev = priv->mdev;
1486 void *rqc = param->rqc;
1487 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1490 param->wq.db_numa_node = param->wq.buf_numa_node;
1492 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1502 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1503 struct mlx5e_cq *cq,
1504 struct mlx5e_cq_param *param)
1506 struct mlx5_core_dev *mdev = priv->mdev;
1507 struct mlx5_core_cq *mcq = &cq->mcq;
1512 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1517 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1520 mcq->set_ci_db = cq->wq_ctrl.db.db;
1521 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1522 *mcq->set_ci_db = 0;
1524 mcq->vector = param->eq_ix;
1525 mcq->comp = mlx5e_completion_event;
1526 mcq->event = mlx5e_cq_error_event;
1528 mcq->uar = &priv->cq_uar;
1535 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1537 struct mlx5e_cq_param cq_param;
1538 struct mlx5e_rq_param rq_param;
1539 struct mlx5e_rq *rq = &priv->drop_rq;
1540 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1543 memset(&cq_param, 0, sizeof(cq_param));
1544 memset(&rq_param, 0, sizeof(rq_param));
1545 mlx5e_build_rx_cq_param(priv, &cq_param);
1546 mlx5e_build_rq_param(priv, &rq_param);
1548 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1552 err = mlx5e_enable_cq(cq, &cq_param);
1554 goto err_destroy_cq;
1556 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1558 goto err_disable_cq;
1560 err = mlx5e_enable_rq(rq, &rq_param);
1562 goto err_destroy_rq;
1567 mlx5e_destroy_rq(&priv->drop_rq);
1570 mlx5e_disable_cq(&priv->drop_rq.cq);
1573 mlx5e_destroy_cq(&priv->drop_rq.cq);
1578 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1580 mlx5e_disable_rq(&priv->drop_rq);
1581 mlx5e_destroy_rq(&priv->drop_rq);
1582 mlx5e_disable_cq(&priv->drop_rq.cq);
1583 mlx5e_destroy_cq(&priv->drop_rq.cq);
1586 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1588 struct mlx5_core_dev *mdev = priv->mdev;
1589 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1590 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1592 memset(in, 0, sizeof(in));
1594 MLX5_SET(tisc, tisc, prio, tc);
1595 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1597 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1600 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1602 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1605 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1610 for (tc = 0; tc < priv->params.num_tc; tc++) {
1611 err = mlx5e_create_tis(priv, tc);
1613 goto err_close_tises;
1619 for (tc--; tc >= 0; tc--)
1620 mlx5e_destroy_tis(priv, tc);
1625 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1629 for (tc = 0; tc < priv->params.num_tc; tc++)
1630 mlx5e_destroy_tis(priv, tc);
1633 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1635 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1637 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1639 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1640 MLX5_HASH_FIELD_SEL_DST_IP)
1642 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1643 MLX5_HASH_FIELD_SEL_DST_IP |\
1644 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1645 MLX5_HASH_FIELD_SEL_L4_DPORT)
1647 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1648 MLX5_HASH_FIELD_SEL_DST_IP |\
1649 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1651 mlx5e_build_tir_ctx_lro(tirc, priv);
1653 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1657 MLX5_SET(tirc, tirc, indirect_table,
1658 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1659 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1662 MLX5_SET(tirc, tirc, indirect_table,
1663 priv->rqtn[MLX5E_INDIRECTION_RQT]);
1664 MLX5_SET(tirc, tirc, rx_hash_fn,
1665 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1666 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1667 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1668 rx_hash_toeplitz_key);
1669 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1670 rx_hash_toeplitz_key);
1672 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1673 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1679 case MLX5E_TT_IPV4_TCP:
1680 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1681 MLX5_L3_PROT_TYPE_IPV4);
1682 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1683 MLX5_L4_PROT_TYPE_TCP);
1684 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1685 MLX5_HASH_IP_L4PORTS);
1688 case MLX5E_TT_IPV6_TCP:
1689 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1690 MLX5_L3_PROT_TYPE_IPV6);
1691 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1692 MLX5_L4_PROT_TYPE_TCP);
1693 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1694 MLX5_HASH_IP_L4PORTS);
1697 case MLX5E_TT_IPV4_UDP:
1698 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1699 MLX5_L3_PROT_TYPE_IPV4);
1700 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1701 MLX5_L4_PROT_TYPE_UDP);
1702 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1703 MLX5_HASH_IP_L4PORTS);
1706 case MLX5E_TT_IPV6_UDP:
1707 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1708 MLX5_L3_PROT_TYPE_IPV6);
1709 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1710 MLX5_L4_PROT_TYPE_UDP);
1711 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1712 MLX5_HASH_IP_L4PORTS);
1715 case MLX5E_TT_IPV4_IPSEC_AH:
1716 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1717 MLX5_L3_PROT_TYPE_IPV4);
1718 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1719 MLX5_HASH_IP_IPSEC_SPI);
1722 case MLX5E_TT_IPV6_IPSEC_AH:
1723 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1724 MLX5_L3_PROT_TYPE_IPV6);
1725 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1726 MLX5_HASH_IP_IPSEC_SPI);
1729 case MLX5E_TT_IPV4_IPSEC_ESP:
1730 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1731 MLX5_L3_PROT_TYPE_IPV4);
1732 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1733 MLX5_HASH_IP_IPSEC_SPI);
1736 case MLX5E_TT_IPV6_IPSEC_ESP:
1737 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1738 MLX5_L3_PROT_TYPE_IPV6);
1739 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1740 MLX5_HASH_IP_IPSEC_SPI);
1744 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1745 MLX5_L3_PROT_TYPE_IPV4);
1746 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1751 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1752 MLX5_L3_PROT_TYPE_IPV6);
1753 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1759 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1761 struct mlx5_core_dev *mdev = priv->mdev;
1767 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1768 in = mlx5_vzalloc(inlen);
1772 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1774 mlx5e_build_tir_ctx(priv, tirc, tt);
1776 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1783 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1785 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1788 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1793 for (i = 0; i < MLX5E_NUM_TT; i++) {
1794 err = mlx5e_create_tir(priv, i);
1796 goto err_destroy_tirs;
1802 for (i--; i >= 0; i--)
1803 mlx5e_destroy_tir(priv, i);
1808 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1812 for (i = 0; i < MLX5E_NUM_TT; i++)
1813 mlx5e_destroy_tir(priv, i);
1816 static struct rtnl_link_stats64 *
1817 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1819 struct mlx5e_priv *priv = netdev_priv(dev);
1820 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1822 stats->rx_packets = vstats->rx_packets;
1823 stats->rx_bytes = vstats->rx_bytes;
1824 stats->tx_packets = vstats->tx_packets;
1825 stats->tx_bytes = vstats->tx_bytes;
1826 stats->multicast = vstats->rx_multicast_packets +
1827 vstats->tx_multicast_packets;
1828 stats->tx_errors = vstats->tx_error_packets;
1829 stats->rx_errors = vstats->rx_error_packets;
1830 stats->tx_dropped = vstats->tx_queue_dropped;
1831 stats->rx_crc_errors = 0;
1832 stats->rx_length_errors = 0;
1837 static void mlx5e_set_rx_mode(struct net_device *dev)
1839 struct mlx5e_priv *priv = netdev_priv(dev);
1841 schedule_work(&priv->set_rx_mode_work);
1844 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1846 struct mlx5e_priv *priv = netdev_priv(netdev);
1847 struct sockaddr *saddr = addr;
1849 if (!is_valid_ether_addr(saddr->sa_data))
1850 return -EADDRNOTAVAIL;
1852 netif_addr_lock_bh(netdev);
1853 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1854 netif_addr_unlock_bh(netdev);
1856 schedule_work(&priv->set_rx_mode_work);
1861 static int mlx5e_set_features(struct net_device *netdev,
1862 netdev_features_t features)
1864 struct mlx5e_priv *priv = netdev_priv(netdev);
1866 netdev_features_t changes = features ^ netdev->features;
1868 mutex_lock(&priv->state_lock);
1870 if (changes & NETIF_F_LRO) {
1871 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1874 mlx5e_close_locked(priv->netdev);
1876 priv->params.lro_en = !!(features & NETIF_F_LRO);
1877 err = mlx5e_modify_tirs_lro(priv);
1879 mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
1883 err = mlx5e_open_locked(priv->netdev);
1886 mutex_unlock(&priv->state_lock);
1888 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1889 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1890 mlx5e_enable_vlan_filter(priv);
1892 mlx5e_disable_vlan_filter(priv);
1898 #define MXL5_HW_MIN_MTU 64
1899 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
1901 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1903 struct mlx5e_priv *priv = netdev_priv(netdev);
1904 struct mlx5_core_dev *mdev = priv->mdev;
1910 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1912 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1913 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
1915 if (new_mtu > max_mtu || new_mtu < min_mtu) {
1917 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
1918 __func__, new_mtu, min_mtu, max_mtu);
1922 mutex_lock(&priv->state_lock);
1924 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1926 mlx5e_close_locked(netdev);
1928 netdev->mtu = new_mtu;
1931 err = mlx5e_open_locked(netdev);
1933 mutex_unlock(&priv->state_lock);
1938 static struct net_device_ops mlx5e_netdev_ops = {
1939 .ndo_open = mlx5e_open,
1940 .ndo_stop = mlx5e_close,
1941 .ndo_start_xmit = mlx5e_xmit,
1942 .ndo_get_stats64 = mlx5e_get_stats,
1943 .ndo_set_rx_mode = mlx5e_set_rx_mode,
1944 .ndo_set_mac_address = mlx5e_set_mac,
1945 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
1946 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
1947 .ndo_set_features = mlx5e_set_features,
1948 .ndo_change_mtu = mlx5e_change_mtu,
1951 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1953 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1955 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1956 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1957 !MLX5_CAP_ETH(mdev, csum_cap) ||
1958 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1959 !MLX5_CAP_ETH(mdev, vlan_cap) ||
1960 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1961 MLX5_CAP_FLOWTABLE(mdev,
1962 flow_table_properties_nic_receive.max_ft_level)
1964 mlx5_core_warn(mdev,
1965 "Not creating net device, some required device capabilities are missing\n");
1968 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
1969 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
1970 if (!MLX5_CAP_GEN(mdev, cq_moderation))
1971 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
1976 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
1978 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1980 return bf_buf_size -
1981 sizeof(struct mlx5e_tx_wqe) +
1982 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
1985 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
1990 for (i = 0; i < len; i++)
1991 indirection_rqt[i] = i % num_channels;
1994 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1995 struct net_device *netdev,
1998 struct mlx5e_priv *priv = netdev_priv(netdev);
2000 priv->params.log_sq_size =
2001 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2002 priv->params.log_rq_size =
2003 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2004 priv->params.rx_cq_moderation_usec =
2005 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2006 priv->params.rx_cq_moderation_pkts =
2007 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2008 priv->params.tx_cq_moderation_usec =
2009 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2010 priv->params.tx_cq_moderation_pkts =
2011 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2012 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2013 priv->params.min_rx_wqes =
2014 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2015 priv->params.num_tc = 1;
2016 priv->params.default_vlan_prio = 0;
2017 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
2019 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2020 sizeof(priv->params.toeplitz_hash_key));
2022 mlx5e_build_default_indir_rqt(priv->params.indirection_rqt,
2023 MLX5E_INDIR_RQT_SIZE, num_channels);
2025 priv->params.lro_wqe_sz =
2026 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2029 priv->netdev = netdev;
2030 priv->params.num_channels = num_channels;
2031 priv->default_vlan_prio = priv->params.default_vlan_prio;
2033 spin_lock_init(&priv->async_events_spinlock);
2034 mutex_init(&priv->state_lock);
2036 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2037 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2038 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2041 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2043 struct mlx5e_priv *priv = netdev_priv(netdev);
2045 mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
2048 static void mlx5e_build_netdev(struct net_device *netdev)
2050 struct mlx5e_priv *priv = netdev_priv(netdev);
2051 struct mlx5_core_dev *mdev = priv->mdev;
2053 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2055 if (priv->params.num_tc > 1)
2056 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
2058 netdev->netdev_ops = &mlx5e_netdev_ops;
2059 netdev->watchdog_timeo = 15 * HZ;
2061 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2063 netdev->vlan_features |= NETIF_F_SG;
2064 netdev->vlan_features |= NETIF_F_IP_CSUM;
2065 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2066 netdev->vlan_features |= NETIF_F_GRO;
2067 netdev->vlan_features |= NETIF_F_TSO;
2068 netdev->vlan_features |= NETIF_F_TSO6;
2069 netdev->vlan_features |= NETIF_F_RXCSUM;
2070 netdev->vlan_features |= NETIF_F_RXHASH;
2072 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2073 netdev->vlan_features |= NETIF_F_LRO;
2075 netdev->hw_features = netdev->vlan_features;
2076 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
2077 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2078 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2080 netdev->features = netdev->hw_features;
2081 if (!priv->params.lro_en)
2082 netdev->features &= ~NETIF_F_LRO;
2084 netdev->features |= NETIF_F_HIGHDMA;
2086 netdev->priv_flags |= IFF_UNICAST_FLT;
2088 mlx5e_set_netdev_dev_addr(netdev);
2091 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2092 struct mlx5_core_mr *mr)
2094 struct mlx5_core_dev *mdev = priv->mdev;
2095 struct mlx5_create_mkey_mbox_in *in;
2098 in = mlx5_vzalloc(sizeof(*in));
2102 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2103 MLX5_PERM_LOCAL_READ |
2104 MLX5_ACCESS_MODE_PA;
2105 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2106 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2108 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2116 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2118 struct net_device *netdev;
2119 struct mlx5e_priv *priv;
2120 int nch = mlx5e_get_max_num_channels(mdev);
2123 if (mlx5e_check_required_hca_cap(mdev))
2126 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), nch, nch);
2128 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2132 mlx5e_build_netdev_priv(mdev, netdev, nch);
2133 mlx5e_build_netdev(netdev);
2135 netif_carrier_off(netdev);
2137 priv = netdev_priv(netdev);
2139 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2141 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2142 goto err_free_netdev;
2145 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2147 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2148 goto err_unmap_free_uar;
2151 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2153 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2154 goto err_dealloc_pd;
2157 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2159 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2160 goto err_dealloc_transport_domain;
2163 err = mlx5e_create_tises(priv);
2165 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2166 goto err_destroy_mkey;
2169 err = mlx5e_open_drop_rq(priv);
2171 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2172 goto err_destroy_tises;
2175 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2177 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2178 goto err_close_drop_rq;
2181 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2183 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2184 goto err_destroy_rqt_indir;
2187 err = mlx5e_create_tirs(priv);
2189 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2190 goto err_destroy_rqt_single;
2193 err = mlx5e_create_flow_tables(priv);
2195 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2196 goto err_destroy_tirs;
2199 mlx5e_init_eth_addr(priv);
2201 err = register_netdev(netdev);
2203 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2204 goto err_destroy_flow_tables;
2207 mlx5e_enable_async_events(priv);
2208 schedule_work(&priv->set_rx_mode_work);
2212 err_destroy_flow_tables:
2213 mlx5e_destroy_flow_tables(priv);
2216 mlx5e_destroy_tirs(priv);
2218 err_destroy_rqt_single:
2219 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2221 err_destroy_rqt_indir:
2222 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2225 mlx5e_close_drop_rq(priv);
2228 mlx5e_destroy_tises(priv);
2231 mlx5_core_destroy_mkey(mdev, &priv->mr);
2233 err_dealloc_transport_domain:
2234 mlx5_dealloc_transport_domain(mdev, priv->tdn);
2237 mlx5_core_dealloc_pd(mdev, priv->pdn);
2240 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2243 free_netdev(netdev);
2248 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2250 struct mlx5e_priv *priv = vpriv;
2251 struct net_device *netdev = priv->netdev;
2253 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2255 schedule_work(&priv->set_rx_mode_work);
2256 mlx5e_disable_async_events(priv);
2257 flush_scheduled_work();
2258 unregister_netdev(netdev);
2259 mlx5e_destroy_flow_tables(priv);
2260 mlx5e_destroy_tirs(priv);
2261 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2262 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2263 mlx5e_close_drop_rq(priv);
2264 mlx5e_destroy_tises(priv);
2265 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
2266 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
2267 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2268 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2269 free_netdev(netdev);
2272 static void *mlx5e_get_netdev(void *vpriv)
2274 struct mlx5e_priv *priv = vpriv;
2276 return priv->netdev;
2279 static struct mlx5_interface mlx5e_interface = {
2280 .add = mlx5e_create_netdev,
2281 .remove = mlx5e_destroy_netdev,
2282 .event = mlx5e_async_event,
2283 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2284 .get_dev = mlx5e_get_netdev,
2287 void mlx5e_init(void)
2289 mlx5_register_interface(&mlx5e_interface);
2292 void mlx5e_cleanup(void)
2294 mlx5_unregister_interface(&mlx5e_interface);