2 * arch/m68k/q40/config.c
4 * Copyright (C) 1999 Richard Zidlicky
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file README.legal in the main directory of this archive
15 #include <linux/errno.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
19 #include <linux/tty.h>
20 #include <linux/console.h>
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <linux/major.h>
24 #include <linux/serial_reg.h>
25 #include <linux/rtc.h>
26 #include <linux/vt_kern.h>
27 #include <linux/bcd.h>
28 #include <linux/platform_device.h>
31 #include <asm/bootinfo.h>
32 #include <asm/pgtable.h>
33 #include <asm/setup.h>
35 #include <asm/traps.h>
36 #include <asm/machdep.h>
37 #include <asm/q40_master.h>
39 extern void q40_init_IRQ(void);
40 static void q40_get_model(char *model);
41 extern void q40_sched_init(irq_handler_t handler);
43 static int q40_hwclk(int, struct rtc_time *);
44 static unsigned int q40_get_ss(void);
45 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
46 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
48 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
50 static void q40_mem_console_write(struct console *co, const char *b,
55 static struct console q40_console_driver = {
57 .write = q40_mem_console_write,
58 .flags = CON_PRINTBUFFER,
63 /* early debugging function:*/
64 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
67 static void q40_mem_console_write(struct console *co, const char *s,
72 if (count < _cpleft) {
81 static int __init q40_debug_setup(char *arg)
83 /* useful for early debugging stages - writes kernel messages into SRAM */
84 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
85 /*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
86 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
87 register_console(&q40_console_driver);
92 early_param("debug", q40_debug_setup);
95 void printq40(char *str)
98 char *p = q40_mem_cptr;
100 while (l-- > 0 && _cpleft-- > 0) {
110 #ifdef CONFIG_HEARTBEAT
111 static void q40_heartbeat(int on)
123 static void q40_reset(void)
126 pr_info("*******************************************\n"
127 "Called q40_reset : press the RESET button!!\n"
128 "*******************************************\n");
134 static void q40_halt(void)
137 pr_info("*******************\n"
139 "*******************\n");
145 static void q40_get_model(char *model)
147 sprintf(model, "Q40");
150 static unsigned int serports[] =
152 0x3f8,0x2f8,0x3e8,0x2e8,0
155 static void __init q40_disable_irqs(void)
160 while ((i = serports[j++]))
161 outb(0, i + UART_IER);
162 master_outb(0, EXT_ENABLE_REG);
163 master_outb(0, KEY_IRQ_ENABLE_REG);
166 void __init config_q40(void)
168 mach_sched_init = q40_sched_init;
170 mach_init_IRQ = q40_init_IRQ;
171 mach_hwclk = q40_hwclk;
172 mach_get_ss = q40_get_ss;
173 mach_get_rtc_pll = q40_get_rtc_pll;
174 mach_set_rtc_pll = q40_set_rtc_pll;
176 mach_reset = q40_reset;
177 mach_get_model = q40_get_model;
179 #if IS_ENABLED(CONFIG_INPUT_M68K_BEEP)
180 mach_beep = q40_mksound;
182 #ifdef CONFIG_HEARTBEAT
183 mach_heartbeat = q40_heartbeat;
185 mach_halt = q40_halt;
187 /* disable a few things that SMSQ might have left enabled */
190 /* no DMA at all, but ide-scsi requires it.. make sure
191 * all physical RAM fits into the boundary - otherwise
192 * allocator may play costly and useless tricks */
193 mach_max_dma_address = 1024*1024*1024;
197 int __init q40_parse_bootinfo(const struct bi_record *rec)
203 * Looks like op is non-zero for setting the clock, and zero for
206 * struct hwclk_time {
207 * unsigned sec; 0..59
208 * unsigned min; 0..59
209 * unsigned hour; 0..23
210 * unsigned day; 1..31
211 * unsigned mon; 0..11
212 * unsigned year; 00...
213 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
217 static int q40_hwclk(int op, struct rtc_time *t)
221 Q40_RTC_CTRL |= Q40_RTC_WRITE;
223 Q40_RTC_SECS = bin2bcd(t->tm_sec);
224 Q40_RTC_MINS = bin2bcd(t->tm_min);
225 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
226 Q40_RTC_DATE = bin2bcd(t->tm_mday);
227 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
228 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
230 Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
232 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
235 Q40_RTC_CTRL |= Q40_RTC_READ;
237 t->tm_year = bcd2bin (Q40_RTC_YEAR);
238 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
239 t->tm_mday = bcd2bin (Q40_RTC_DATE);
240 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
241 t->tm_min = bcd2bin (Q40_RTC_MINS);
242 t->tm_sec = bcd2bin (Q40_RTC_SECS);
244 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
248 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
254 static unsigned int q40_get_ss(void)
256 return bcd2bin(Q40_RTC_SECS);
259 /* get and set PLL calibration of RTC clock */
260 #define Q40_RTC_PLL_MASK ((1<<5)-1)
261 #define Q40_RTC_PLL_SIGN (1<<5)
263 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
265 int tmp = Q40_RTC_CTRL;
268 pll->pll_value = tmp & Q40_RTC_PLL_MASK;
269 if (tmp & Q40_RTC_PLL_SIGN)
270 pll->pll_value = -pll->pll_value;
273 pll->pll_posmult = 512;
274 pll->pll_negmult = 256;
275 pll->pll_clock = 125829120;
280 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
282 if (!pll->pll_ctrl) {
283 /* the docs are a bit unclear so I am doublesetting */
284 /* RTC_WRITE here ... */
285 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
287 Q40_RTC_CTRL |= Q40_RTC_WRITE;
289 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
295 static __init int q40_add_kbd_device(void)
297 struct platform_device *pdev;
302 pdev = platform_device_register_simple("q40kbd", -1, NULL, 0);
303 return PTR_ERR_OR_ZERO(pdev);
305 arch_initcall(q40_add_kbd_device);