codecs/wsa881x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2015-2017, The Linux Foundation.
   3 // Copyright (c) 2019, Linaro Limited
   4
   5 #include <linux/bitops.h>
   6 #include <linux/gpio.h>
   7 #include <linux/gpio/consumer.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_gpio.h>
  12 #include <linux/regmap.h>
  13 #include <linux/slab.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/soundwire/sdw.h>
  16 #include <linux/soundwire/sdw_registers.h>
  17 #include <linux/soundwire/sdw_type.h>
  18 #include <sound/soc.h>
  19 #include <sound/tlv.h>
  20
  21 #define WSA881X_DIGITAL_BASE            0x3000
  22 #define WSA881X_ANALOG_BASE             0x3100
  23
  24 /* Digital register address space */
  25 #define WSA881X_CHIP_ID0                        (WSA881X_DIGITAL_BASE + 0x0000)
  26 #define WSA881X_CHIP_ID1                        (WSA881X_DIGITAL_BASE + 0x0001)
  27 #define WSA881X_CHIP_ID2                        (WSA881X_DIGITAL_BASE + 0x0002)
  28 #define WSA881X_CHIP_ID3                        (WSA881X_DIGITAL_BASE + 0x0003)
  29 #define WSA881X_BUS_ID                          (WSA881X_DIGITAL_BASE + 0x0004)
  30 #define WSA881X_CDC_RST_CTL                     (WSA881X_DIGITAL_BASE + 0x0005)
  31 #define WSA881X_CDC_TOP_CLK_CTL                 (WSA881X_DIGITAL_BASE + 0x0006)
  32 #define WSA881X_CDC_ANA_CLK_CTL                 (WSA881X_DIGITAL_BASE + 0x0007)
  33 #define WSA881X_CDC_DIG_CLK_CTL                 (WSA881X_DIGITAL_BASE + 0x0008)
  34 #define WSA881X_CLOCK_CONFIG                    (WSA881X_DIGITAL_BASE + 0x0009)
  35 #define WSA881X_ANA_CTL                         (WSA881X_DIGITAL_BASE + 0x000A)
  36 #define WSA881X_SWR_RESET_EN                    (WSA881X_DIGITAL_BASE + 0x000B)
  37 #define WSA881X_RESET_CTL                       (WSA881X_DIGITAL_BASE + 0x000C)
  38 #define WSA881X_TADC_VALUE_CTL                  (WSA881X_DIGITAL_BASE + 0x000F)
  39 #define WSA881X_TEMP_DETECT_CTL                 (WSA881X_DIGITAL_BASE + 0x0010)
  40 #define WSA881X_TEMP_MSB                        (WSA881X_DIGITAL_BASE + 0x0011)
  41 #define WSA881X_TEMP_LSB                        (WSA881X_DIGITAL_BASE + 0x0012)
  42 #define WSA881X_TEMP_CONFIG0                    (WSA881X_DIGITAL_BASE + 0x0013)
  43 #define WSA881X_TEMP_CONFIG1                    (WSA881X_DIGITAL_BASE + 0x0014)
  44 #define WSA881X_CDC_CLIP_CTL                    (WSA881X_DIGITAL_BASE + 0x0015)
  45 #define WSA881X_SDM_PDM9_LSB                    (WSA881X_DIGITAL_BASE + 0x0016)
  46 #define WSA881X_SDM_PDM9_MSB                    (WSA881X_DIGITAL_BASE + 0x0017)
  47 #define WSA881X_CDC_RX_CTL                      (WSA881X_DIGITAL_BASE + 0x0018)
  48 #define WSA881X_DEM_BYPASS_DATA0                (WSA881X_DIGITAL_BASE + 0x0019)
  49 #define WSA881X_DEM_BYPASS_DATA1                (WSA881X_DIGITAL_BASE + 0x001A)
  50 #define WSA881X_DEM_BYPASS_DATA2                (WSA881X_DIGITAL_BASE + 0x001B)
  51 #define WSA881X_DEM_BYPASS_DATA3                (WSA881X_DIGITAL_BASE + 0x001C)
  52 #define WSA881X_OTP_CTRL0                       (WSA881X_DIGITAL_BASE + 0x001D)
  53 #define WSA881X_OTP_CTRL1                       (WSA881X_DIGITAL_BASE + 0x001E)
  54 #define WSA881X_HDRIVE_CTL_GROUP1               (WSA881X_DIGITAL_BASE + 0x001F)
  55 #define WSA881X_INTR_MODE                       (WSA881X_DIGITAL_BASE + 0x0020)
  56 #define WSA881X_INTR_MASK                       (WSA881X_DIGITAL_BASE + 0x0021)
  57 #define WSA881X_INTR_STATUS                     (WSA881X_DIGITAL_BASE + 0x0022)
  58 #define WSA881X_INTR_CLEAR                      (WSA881X_DIGITAL_BASE + 0x0023)
  59 #define WSA881X_INTR_LEVEL                      (WSA881X_DIGITAL_BASE + 0x0024)
  60 #define WSA881X_INTR_SET                        (WSA881X_DIGITAL_BASE + 0x0025)
  61 #define WSA881X_INTR_TEST                       (WSA881X_DIGITAL_BASE + 0x0026)
  62 #define WSA881X_PDM_TEST_MODE                   (WSA881X_DIGITAL_BASE + 0x0030)
  63 #define WSA881X_ATE_TEST_MODE                   (WSA881X_DIGITAL_BASE + 0x0031)
  64 #define WSA881X_PIN_CTL_MODE                    (WSA881X_DIGITAL_BASE + 0x0032)
  65 #define WSA881X_PIN_CTL_OE                      (WSA881X_DIGITAL_BASE + 0x0033)
  66 #define WSA881X_PIN_WDATA_IOPAD                 (WSA881X_DIGITAL_BASE + 0x0034)
  67 #define WSA881X_PIN_STATUS                      (WSA881X_DIGITAL_BASE + 0x0035)
  68 #define WSA881X_DIG_DEBUG_MODE                  (WSA881X_DIGITAL_BASE + 0x0037)
  69 #define WSA881X_DIG_DEBUG_SEL                   (WSA881X_DIGITAL_BASE + 0x0038)
  70 #define WSA881X_DIG_DEBUG_EN                    (WSA881X_DIGITAL_BASE + 0x0039)
  71 #define WSA881X_SWR_HM_TEST1                    (WSA881X_DIGITAL_BASE + 0x003B)
  72 #define WSA881X_SWR_HM_TEST2                    (WSA881X_DIGITAL_BASE + 0x003C)
  73 #define WSA881X_TEMP_DETECT_DBG_CTL             (WSA881X_DIGITAL_BASE + 0x003D)
  74 #define WSA881X_TEMP_DEBUG_MSB                  (WSA881X_DIGITAL_BASE + 0x003E)
  75 #define WSA881X_TEMP_DEBUG_LSB                  (WSA881X_DIGITAL_BASE + 0x003F)
  76 #define WSA881X_SAMPLE_EDGE_SEL                 (WSA881X_DIGITAL_BASE + 0x0044)
  77 #define WSA881X_IOPAD_CTL                       (WSA881X_DIGITAL_BASE + 0x0045)
  78 #define WSA881X_SPARE_0                         (WSA881X_DIGITAL_BASE + 0x0050)
  79 #define WSA881X_SPARE_1                         (WSA881X_DIGITAL_BASE + 0x0051)
  80 #define WSA881X_SPARE_2                         (WSA881X_DIGITAL_BASE + 0x0052)
  81 #define WSA881X_OTP_REG_0                       (WSA881X_DIGITAL_BASE + 0x0080)
  82 #define WSA881X_OTP_REG_1                       (WSA881X_DIGITAL_BASE + 0x0081)
  83 #define WSA881X_OTP_REG_2                       (WSA881X_DIGITAL_BASE + 0x0082)
  84 #define WSA881X_OTP_REG_3                       (WSA881X_DIGITAL_BASE + 0x0083)
  85 #define WSA881X_OTP_REG_4                       (WSA881X_DIGITAL_BASE + 0x0084)
  86 #define WSA881X_OTP_REG_5                       (WSA881X_DIGITAL_BASE + 0x0085)
  87 #define WSA881X_OTP_REG_6                       (WSA881X_DIGITAL_BASE + 0x0086)
  88 #define WSA881X_OTP_REG_7                       (WSA881X_DIGITAL_BASE + 0x0087)
  89 #define WSA881X_OTP_REG_8                       (WSA881X_DIGITAL_BASE + 0x0088)
  90 #define WSA881X_OTP_REG_9                       (WSA881X_DIGITAL_BASE + 0x0089)
  91 #define WSA881X_OTP_REG_10                      (WSA881X_DIGITAL_BASE + 0x008A)
  92 #define WSA881X_OTP_REG_11                      (WSA881X_DIGITAL_BASE + 0x008B)
  93 #define WSA881X_OTP_REG_12                      (WSA881X_DIGITAL_BASE + 0x008C)
  94 #define WSA881X_OTP_REG_13                      (WSA881X_DIGITAL_BASE + 0x008D)
  95 #define WSA881X_OTP_REG_14                      (WSA881X_DIGITAL_BASE + 0x008E)
  96 #define WSA881X_OTP_REG_15                      (WSA881X_DIGITAL_BASE + 0x008F)
  97 #define WSA881X_OTP_REG_16                      (WSA881X_DIGITAL_BASE + 0x0090)
  98 #define WSA881X_OTP_REG_17                      (WSA881X_DIGITAL_BASE + 0x0091)
  99 #define WSA881X_OTP_REG_18                      (WSA881X_DIGITAL_BASE + 0x0092)
 100 #define WSA881X_OTP_REG_19                      (WSA881X_DIGITAL_BASE + 0x0093)
 101 #define WSA881X_OTP_REG_20                      (WSA881X_DIGITAL_BASE + 0x0094)
 102 #define WSA881X_OTP_REG_21                      (WSA881X_DIGITAL_BASE + 0x0095)
 103 #define WSA881X_OTP_REG_22                      (WSA881X_DIGITAL_BASE + 0x0096)
 104 #define WSA881X_OTP_REG_23                      (WSA881X_DIGITAL_BASE + 0x0097)
 105 #define WSA881X_OTP_REG_24                      (WSA881X_DIGITAL_BASE + 0x0098)
 106 #define WSA881X_OTP_REG_25                      (WSA881X_DIGITAL_BASE + 0x0099)
 107 #define WSA881X_OTP_REG_26                      (WSA881X_DIGITAL_BASE + 0x009A)
 108 #define WSA881X_OTP_REG_27                      (WSA881X_DIGITAL_BASE + 0x009B)
 109 #define WSA881X_OTP_REG_28                      (WSA881X_DIGITAL_BASE + 0x009C)
 110 #define WSA881X_OTP_REG_29                      (WSA881X_DIGITAL_BASE + 0x009D)
 111 #define WSA881X_OTP_REG_30                      (WSA881X_DIGITAL_BASE + 0x009E)
 112 #define WSA881X_OTP_REG_31                      (WSA881X_DIGITAL_BASE + 0x009F)
 113 #define WSA881X_OTP_REG_63                      (WSA881X_DIGITAL_BASE + 0x00BF)
 114
 115 /* Analog Register address space */
 116 #define WSA881X_BIAS_REF_CTRL                   (WSA881X_ANALOG_BASE + 0x0000)
 117 #define WSA881X_BIAS_TEST                       (WSA881X_ANALOG_BASE + 0x0001)
 118 #define WSA881X_BIAS_BIAS                       (WSA881X_ANALOG_BASE + 0x0002)
 119 #define WSA881X_TEMP_OP                         (WSA881X_ANALOG_BASE + 0x0003)
 120 #define WSA881X_TEMP_IREF_CTRL                  (WSA881X_ANALOG_BASE + 0x0004)
 121 #define WSA881X_TEMP_ISENS_CTRL                 (WSA881X_ANALOG_BASE + 0x0005)
 122 #define WSA881X_TEMP_CLK_CTRL                   (WSA881X_ANALOG_BASE + 0x0006)
 123 #define WSA881X_TEMP_TEST                       (WSA881X_ANALOG_BASE + 0x0007)
 124 #define WSA881X_TEMP_BIAS                       (WSA881X_ANALOG_BASE + 0x0008)
 125 #define WSA881X_TEMP_ADC_CTRL                   (WSA881X_ANALOG_BASE + 0x0009)
 126 #define WSA881X_TEMP_DOUT_MSB                   (WSA881X_ANALOG_BASE + 0x000A)
 127 #define WSA881X_TEMP_DOUT_LSB                   (WSA881X_ANALOG_BASE + 0x000B)
 128 #define WSA881X_ADC_EN_MODU_V                   (WSA881X_ANALOG_BASE + 0x0010)
 129 #define WSA881X_ADC_EN_MODU_I                   (WSA881X_ANALOG_BASE + 0x0011)
 130 #define WSA881X_ADC_EN_DET_TEST_V               (WSA881X_ANALOG_BASE + 0x0012)
 131 #define WSA881X_ADC_EN_DET_TEST_I               (WSA881X_ANALOG_BASE + 0x0013)
 132 #define WSA881X_ADC_SEL_IBIAS                   (WSA881X_ANALOG_BASE + 0x0014)
 133 #define WSA881X_ADC_EN_SEL_IBAIS                (WSA881X_ANALOG_BASE + 0x0015)
 134 #define WSA881X_SPKR_DRV_EN                     (WSA881X_ANALOG_BASE + 0x001A)
 135 #define WSA881X_SPKR_DRV_GAIN                   (WSA881X_ANALOG_BASE + 0x001B)
 136 #define WSA881X_PA_GAIN_SEL_MASK                BIT(3)
 137 #define WSA881X_PA_GAIN_SEL_REG                 BIT(3)
 138 #define WSA881X_PA_GAIN_SEL_DRE                 0
 139 #define WSA881X_SPKR_PAG_GAIN_MASK              GENMASK(7, 4)
 140 #define WSA881X_SPKR_DAC_CTL                    (WSA881X_ANALOG_BASE + 0x001C)
 141 #define WSA881X_SPKR_DRV_DBG                    (WSA881X_ANALOG_BASE + 0x001D)
 142 #define WSA881X_SPKR_PWRSTG_DBG                 (WSA881X_ANALOG_BASE + 0x001E)
 143 #define WSA881X_SPKR_OCP_CTL                    (WSA881X_ANALOG_BASE + 0x001F)
 144 #define WSA881X_SPKR_OCP_MASK                   GENMASK(7, 6)
 145 #define WSA881X_SPKR_OCP_EN                     BIT(7)
 146 #define WSA881X_SPKR_OCP_HOLD                   BIT(6)
 147 #define WSA881X_SPKR_CLIP_CTL                   (WSA881X_ANALOG_BASE + 0x0020)
 148 #define WSA881X_SPKR_BBM_CTL                    (WSA881X_ANALOG_BASE + 0x0021)
 149 #define WSA881X_SPKR_MISC_CTL1                  (WSA881X_ANALOG_BASE + 0x0022)
 150 #define WSA881X_SPKR_MISC_CTL2                  (WSA881X_ANALOG_BASE + 0x0023)
 151 #define WSA881X_SPKR_BIAS_INT                   (WSA881X_ANALOG_BASE + 0x0024)
 152 #define WSA881X_SPKR_PA_INT                     (WSA881X_ANALOG_BASE + 0x0025)
 153 #define WSA881X_SPKR_BIAS_CAL                   (WSA881X_ANALOG_BASE + 0x0026)
 154 #define WSA881X_SPKR_BIAS_PSRR                  (WSA881X_ANALOG_BASE + 0x0027)
 155 #define WSA881X_SPKR_STATUS1                    (WSA881X_ANALOG_BASE + 0x0028)
 156 #define WSA881X_SPKR_STATUS2                    (WSA881X_ANALOG_BASE + 0x0029)
 157 #define WSA881X_BOOST_EN_CTL                    (WSA881X_ANALOG_BASE + 0x002A)
 158 #define WSA881X_BOOST_EN_MASK                   BIT(7)
 159 #define WSA881X_BOOST_EN                        BIT(7)
 160 #define WSA881X_BOOST_CURRENT_LIMIT             (WSA881X_ANALOG_BASE + 0x002B)
 161 #define WSA881X_BOOST_PS_CTL                    (WSA881X_ANALOG_BASE + 0x002C)
 162 #define WSA881X_BOOST_PRESET_OUT1               (WSA881X_ANALOG_BASE + 0x002D)
 163 #define WSA881X_BOOST_PRESET_OUT2               (WSA881X_ANALOG_BASE + 0x002E)
 164 #define WSA881X_BOOST_FORCE_OUT                 (WSA881X_ANALOG_BASE + 0x002F)
 165 #define WSA881X_BOOST_LDO_PROG                  (WSA881X_ANALOG_BASE + 0x0030)
 166 #define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB      (WSA881X_ANALOG_BASE + 0x0031)
 167 #define WSA881X_BOOST_RON_CTL                   (WSA881X_ANALOG_BASE + 0x0032)
 168 #define WSA881X_BOOST_LOOP_STABILITY            (WSA881X_ANALOG_BASE + 0x0033)
 169 #define WSA881X_BOOST_ZX_CTL                    (WSA881X_ANALOG_BASE + 0x0034)
 170 #define WSA881X_BOOST_START_CTL                 (WSA881X_ANALOG_BASE + 0x0035)
 171 #define WSA881X_BOOST_MISC1_CTL                 (WSA881X_ANALOG_BASE + 0x0036)
 172 #define WSA881X_BOOST_MISC2_CTL                 (WSA881X_ANALOG_BASE + 0x0037)
 173 #define WSA881X_BOOST_MISC3_CTL                 (WSA881X_ANALOG_BASE + 0x0038)
 174 #define WSA881X_BOOST_ATEST_CTL                 (WSA881X_ANALOG_BASE + 0x0039)
 175 #define WSA881X_SPKR_PROT_FE_GAIN               (WSA881X_ANALOG_BASE + 0x003A)
 176 #define WSA881X_SPKR_PROT_FE_CM_LDO_SET         (WSA881X_ANALOG_BASE + 0x003B)
 177 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1   (WSA881X_ANALOG_BASE + 0x003C)
 178 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2   (WSA881X_ANALOG_BASE + 0x003D)
 179 #define WSA881X_SPKR_PROT_ATEST1                (WSA881X_ANALOG_BASE + 0x003E)
 180 #define WSA881X_SPKR_PROT_ATEST2                (WSA881X_ANALOG_BASE + 0x003F)
 181 #define WSA881X_SPKR_PROT_FE_VSENSE_VCM         (WSA881X_ANALOG_BASE + 0x0040)
 182 #define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1   (WSA881X_ANALOG_BASE + 0x0041)
 183 #define WSA881X_BONGO_RESRV_REG1                (WSA881X_ANALOG_BASE + 0x0042)
 184 #define WSA881X_BONGO_RESRV_REG2                (WSA881X_ANALOG_BASE + 0x0043)
 185 #define WSA881X_SPKR_PROT_SAR                   (WSA881X_ANALOG_BASE + 0x0044)
 186 #define WSA881X_SPKR_STATUS3                    (WSA881X_ANALOG_BASE + 0x0045)
 187
 188 #define SWRS_SCP_FRAME_CTRL_BANK(m)             (0x60 + 0x10 * (m))
 189 #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m)      (0xE0 + 0x10 * (m))
 190 #define SWR_SLV_MAX_REG_ADDR    0x390
 191 #define SWR_SLV_START_REG_ADDR  0x40
 192 #define SWR_SLV_MAX_BUF_LEN     20
 193 #define BYTES_PER_LINE          12
 194 #define SWR_SLV_RD_BUF_LEN      8
 195 #define SWR_SLV_WR_BUF_LEN      32
 196 #define SWR_SLV_MAX_DEVICES     2
 197 #define WSA881X_MAX_SWR_PORTS   4
 198 #define WSA881X_VERSION_ENTRY_SIZE 27
 199 #define WSA881X_OCP_CTL_TIMER_SEC 2
 200 #define WSA881X_OCP_CTL_TEMP_CELSIUS 25
 201 #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60
 202 #define WSA881X_PROBE_TIMEOUT 1000
 203
 204 #define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
 205 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 206         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 207                  SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 208         .tlv.p = (tlv_array), \
 209         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 210         .put = wsa881x_put_pa_gain, \
 211         .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
 212
 213 static struct reg_default wsa881x_defaults[] = {
 214         { WSA881X_CHIP_ID0, 0x00 },
 215         { WSA881X_CHIP_ID1, 0x00 },
 216         { WSA881X_CHIP_ID2, 0x00 },
 217         { WSA881X_CHIP_ID3, 0x02 },
 218         { WSA881X_BUS_ID, 0x00 },
 219         { WSA881X_CDC_RST_CTL, 0x00 },
 220         { WSA881X_CDC_TOP_CLK_CTL, 0x03 },
 221         { WSA881X_CDC_ANA_CLK_CTL, 0x00 },
 222         { WSA881X_CDC_DIG_CLK_CTL, 0x00 },
 223         { WSA881X_CLOCK_CONFIG, 0x00 },
 224         { WSA881X_ANA_CTL, 0x08 },
 225         { WSA881X_SWR_RESET_EN, 0x00 },
 226         { WSA881X_TEMP_DETECT_CTL, 0x01 },
 227         { WSA881X_TEMP_MSB, 0x00 },
 228         { WSA881X_TEMP_LSB, 0x00 },
 229         { WSA881X_TEMP_CONFIG0, 0x00 },
 230         { WSA881X_TEMP_CONFIG1, 0x00 },
 231         { WSA881X_CDC_CLIP_CTL, 0x03 },
 232         { WSA881X_SDM_PDM9_LSB, 0x00 },
 233         { WSA881X_SDM_PDM9_MSB, 0x00 },
 234         { WSA881X_CDC_RX_CTL, 0x7E },
 235         { WSA881X_DEM_BYPASS_DATA0, 0x00 },
 236         { WSA881X_DEM_BYPASS_DATA1, 0x00 },
 237         { WSA881X_DEM_BYPASS_DATA2, 0x00 },
 238         { WSA881X_DEM_BYPASS_DATA3, 0x00 },
 239         { WSA881X_OTP_CTRL0, 0x00 },
 240         { WSA881X_OTP_CTRL1, 0x00 },
 241         { WSA881X_HDRIVE_CTL_GROUP1, 0x00 },
 242         { WSA881X_INTR_MODE, 0x00 },
 243         { WSA881X_INTR_STATUS, 0x00 },
 244         { WSA881X_INTR_CLEAR, 0x00 },
 245         { WSA881X_INTR_LEVEL, 0x00 },
 246         { WSA881X_INTR_SET, 0x00 },
 247         { WSA881X_INTR_TEST, 0x00 },
 248         { WSA881X_PDM_TEST_MODE, 0x00 },
 249         { WSA881X_ATE_TEST_MODE, 0x00 },
 250         { WSA881X_PIN_CTL_MODE, 0x00 },
 251         { WSA881X_PIN_CTL_OE, 0x00 },
 252         { WSA881X_PIN_WDATA_IOPAD, 0x00 },
 253         { WSA881X_PIN_STATUS, 0x00 },
 254         { WSA881X_DIG_DEBUG_MODE, 0x00 },
 255         { WSA881X_DIG_DEBUG_SEL, 0x00 },
 256         { WSA881X_DIG_DEBUG_EN, 0x00 },
 257         { WSA881X_SWR_HM_TEST1, 0x08 },
 258         { WSA881X_SWR_HM_TEST2, 0x00 },
 259         { WSA881X_TEMP_DETECT_DBG_CTL, 0x00 },
 260         { WSA881X_TEMP_DEBUG_MSB, 0x00 },
 261         { WSA881X_TEMP_DEBUG_LSB, 0x00 },
 262         { WSA881X_SAMPLE_EDGE_SEL, 0x0C },
 263         { WSA881X_SPARE_0, 0x00 },
 264         { WSA881X_SPARE_1, 0x00 },
 265         { WSA881X_SPARE_2, 0x00 },
 266         { WSA881X_OTP_REG_0, 0x01 },
 267         { WSA881X_OTP_REG_1, 0xFF },
 268         { WSA881X_OTP_REG_2, 0xC0 },
 269         { WSA881X_OTP_REG_3, 0xFF },
 270         { WSA881X_OTP_REG_4, 0xC0 },
 271         { WSA881X_OTP_REG_5, 0xFF },
 272         { WSA881X_OTP_REG_6, 0xFF },
 273         { WSA881X_OTP_REG_7, 0xFF },
 274         { WSA881X_OTP_REG_8, 0xFF },
 275         { WSA881X_OTP_REG_9, 0xFF },
 276         { WSA881X_OTP_REG_10, 0xFF },
 277         { WSA881X_OTP_REG_11, 0xFF },
 278         { WSA881X_OTP_REG_12, 0xFF },
 279         { WSA881X_OTP_REG_13, 0xFF },
 280         { WSA881X_OTP_REG_14, 0xFF },
 281         { WSA881X_OTP_REG_15, 0xFF },
 282         { WSA881X_OTP_REG_16, 0xFF },
 283         { WSA881X_OTP_REG_17, 0xFF },
 284         { WSA881X_OTP_REG_18, 0xFF },
 285         { WSA881X_OTP_REG_19, 0xFF },
 286         { WSA881X_OTP_REG_20, 0xFF },
 287         { WSA881X_OTP_REG_21, 0xFF },
 288         { WSA881X_OTP_REG_22, 0xFF },
 289         { WSA881X_OTP_REG_23, 0xFF },
 290         { WSA881X_OTP_REG_24, 0x03 },
 291         { WSA881X_OTP_REG_25, 0x01 },
 292         { WSA881X_OTP_REG_26, 0x03 },
 293         { WSA881X_OTP_REG_27, 0x11 },
 294         { WSA881X_OTP_REG_63, 0x40 },
 295         /* WSA881x Analog registers */
 296         { WSA881X_BIAS_REF_CTRL, 0x6C },
 297         { WSA881X_BIAS_TEST, 0x16 },
 298         { WSA881X_BIAS_BIAS, 0xF0 },
 299         { WSA881X_TEMP_OP, 0x00 },
 300         { WSA881X_TEMP_IREF_CTRL, 0x56 },
 301         { WSA881X_TEMP_ISENS_CTRL, 0x47 },
 302         { WSA881X_TEMP_CLK_CTRL, 0x87 },
 303         { WSA881X_TEMP_TEST, 0x00 },
 304         { WSA881X_TEMP_BIAS, 0x51 },
 305         { WSA881X_TEMP_DOUT_MSB, 0x00 },
 306         { WSA881X_TEMP_DOUT_LSB, 0x00 },
 307         { WSA881X_ADC_EN_MODU_V, 0x00 },
 308         { WSA881X_ADC_EN_MODU_I, 0x00 },
 309         { WSA881X_ADC_EN_DET_TEST_V, 0x00 },
 310         { WSA881X_ADC_EN_DET_TEST_I, 0x00 },
 311         { WSA881X_ADC_EN_SEL_IBAIS, 0x10 },
 312         { WSA881X_SPKR_DRV_EN, 0x74 },
 313         { WSA881X_SPKR_DRV_DBG, 0x15 },
 314         { WSA881X_SPKR_PWRSTG_DBG, 0x00 },
 315         { WSA881X_SPKR_OCP_CTL, 0xD4 },
 316         { WSA881X_SPKR_CLIP_CTL, 0x90 },
 317         { WSA881X_SPKR_PA_INT, 0x54 },
 318         { WSA881X_SPKR_BIAS_CAL, 0xAC },
 319         { WSA881X_SPKR_STATUS1, 0x00 },
 320         { WSA881X_SPKR_STATUS2, 0x00 },
 321         { WSA881X_BOOST_EN_CTL, 0x18 },
 322         { WSA881X_BOOST_CURRENT_LIMIT, 0x7A },
 323         { WSA881X_BOOST_PRESET_OUT2, 0x70 },
 324         { WSA881X_BOOST_FORCE_OUT, 0x0E },
 325         { WSA881X_BOOST_LDO_PROG, 0x16 },
 326         { WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 },
 327         { WSA881X_BOOST_RON_CTL, 0x0F },
 328         { WSA881X_BOOST_ZX_CTL, 0x34 },
 329         { WSA881X_BOOST_START_CTL, 0x23 },
 330         { WSA881X_BOOST_MISC1_CTL, 0x80 },
 331         { WSA881X_BOOST_MISC2_CTL, 0x00 },
 332         { WSA881X_BOOST_MISC3_CTL, 0x00 },
 333         { WSA881X_BOOST_ATEST_CTL, 0x00 },
 334         { WSA881X_SPKR_PROT_FE_GAIN, 0x46 },
 335         { WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B },
 336         { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D },
 337         { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D },
 338         { WSA881X_SPKR_PROT_ATEST1, 0x01 },
 339         { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D },
 340         { WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D },
 341         { WSA881X_SPKR_PROT_SAR, 0x00 },
 342         { WSA881X_SPKR_STATUS3, 0x00 },
 343 };
 344
 345 static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = {
 346         { WSA881X_SPKR_DRV_GAIN, 0x41, 0 },
 347         { WSA881X_SPKR_MISC_CTL1, 0x87, 0 },
 348 };
 349
 350 static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = {
 351         { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 },
 352         { WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 },
 353         { WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 },
 354 };
 355
 356 /* Default register reset values for WSA881x rev 2.0 */
 357 static struct reg_sequence wsa881x_rev_2_0[] = {
 358         { WSA881X_RESET_CTL, 0x00, 0x00 },
 359         { WSA881X_TADC_VALUE_CTL, 0x01, 0x00 },
 360         { WSA881X_INTR_MASK, 0x1B, 0x00 },
 361         { WSA881X_IOPAD_CTL, 0x00, 0x00 },
 362         { WSA881X_OTP_REG_28, 0x3F, 0x00 },
 363         { WSA881X_OTP_REG_29, 0x3F, 0x00 },
 364         { WSA881X_OTP_REG_30, 0x01, 0x00 },
 365         { WSA881X_OTP_REG_31, 0x01, 0x00 },
 366         { WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 },
 367         { WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 },
 368         { WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 },
 369         { WSA881X_SPKR_DAC_CTL, 0x42, 0x00 },
 370         { WSA881X_SPKR_BBM_CTL, 0x02, 0x00 },
 371         { WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 },
 372         { WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 },
 373         { WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 },
 374         { WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 },
 375         { WSA881X_BOOST_PS_CTL, 0xA0, 0x00 },
 376         { WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 },
 377         { WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 },
 378         { WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 },
 379         { WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 },
 380         { WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 },
 381 };
 382
 383 enum wsa_port_ids {
 384         WSA881X_PORT_DAC,
 385         WSA881X_PORT_COMP,
 386         WSA881X_PORT_BOOST,
 387         WSA881X_PORT_VISENSE,
 388 };
 389
 390 /* 4 ports */
 391 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = {
 392         {
 393                 /* DAC */
 394                 .num = 1,
 395                 .type = SDW_DPN_SIMPLE,
 396                 .min_ch = 1,
 397                 .max_ch = 1,
 398                 .simple_ch_prep_sm = true,
 399                 .read_only_wordlength = true,
 400         }, {
 401                 /* COMP */
 402                 .num = 2,
 403                 .type = SDW_DPN_SIMPLE,
 404                 .min_ch = 1,
 405                 .max_ch = 1,
 406                 .simple_ch_prep_sm = true,
 407                 .read_only_wordlength = true,
 408         }, {
 409                 /* BOOST */
 410                 .num = 3,
 411                 .type = SDW_DPN_SIMPLE,
 412                 .min_ch = 1,
 413                 .max_ch = 1,
 414                 .simple_ch_prep_sm = true,
 415                 .read_only_wordlength = true,
 416         }, {
 417                 /* VISENSE */
 418                 .num = 4,
 419                 .type = SDW_DPN_SIMPLE,
 420                 .min_ch = 1,
 421                 .max_ch = 1,
 422                 .simple_ch_prep_sm = true,
 423                 .read_only_wordlength = true,
 424         }
 425 };
 426
 427 static struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = {
 428         {
 429                 .num = 1,
 430                 .ch_mask = 0x1,
 431         }, {
 432                 .num = 2,
 433                 .ch_mask = 0xf,
 434         }, {
 435                 .num = 3,
 436                 .ch_mask = 0x3,
 437         }, {    /* IV feedback */
 438                 .num = 4,
 439                 .ch_mask = 0x3,
 440         },
 441 };
 442
 443 static bool wsa881x_readable_register(struct device *dev, unsigned int reg)
 444 {
 445         switch (reg) {
 446         case WSA881X_CHIP_ID0:
 447         case WSA881X_CHIP_ID1:
 448         case WSA881X_CHIP_ID2:
 449         case WSA881X_CHIP_ID3:
 450         case WSA881X_BUS_ID:
 451         case WSA881X_CDC_RST_CTL:
 452         case WSA881X_CDC_TOP_CLK_CTL:
 453         case WSA881X_CDC_ANA_CLK_CTL:
 454         case WSA881X_CDC_DIG_CLK_CTL:
 455         case WSA881X_CLOCK_CONFIG:
 456         case WSA881X_ANA_CTL:
 457         case WSA881X_SWR_RESET_EN:
 458         case WSA881X_RESET_CTL:
 459         case WSA881X_TADC_VALUE_CTL:
 460         case WSA881X_TEMP_DETECT_CTL:
 461         case WSA881X_TEMP_MSB:
 462         case WSA881X_TEMP_LSB:
 463         case WSA881X_TEMP_CONFIG0:
 464         case WSA881X_TEMP_CONFIG1:
 465         case WSA881X_CDC_CLIP_CTL:
 466         case WSA881X_SDM_PDM9_LSB:
 467         case WSA881X_SDM_PDM9_MSB:
 468         case WSA881X_CDC_RX_CTL:
 469         case WSA881X_DEM_BYPASS_DATA0:
 470         case WSA881X_DEM_BYPASS_DATA1:
 471         case WSA881X_DEM_BYPASS_DATA2:
 472         case WSA881X_DEM_BYPASS_DATA3:
 473         case WSA881X_OTP_CTRL0:
 474         case WSA881X_OTP_CTRL1:
 475         case WSA881X_HDRIVE_CTL_GROUP1:
 476         case WSA881X_INTR_MODE:
 477         case WSA881X_INTR_MASK:
 478         case WSA881X_INTR_STATUS:
 479         case WSA881X_INTR_CLEAR:
 480         case WSA881X_INTR_LEVEL:
 481         case WSA881X_INTR_SET:
 482         case WSA881X_INTR_TEST:
 483         case WSA881X_PDM_TEST_MODE:
 484         case WSA881X_ATE_TEST_MODE:
 485         case WSA881X_PIN_CTL_MODE:
 486         case WSA881X_PIN_CTL_OE:
 487         case WSA881X_PIN_WDATA_IOPAD:
 488         case WSA881X_PIN_STATUS:
 489         case WSA881X_DIG_DEBUG_MODE:
 490         case WSA881X_DIG_DEBUG_SEL:
 491         case WSA881X_DIG_DEBUG_EN:
 492         case WSA881X_SWR_HM_TEST1:
 493         case WSA881X_SWR_HM_TEST2:
 494         case WSA881X_TEMP_DETECT_DBG_CTL:
 495         case WSA881X_TEMP_DEBUG_MSB:
 496         case WSA881X_TEMP_DEBUG_LSB:
 497         case WSA881X_SAMPLE_EDGE_SEL:
 498         case WSA881X_IOPAD_CTL:
 499         case WSA881X_SPARE_0:
 500         case WSA881X_SPARE_1:
 501         case WSA881X_SPARE_2:
 502         case WSA881X_OTP_REG_0:
 503         case WSA881X_OTP_REG_1:
 504         case WSA881X_OTP_REG_2:
 505         case WSA881X_OTP_REG_3:
 506         case WSA881X_OTP_REG_4:
 507         case WSA881X_OTP_REG_5:
 508         case WSA881X_OTP_REG_6:
 509         case WSA881X_OTP_REG_7:
 510         case WSA881X_OTP_REG_8:
 511         case WSA881X_OTP_REG_9:
 512         case WSA881X_OTP_REG_10:
 513         case WSA881X_OTP_REG_11:
 514         case WSA881X_OTP_REG_12:
 515         case WSA881X_OTP_REG_13:
 516         case WSA881X_OTP_REG_14:
 517         case WSA881X_OTP_REG_15:
 518         case WSA881X_OTP_REG_16:
 519         case WSA881X_OTP_REG_17:
 520         case WSA881X_OTP_REG_18:
 521         case WSA881X_OTP_REG_19:
 522         case WSA881X_OTP_REG_20:
 523         case WSA881X_OTP_REG_21:
 524         case WSA881X_OTP_REG_22:
 525         case WSA881X_OTP_REG_23:
 526         case WSA881X_OTP_REG_24:
 527         case WSA881X_OTP_REG_25:
 528         case WSA881X_OTP_REG_26:
 529         case WSA881X_OTP_REG_27:
 530         case WSA881X_OTP_REG_28:
 531         case WSA881X_OTP_REG_29:
 532         case WSA881X_OTP_REG_30:
 533         case WSA881X_OTP_REG_31:
 534         case WSA881X_OTP_REG_63:
 535         case WSA881X_BIAS_REF_CTRL:
 536         case WSA881X_BIAS_TEST:
 537         case WSA881X_BIAS_BIAS:
 538         case WSA881X_TEMP_OP:
 539         case WSA881X_TEMP_IREF_CTRL:
 540         case WSA881X_TEMP_ISENS_CTRL:
 541         case WSA881X_TEMP_CLK_CTRL:
 542         case WSA881X_TEMP_TEST:
 543         case WSA881X_TEMP_BIAS:
 544         case WSA881X_TEMP_ADC_CTRL:
 545         case WSA881X_TEMP_DOUT_MSB:
 546         case WSA881X_TEMP_DOUT_LSB:
 547         case WSA881X_ADC_EN_MODU_V:
 548         case WSA881X_ADC_EN_MODU_I:
 549         case WSA881X_ADC_EN_DET_TEST_V:
 550         case WSA881X_ADC_EN_DET_TEST_I:
 551         case WSA881X_ADC_SEL_IBIAS:
 552         case WSA881X_ADC_EN_SEL_IBAIS:
 553         case WSA881X_SPKR_DRV_EN:
 554         case WSA881X_SPKR_DRV_GAIN:
 555         case WSA881X_SPKR_DAC_CTL:
 556         case WSA881X_SPKR_DRV_DBG:
 557         case WSA881X_SPKR_PWRSTG_DBG:
 558         case WSA881X_SPKR_OCP_CTL:
 559         case WSA881X_SPKR_CLIP_CTL:
 560         case WSA881X_SPKR_BBM_CTL:
 561         case WSA881X_SPKR_MISC_CTL1:
 562         case WSA881X_SPKR_MISC_CTL2:
 563         case WSA881X_SPKR_BIAS_INT:
 564         case WSA881X_SPKR_PA_INT:
 565         case WSA881X_SPKR_BIAS_CAL:
 566         case WSA881X_SPKR_BIAS_PSRR:
 567         case WSA881X_SPKR_STATUS1:
 568         case WSA881X_SPKR_STATUS2:
 569         case WSA881X_BOOST_EN_CTL:
 570         case WSA881X_BOOST_CURRENT_LIMIT:
 571         case WSA881X_BOOST_PS_CTL:
 572         case WSA881X_BOOST_PRESET_OUT1:
 573         case WSA881X_BOOST_PRESET_OUT2:
 574         case WSA881X_BOOST_FORCE_OUT:
 575         case WSA881X_BOOST_LDO_PROG:
 576         case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB:
 577         case WSA881X_BOOST_RON_CTL:
 578         case WSA881X_BOOST_LOOP_STABILITY:
 579         case WSA881X_BOOST_ZX_CTL:
 580         case WSA881X_BOOST_START_CTL:
 581         case WSA881X_BOOST_MISC1_CTL:
 582         case WSA881X_BOOST_MISC2_CTL:
 583         case WSA881X_BOOST_MISC3_CTL:
 584         case WSA881X_BOOST_ATEST_CTL:
 585         case WSA881X_SPKR_PROT_FE_GAIN:
 586         case WSA881X_SPKR_PROT_FE_CM_LDO_SET:
 587         case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1:
 588         case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2:
 589         case WSA881X_SPKR_PROT_ATEST1:
 590         case WSA881X_SPKR_PROT_ATEST2:
 591         case WSA881X_SPKR_PROT_FE_VSENSE_VCM:
 592         case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1:
 593         case WSA881X_BONGO_RESRV_REG1:
 594         case WSA881X_BONGO_RESRV_REG2:
 595         case WSA881X_SPKR_PROT_SAR:
 596         case WSA881X_SPKR_STATUS3:
 597                 return true;
 598         default:
 599                 return false;
 600         }
 601 }
 602
 603 static bool wsa881x_volatile_register(struct device *dev, unsigned int reg)
 604 {
 605         switch (reg) {
 606         case WSA881X_CHIP_ID0:
 607         case WSA881X_CHIP_ID1:
 608         case WSA881X_CHIP_ID2:
 609         case WSA881X_CHIP_ID3:
 610         case WSA881X_BUS_ID:
 611         case WSA881X_TEMP_MSB:
 612         case WSA881X_TEMP_LSB:
 613         case WSA881X_SDM_PDM9_LSB:
 614         case WSA881X_SDM_PDM9_MSB:
 615         case WSA881X_OTP_CTRL1:
 616         case WSA881X_INTR_STATUS:
 617         case WSA881X_ATE_TEST_MODE:
 618         case WSA881X_PIN_STATUS:
 619         case WSA881X_SWR_HM_TEST2:
 620         case WSA881X_SPKR_STATUS1:
 621         case WSA881X_SPKR_STATUS2:
 622         case WSA881X_SPKR_STATUS3:
 623         case WSA881X_OTP_REG_0:
 624         case WSA881X_OTP_REG_1:
 625         case WSA881X_OTP_REG_2:
 626         case WSA881X_OTP_REG_3:
 627         case WSA881X_OTP_REG_4:
 628         case WSA881X_OTP_REG_5:
 629         case WSA881X_OTP_REG_31:
 630         case WSA881X_TEMP_DOUT_MSB:
 631         case WSA881X_TEMP_DOUT_LSB:
 632         case WSA881X_TEMP_OP:
 633         case WSA881X_SPKR_PROT_SAR:
 634                 return true;
 635         default:
 636                 return false;
 637         }
 638 }
 639
 640 static struct regmap_config wsa881x_regmap_config = {
 641         .reg_bits = 32,
 642         .val_bits = 8,
 643         .cache_type = REGCACHE_RBTREE,
 644         .reg_defaults = wsa881x_defaults,
 645         .max_register = WSA881X_SPKR_STATUS3,
 646         .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults),
 647         .volatile_reg = wsa881x_volatile_register,
 648         .readable_reg = wsa881x_readable_register,
 649         .reg_format_endian = REGMAP_ENDIAN_NATIVE,
 650         .val_format_endian = REGMAP_ENDIAN_NATIVE,
 651 };
 652
 653 enum {
 654         G_18DB = 0,
 655         G_16P5DB,
 656         G_15DB,
 657         G_13P5DB,
 658         G_12DB,
 659         G_10P5DB,
 660         G_9DB,
 661         G_7P5DB,
 662         G_6DB,
 663         G_4P5DB,
 664         G_3DB,
 665         G_1P5DB,
 666         G_0DB,
 667 };
 668
 669 /*
 670  * Private data Structure for wsa881x. All parameters related to
 671  * WSA881X codec needs to be defined here.
 672  */
 673 struct wsa881x_priv {
 674         struct regmap *regmap;
 675         struct device *dev;
 676         struct sdw_slave *slave;
 677         struct sdw_stream_config sconfig;
 678         struct sdw_stream_runtime *sruntime;
 679         struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS];
 680         struct gpio_desc *sd_n;
 681         int version;
 682         int active_ports;
 683         bool port_prepared[WSA881X_MAX_SWR_PORTS];
 684         bool port_enable[WSA881X_MAX_SWR_PORTS];
 685 };
 686
 687 static void wsa881x_init(struct wsa881x_priv *wsa881x)
 688 {
 689         struct regmap *rm = wsa881x->regmap;
 690         unsigned int val = 0;
 691
 692         regmap_read(rm, WSA881X_CHIP_ID1, &wsa881x->version);
 693         regmap_register_patch(wsa881x->regmap, wsa881x_rev_2_0,
 694                               ARRAY_SIZE(wsa881x_rev_2_0));
 695
 696         /* Enable software reset output from soundwire slave */
 697         regmap_update_bits(rm, WSA881X_SWR_RESET_EN, 0x07, 0x07);
 698
 699         /* Bring out of analog reset */
 700         regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x02, 0x02);
 701
 702         /* Bring out of digital reset */
 703         regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x01, 0x01);
 704         regmap_update_bits(rm, WSA881X_CLOCK_CONFIG, 0x10, 0x10);
 705         regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x02, 0x02);
 706         regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80);
 707         regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06);
 708         regmap_update_bits(rm, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00);
 709         regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0xF0, 0x40);
 710         regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0x0E, 0x0E);
 711         regmap_update_bits(rm, WSA881X_BOOST_LOOP_STABILITY, 0x03, 0x03);
 712         regmap_update_bits(rm, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14);
 713         regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x80, 0x80);
 714         regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x03, 0x00);
 715         regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x0C, 0x04);
 716         regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x03, 0x00);
 717
 718         regmap_read(rm, WSA881X_OTP_REG_0, &val);
 719         if (val)
 720                 regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT1, 0xF0, 0x70);
 721
 722         regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT2, 0xF0, 0x30);
 723         regmap_update_bits(rm, WSA881X_SPKR_DRV_EN, 0x08, 0x08);
 724         regmap_update_bits(rm, WSA881X_BOOST_CURRENT_LIMIT, 0x0F, 0x08);
 725         regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x30, 0x30);
 726         regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00);
 727         regmap_update_bits(rm, WSA881X_OTP_REG_28, 0x3F, 0x3A);
 728         regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG1, 0xFF, 0xB2);
 729         regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG2, 0xFF, 0x05);
 730 }
 731
 732 static int wsa881x_component_probe(struct snd_soc_component *comp)
 733 {
 734         struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
 735
 736         snd_soc_component_init_regmap(comp, wsa881x->regmap);
 737
 738         return 0;
 739 }
 740
 741 static int wsa881x_put_pa_gain(struct snd_kcontrol *kc,
 742                                struct snd_ctl_elem_value *ucontrol)
 743 {
 744         struct snd_soc_component *comp = snd_soc_kcontrol_component(kc);
 745         struct soc_mixer_control *mc =
 746                         (struct soc_mixer_control *)kc->private_value;
 747         int max = mc->max;
 748         unsigned int mask = (1 << fls(max)) - 1;
 749         int val, ret, min_gain, max_gain;
 750
 751         ret = pm_runtime_resume_and_get(comp->dev);
 752         if (ret < 0 && ret != -EACCES)
 753                 return ret;
 754
 755         max_gain = (max - ucontrol->value.integer.value[0]) & mask;
 756         /*
 757          * Gain has to set incrementally in 4 steps
 758          * as per HW sequence
 759          */
 760         if (max_gain > G_4P5DB)
 761                 min_gain = G_0DB;
 762         else
 763                 min_gain = max_gain + 3;
 764         /*
 765          * 1ms delay is needed before change in gain
 766          * as per HW requirement.
 767          */
 768         usleep_range(1000, 1010);
 769
 770         for (val = min_gain; max_gain <= val; val--) {
 771                 ret = snd_soc_component_update_bits(comp,
 772                               WSA881X_SPKR_DRV_GAIN,
 773                               WSA881X_SPKR_PAG_GAIN_MASK,
 774                               val << 4);
 775                 if (ret < 0)
 776                         dev_err(comp->dev, "Failed to change PA gain");
 777
 778                 usleep_range(1000, 1010);
 779         }
 780
 781         pm_runtime_mark_last_busy(comp->dev);
 782         pm_runtime_put_autosuspend(comp->dev);
 783
 784         return 1;
 785 }
 786
 787 static int wsa881x_get_port(struct snd_kcontrol *kcontrol,
 788                             struct snd_ctl_elem_value *ucontrol)
 789 {
 790         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
 791         struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
 792         struct soc_mixer_control *mixer =
 793                 (struct soc_mixer_control *)kcontrol->private_value;
 794         int portidx = mixer->reg;
 795
 796         ucontrol->value.integer.value[0] = data->port_enable[portidx];
 797
 798
 799         return 0;
 800 }
 801
 802 static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable)
 803 {
 804         if (enable)
 805                 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
 806                                               WSA881X_BOOST_EN_MASK,
 807                                               WSA881X_BOOST_EN);
 808         else
 809                 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
 810                                               WSA881X_BOOST_EN_MASK, 0);
 811         /*
 812          * 1.5ms sleep is needed after boost enable/disable as per
 813          * HW requirement
 814          */
 815         usleep_range(1500, 1510);
 816         return 0;
 817 }
 818
 819 static int wsa881x_set_port(struct snd_kcontrol *kcontrol,
 820                             struct snd_ctl_elem_value *ucontrol)
 821 {
 822         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
 823         struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
 824         struct soc_mixer_control *mixer =
 825                 (struct soc_mixer_control *)kcontrol->private_value;
 826         int portidx = mixer->reg;
 827
 828         if (ucontrol->value.integer.value[0]) {
 829                 if (data->port_enable[portidx])
 830                         return 0;
 831
 832                 data->port_enable[portidx] = true;
 833         } else {
 834                 if (!data->port_enable[portidx])
 835                         return 0;
 836
 837                 data->port_enable[portidx] = false;
 838         }
 839
 840         if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */
 841                 wsa881x_boost_ctrl(comp, data->port_enable[portidx]);
 842
 843         return 1;
 844 }
 845
 846 static const char * const smart_boost_lvl_text[] = {
 847         "6.625 V", "6.750 V", "6.875 V", "7.000 V",
 848         "7.125 V", "7.250 V", "7.375 V", "7.500 V",
 849         "7.625 V", "7.750 V", "7.875 V", "8.000 V",
 850         "8.125 V", "8.250 V", "8.375 V", "8.500 V"
 851 };
 852
 853 static const struct soc_enum smart_boost_lvl_enum =
 854         SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0,
 855                         ARRAY_SIZE(smart_boost_lvl_text),
 856                         smart_boost_lvl_text);
 857
 858 static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0);
 859
 860 static const struct snd_kcontrol_new wsa881x_snd_controls[] = {
 861         SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum),
 862         WSA881X_PA_GAIN_TLV("PA Volume", WSA881X_SPKR_DRV_GAIN,
 863                             4, 0xC, 1, pa_gain),
 864         SOC_SINGLE_EXT("DAC Switch", WSA881X_PORT_DAC, 0, 1, 0,
 865                        wsa881x_get_port, wsa881x_set_port),
 866         SOC_SINGLE_EXT("COMP Switch", WSA881X_PORT_COMP, 0, 1, 0,
 867                        wsa881x_get_port, wsa881x_set_port),
 868         SOC_SINGLE_EXT("BOOST Switch", WSA881X_PORT_BOOST, 0, 1, 0,
 869                        wsa881x_get_port, wsa881x_set_port),
 870         SOC_SINGLE_EXT("VISENSE Switch", WSA881X_PORT_VISENSE, 0, 1, 0,
 871                        wsa881x_get_port, wsa881x_set_port),
 872 };
 873
 874 static const struct snd_soc_dapm_route wsa881x_audio_map[] = {
 875         { "RDAC", NULL, "IN" },
 876         { "RDAC", NULL, "DCLK" },
 877         { "RDAC", NULL, "ACLK" },
 878         { "RDAC", NULL, "Bandgap" },
 879         { "SPKR PGA", NULL, "RDAC" },
 880         { "SPKR", NULL, "SPKR PGA" },
 881 };
 882
 883 static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp,
 884                                      bool enable)
 885 {
 886         struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
 887
 888         if (enable) {
 889                 regmap_multi_reg_write(wsa881x->regmap, wsa881x_vi_txfe_en_2_0,
 890                                        ARRAY_SIZE(wsa881x_vi_txfe_en_2_0));
 891         } else {
 892                 snd_soc_component_update_bits(comp,
 893                                               WSA881X_SPKR_PROT_FE_VSENSE_VCM,
 894                                               0x08, 0x08);
 895                 /*
 896                  * 200us sleep is needed after visense txfe disable as per
 897                  * HW requirement.
 898                  */
 899                 usleep_range(200, 210);
 900                 snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN,
 901                                               0x01, 0x00);
 902         }
 903         return 0;
 904 }
 905
 906 static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp,
 907                                     bool enable)
 908 {
 909         snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, BIT(7),
 910                                       (enable << 7));
 911         snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, BIT(7),
 912                                       (enable << 7));
 913         return 0;
 914 }
 915
 916 static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w,
 917                                  struct snd_kcontrol *kcontrol, int event)
 918 {
 919         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
 920         struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
 921
 922         switch (event) {
 923         case SND_SOC_DAPM_PRE_PMU:
 924                 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
 925                                               WSA881X_SPKR_OCP_MASK,
 926                                               WSA881X_SPKR_OCP_EN);
 927                 regmap_multi_reg_write(wsa881x->regmap, wsa881x_pre_pmu_pa_2_0,
 928                                        ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0));
 929
 930                 snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN,
 931                                               WSA881X_PA_GAIN_SEL_MASK,
 932                                               WSA881X_PA_GAIN_SEL_REG);
 933                 break;
 934         case SND_SOC_DAPM_POST_PMU:
 935                 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
 936                         wsa881x_visense_txfe_ctrl(comp, true);
 937                         snd_soc_component_update_bits(comp,
 938                                                       WSA881X_ADC_EN_SEL_IBAIS,
 939                                                       0x07, 0x01);
 940                         wsa881x_visense_adc_ctrl(comp, true);
 941                 }
 942
 943                 break;
 944         case SND_SOC_DAPM_POST_PMD:
 945                 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
 946                         wsa881x_visense_adc_ctrl(comp, false);
 947                         wsa881x_visense_txfe_ctrl(comp, false);
 948                 }
 949
 950                 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
 951                                               WSA881X_SPKR_OCP_MASK,
 952                                               WSA881X_SPKR_OCP_EN |
 953                                               WSA881X_SPKR_OCP_HOLD);
 954                 break;
 955         }
 956         return 0;
 957 }
 958
 959 static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = {
 960         SND_SOC_DAPM_INPUT("IN"),
 961         SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0,
 962                            NULL,
 963                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 964         SND_SOC_DAPM_PGA_E("SPKR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
 965                            wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU |
 966                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 967         SND_SOC_DAPM_SUPPLY("DCLK", WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL,
 968                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 969         SND_SOC_DAPM_SUPPLY("ACLK", WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL,
 970                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 971         SND_SOC_DAPM_SUPPLY("Bandgap", WSA881X_TEMP_OP, 3, 0,
 972                             NULL,
 973                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 974         SND_SOC_DAPM_OUTPUT("SPKR"),
 975 };
 976
 977 static int wsa881x_hw_params(struct snd_pcm_substream *substream,
 978                              struct snd_pcm_hw_params *params,
 979                              struct snd_soc_dai *dai)
 980 {
 981         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
 982         int i;
 983
 984         wsa881x->active_ports = 0;
 985         for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) {
 986                 if (!wsa881x->port_enable[i])
 987                         continue;
 988
 989                 wsa881x->port_config[wsa881x->active_ports] =
 990                                                         wsa881x_pconfig[i];
 991                 wsa881x->active_ports++;
 992         }
 993
 994         return sdw_stream_add_slave(wsa881x->slave, &wsa881x->sconfig,
 995                                     wsa881x->port_config, wsa881x->active_ports,
 996                                     wsa881x->sruntime);
 997 }
 998
 999 static int wsa881x_hw_free(struct snd_pcm_substream *substream,
1000                            struct snd_soc_dai *dai)
1001 {
1002         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1003
1004         sdw_stream_remove_slave(wsa881x->slave, wsa881x->sruntime);
1005
1006         return 0;
1007 }
1008
1009 static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai,
1010                                   void *stream, int direction)
1011 {
1012         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1013
1014         wsa881x->sruntime = stream;
1015
1016         return 0;
1017 }
1018
1019 static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1020 {
1021         struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1022
1023         if (mute)
1024                 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1025                                    0x00);
1026         else
1027                 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1028                                    0x80);
1029
1030         return 0;
1031 }
1032
1033 static const struct snd_soc_dai_ops wsa881x_dai_ops = {
1034         .hw_params = wsa881x_hw_params,
1035         .hw_free = wsa881x_hw_free,
1036         .mute_stream = wsa881x_digital_mute,
1037         .set_stream = wsa881x_set_sdw_stream,
1038 };
1039
1040 static struct snd_soc_dai_driver wsa881x_dais[] = {
1041         {
1042                 .name = "SPKR",
1043                 .id = 0,
1044                 .playback = {
1045                         .stream_name = "SPKR Playback",
1046                         .rates = SNDRV_PCM_RATE_48000,
1047                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1048                         .rate_max = 48000,
1049                         .rate_min = 48000,
1050                         .channels_min = 1,
1051                         .channels_max = 1,
1052                 },
1053                 .ops = &wsa881x_dai_ops,
1054         },
1055 };
1056
1057 static const struct snd_soc_component_driver wsa881x_component_drv = {
1058         .name = "WSA881x",
1059         .probe = wsa881x_component_probe,
1060         .controls = wsa881x_snd_controls,
1061         .num_controls = ARRAY_SIZE(wsa881x_snd_controls),
1062         .dapm_widgets = wsa881x_dapm_widgets,
1063         .num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets),
1064         .dapm_routes = wsa881x_audio_map,
1065         .num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map),
1066         .endianness = 1,
1067 };
1068
1069 static int wsa881x_update_status(struct sdw_slave *slave,
1070                                  enum sdw_slave_status status)
1071 {
1072         struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1073
1074         if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
1075                 wsa881x_init(wsa881x);
1076
1077         return 0;
1078 }
1079
1080 static int wsa881x_port_prep(struct sdw_slave *slave,
1081                              struct sdw_prepare_ch *prepare_ch,
1082                              enum sdw_port_prep_ops state)
1083 {
1084         struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1085
1086         if (state == SDW_OPS_PORT_POST_PREP)
1087                 wsa881x->port_prepared[prepare_ch->num - 1] = true;
1088         else
1089                 wsa881x->port_prepared[prepare_ch->num - 1] = false;
1090
1091         return 0;
1092 }
1093
1094 static int wsa881x_bus_config(struct sdw_slave *slave,
1095                               struct sdw_bus_params *params)
1096 {
1097         sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank),
1098                   0x01);
1099
1100         return 0;
1101 }
1102
1103 static const struct sdw_slave_ops wsa881x_slave_ops = {
1104         .update_status = wsa881x_update_status,
1105         .bus_config = wsa881x_bus_config,
1106         .port_prep = wsa881x_port_prep,
1107 };
1108
1109 static int wsa881x_probe(struct sdw_slave *pdev,
1110                          const struct sdw_device_id *id)
1111 {
1112         struct wsa881x_priv *wsa881x;
1113         struct device *dev = &pdev->dev;
1114
1115         wsa881x = devm_kzalloc(&pdev->dev, sizeof(*wsa881x), GFP_KERNEL);
1116         if (!wsa881x)
1117                 return -ENOMEM;
1118
1119         wsa881x->sd_n = devm_gpiod_get_optional(&pdev->dev, "powerdown",
1120                                                 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1121         if (IS_ERR(wsa881x->sd_n)) {
1122                 dev_err(&pdev->dev, "Shutdown Control GPIO not found\n");
1123                 return PTR_ERR(wsa881x->sd_n);
1124         }
1125
1126         dev_set_drvdata(&pdev->dev, wsa881x);
1127         wsa881x->slave = pdev;
1128         wsa881x->dev = &pdev->dev;
1129         wsa881x->sconfig.ch_count = 1;
1130         wsa881x->sconfig.bps = 1;
1131         wsa881x->sconfig.frame_rate = 48000;
1132         wsa881x->sconfig.direction = SDW_DATA_DIR_RX;
1133         wsa881x->sconfig.type = SDW_STREAM_PDM;
1134         pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0);
1135         pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
1136         pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1137         gpiod_direction_output(wsa881x->sd_n, 1);
1138
1139         wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config);
1140         if (IS_ERR(wsa881x->regmap)) {
1141                 dev_err(&pdev->dev, "regmap_init failed\n");
1142                 return PTR_ERR(wsa881x->regmap);
1143         }
1144
1145         pm_runtime_set_autosuspend_delay(dev, 3000);
1146         pm_runtime_use_autosuspend(dev);
1147         pm_runtime_mark_last_busy(dev);
1148         pm_runtime_set_active(dev);
1149         pm_runtime_enable(dev);
1150
1151         return devm_snd_soc_register_component(&pdev->dev,
1152                                                &wsa881x_component_drv,
1153                                                wsa881x_dais,
1154                                                ARRAY_SIZE(wsa881x_dais));
1155 }
1156
1157 static int __maybe_unused wsa881x_runtime_suspend(struct device *dev)
1158 {
1159         struct regmap *regmap = dev_get_regmap(dev, NULL);
1160         struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
1161
1162         gpiod_direction_output(wsa881x->sd_n, 0);
1163
1164         regcache_cache_only(regmap, true);
1165         regcache_mark_dirty(regmap);
1166
1167         return 0;
1168 }
1169
1170 static int __maybe_unused wsa881x_runtime_resume(struct device *dev)
1171 {
1172         struct sdw_slave *slave = dev_to_sdw_dev(dev);
1173         struct regmap *regmap = dev_get_regmap(dev, NULL);
1174         struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
1175         unsigned long time;
1176
1177         gpiod_direction_output(wsa881x->sd_n, 1);
1178
1179         time = wait_for_completion_timeout(&slave->initialization_complete,
1180                                            msecs_to_jiffies(WSA881X_PROBE_TIMEOUT));
1181         if (!time) {
1182                 dev_err(dev, "Initialization not complete, timed out\n");
1183                 gpiod_direction_output(wsa881x->sd_n, 0);
1184                 return -ETIMEDOUT;
1185         }
1186
1187         regcache_cache_only(regmap, false);
1188         regcache_sync(regmap);
1189
1190         return 0;
1191 }
1192
1193 static const struct dev_pm_ops wsa881x_pm_ops = {
1194         SET_RUNTIME_PM_OPS(wsa881x_runtime_suspend, wsa881x_runtime_resume, NULL)
1195 };
1196
1197 static const struct sdw_device_id wsa881x_slave_id[] = {
1198         SDW_SLAVE_ENTRY(0x0217, 0x2010, 0),
1199         SDW_SLAVE_ENTRY(0x0217, 0x2110, 0),
1200         {},
1201 };
1202 MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id);
1203
1204 static struct sdw_driver wsa881x_codec_driver = {
1205         .probe  = wsa881x_probe,
1206         .ops = &wsa881x_slave_ops,
1207         .id_table = wsa881x_slave_id,
1208         .driver = {
1209                 .name   = "wsa881x-codec",
1210                 .pm = &wsa881x_pm_ops,
1211         }
1212 };
1213 module_sdw_driver(wsa881x_codec_driver);
1214
1215 MODULE_DESCRIPTION("WSA881x codec driver");
1216 MODULE_LICENSE("GPL v2");