codecs/rt1308-sdw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver
   4 //
   5 // Copyright(c) 2019 Realtek Semiconductor Corp.
   6 //
   7 //
   8 #include <linux/delay.h>
   9 #include <linux/device.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/mod_devicetable.h>
  12 #include <linux/soundwire/sdw.h>
  13 #include <linux/soundwire/sdw_type.h>
  14 #include <linux/soundwire/sdw_registers.h>
  15 #include <linux/module.h>
  16 #include <linux/regmap.h>
  17 #include <sound/core.h>
  18 #include <sound/pcm.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/soc.h>
  21 #include <sound/soc-dapm.h>
  22 #include <sound/initval.h>
  23
  24 #include "rt1308.h"
  25 #include "rt1308-sdw.h"
  26
  27 static bool rt1308_readable_register(struct device *dev, unsigned int reg)
  28 {
  29         switch (reg) {
  30         case 0x00e0:
  31         case 0x00f0:
  32         case 0x2f01 ... 0x2f07:
  33         case 0x3000 ... 0x3001:
  34         case 0x3004 ... 0x3005:
  35         case 0x3008:
  36         case 0x300a:
  37         case 0xc000 ... 0xcff3:
  38                 return true;
  39         default:
  40                 return false;
  41         }
  42 }
  43
  44 static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
  45 {
  46         switch (reg) {
  47         case 0x2f01 ... 0x2f07:
  48         case 0x3000 ... 0x3001:
  49         case 0x3004 ... 0x3005:
  50         case 0x3008:
  51         case 0x300a:
  52         case 0xc000:
  53         case 0xc710:
  54         case 0xc860 ... 0xc863:
  55         case 0xc870 ... 0xc873:
  56                 return true;
  57         default:
  58                 return false;
  59         }
  60 }
  61
  62 static const struct regmap_config rt1308_sdw_regmap = {
  63         .reg_bits = 32,
  64         .val_bits = 8,
  65         .readable_reg = rt1308_readable_register,
  66         .volatile_reg = rt1308_volatile_register,
  67         .max_register = 0xcfff,
  68         .reg_defaults = rt1308_reg_defaults,
  69         .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults),
  70         .cache_type = REGCACHE_RBTREE,
  71         .use_single_read = true,
  72         .use_single_write = true,
  73 };
  74
  75 /* Bus clock frequency */
  76 #define RT1308_CLK_FREQ_9600000HZ 9600000
  77 #define RT1308_CLK_FREQ_12000000HZ 12000000
  78 #define RT1308_CLK_FREQ_6000000HZ 6000000
  79 #define RT1308_CLK_FREQ_4800000HZ 4800000
  80 #define RT1308_CLK_FREQ_2400000HZ 2400000
  81 #define RT1308_CLK_FREQ_12288000HZ 12288000
  82
  83 static int rt1308_clock_config(struct device *dev)
  84 {
  85         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
  86         unsigned int clk_freq, value;
  87
  88         clk_freq = (rt1308->params.curr_dr_freq >> 1);
  89
  90         switch (clk_freq) {
  91         case RT1308_CLK_FREQ_12000000HZ:
  92                 value = 0x0;
  93                 break;
  94         case RT1308_CLK_FREQ_6000000HZ:
  95                 value = 0x1;
  96                 break;
  97         case RT1308_CLK_FREQ_9600000HZ:
  98                 value = 0x2;
  99                 break;
 100         case RT1308_CLK_FREQ_4800000HZ:
 101                 value = 0x3;
 102                 break;
 103         case RT1308_CLK_FREQ_2400000HZ:
 104                 value = 0x4;
 105                 break;
 106         case RT1308_CLK_FREQ_12288000HZ:
 107                 value = 0x5;
 108                 break;
 109         default:
 110                 return -EINVAL;
 111         }
 112
 113         regmap_write(rt1308->regmap, 0xe0, value);
 114         regmap_write(rt1308->regmap, 0xf0, value);
 115
 116         dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
 117
 118         return 0;
 119 }
 120
 121 static int rt1308_read_prop(struct sdw_slave *slave)
 122 {
 123         struct sdw_slave_prop *prop = &slave->prop;
 124         int nval, i;
 125         u32 bit;
 126         unsigned long addr;
 127         struct sdw_dpn_prop *dpn;
 128
 129         prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
 130         prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
 131
 132         prop->paging_support = true;
 133
 134         /* first we need to allocate memory for set bits in port lists */
 135         prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */
 136         prop->sink_ports = 0x2; /* BITMAP:  00000010 */
 137
 138         /* for sink */
 139         nval = hweight32(prop->sink_ports);
 140         prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
 141                                                 sizeof(*prop->sink_dpn_prop),
 142                                                 GFP_KERNEL);
 143         if (!prop->sink_dpn_prop)
 144                 return -ENOMEM;
 145
 146         i = 0;
 147         dpn = prop->sink_dpn_prop;
 148         addr = prop->sink_ports;
 149         for_each_set_bit(bit, &addr, 32) {
 150                 dpn[i].num = bit;
 151                 dpn[i].type = SDW_DPN_FULL;
 152                 dpn[i].simple_ch_prep_sm = true;
 153                 dpn[i].ch_prep_timeout = 10;
 154                 i++;
 155         }
 156
 157         /* set the timeout values */
 158         prop->clk_stop_timeout = 20;
 159
 160         dev_dbg(&slave->dev, "%s\n", __func__);
 161
 162         return 0;
 163 }
 164
 165 static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308)
 166 {
 167         unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp;
 168         unsigned int efuse_c_btl_l, efuse_c_btl_r;
 169
 170         /* read efuse to apply calibration parameters */
 171         regmap_write(rt1308->regmap, 0xc7f0, 0x04);
 172         regmap_write(rt1308->regmap, 0xc7f1, 0xfe);
 173         msleep(100);
 174         regmap_write(rt1308->regmap, 0xc7f0, 0x44);
 175         msleep(20);
 176         regmap_write(rt1308->regmap, 0xc240, 0x10);
 177
 178         regmap_read(rt1308->regmap, 0xc861, &tmp);
 179         efuse_m_btl_l = tmp;
 180         regmap_read(rt1308->regmap, 0xc860, &tmp);
 181         efuse_m_btl_l = efuse_m_btl_l | (tmp << 8);
 182         regmap_read(rt1308->regmap, 0xc863, &tmp);
 183         efuse_c_btl_l = tmp;
 184         regmap_read(rt1308->regmap, 0xc862, &tmp);
 185         efuse_c_btl_l = efuse_c_btl_l | (tmp << 8);
 186         regmap_read(rt1308->regmap, 0xc871, &tmp);
 187         efuse_m_btl_r = tmp;
 188         regmap_read(rt1308->regmap, 0xc870, &tmp);
 189         efuse_m_btl_r = efuse_m_btl_r | (tmp << 8);
 190         regmap_read(rt1308->regmap, 0xc873, &tmp);
 191         efuse_c_btl_r = tmp;
 192         regmap_read(rt1308->regmap, 0xc872, &tmp);
 193         efuse_c_btl_r = efuse_c_btl_r | (tmp << 8);
 194         dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__,
 195                 efuse_m_btl_l, efuse_m_btl_r);
 196         dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__,
 197                 efuse_c_btl_l, efuse_c_btl_r);
 198 }
 199
 200 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave)
 201 {
 202         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
 203         int ret = 0;
 204         unsigned int tmp;
 205
 206         if (rt1308->hw_init)
 207                 return 0;
 208
 209         if (rt1308->first_hw_init) {
 210                 regcache_cache_only(rt1308->regmap, false);
 211                 regcache_cache_bypass(rt1308->regmap, true);
 212         }
 213
 214         /*
 215          * PM runtime is only enabled when a Slave reports as Attached
 216          */
 217         if (!rt1308->first_hw_init) {
 218                 /* set autosuspend parameters */
 219                 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
 220                 pm_runtime_use_autosuspend(&slave->dev);
 221
 222                 /* update count of parent 'active' children */
 223                 pm_runtime_set_active(&slave->dev);
 224
 225                 /* make sure the device does not suspend immediately */
 226                 pm_runtime_mark_last_busy(&slave->dev);
 227
 228                 pm_runtime_enable(&slave->dev);
 229         }
 230
 231         pm_runtime_get_noresume(&slave->dev);
 232
 233         /* sw reset */
 234         regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0);
 235
 236         regmap_read(rt1308->regmap, 0xc710, &tmp);
 237         rt1308->hw_ver = tmp;
 238         dev_dbg(dev, "%s, hw_ver=0x%x\n", __func__, rt1308->hw_ver);
 239
 240         /* initial settings */
 241         regmap_write(rt1308->regmap, 0xc103, 0xc0);
 242         regmap_write(rt1308->regmap, 0xc030, 0x17);
 243         regmap_write(rt1308->regmap, 0xc031, 0x81);
 244         regmap_write(rt1308->regmap, 0xc032, 0x26);
 245         regmap_write(rt1308->regmap, 0xc040, 0x80);
 246         regmap_write(rt1308->regmap, 0xc041, 0x80);
 247         regmap_write(rt1308->regmap, 0xc042, 0x06);
 248         regmap_write(rt1308->regmap, 0xc052, 0x0a);
 249         regmap_write(rt1308->regmap, 0xc080, 0x0a);
 250         regmap_write(rt1308->regmap, 0xc060, 0x02);
 251         regmap_write(rt1308->regmap, 0xc061, 0x75);
 252         regmap_write(rt1308->regmap, 0xc062, 0x05);
 253         regmap_write(rt1308->regmap, 0xc171, 0x07);
 254         regmap_write(rt1308->regmap, 0xc173, 0x0d);
 255         if (rt1308->hw_ver == RT1308_VER_C) {
 256                 regmap_write(rt1308->regmap, 0xc311, 0x7f);
 257                 regmap_write(rt1308->regmap, 0xc300, 0x09);
 258         } else {
 259                 regmap_write(rt1308->regmap, 0xc311, 0x4f);
 260                 regmap_write(rt1308->regmap, 0xc300, 0x0b);
 261         }
 262         regmap_write(rt1308->regmap, 0xc900, 0x5a);
 263         regmap_write(rt1308->regmap, 0xc1a0, 0x84);
 264         regmap_write(rt1308->regmap, 0xc1a1, 0x01);
 265         regmap_write(rt1308->regmap, 0xc360, 0x78);
 266         regmap_write(rt1308->regmap, 0xc361, 0x87);
 267         regmap_write(rt1308->regmap, 0xc0a1, 0x71);
 268         regmap_write(rt1308->regmap, 0xc210, 0x00);
 269         regmap_write(rt1308->regmap, 0xc070, 0x00);
 270         regmap_write(rt1308->regmap, 0xc100, 0xd7);
 271         regmap_write(rt1308->regmap, 0xc101, 0xd7);
 272
 273         if (rt1308->first_hw_init) {
 274                 regcache_cache_bypass(rt1308->regmap, false);
 275                 regcache_mark_dirty(rt1308->regmap);
 276         } else
 277                 rt1308->first_hw_init = true;
 278
 279         /* Mark Slave initialization complete */
 280         rt1308->hw_init = true;
 281
 282         pm_runtime_mark_last_busy(&slave->dev);
 283         pm_runtime_put_autosuspend(&slave->dev);
 284
 285         dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
 286
 287         return ret;
 288 }
 289
 290 static int rt1308_update_status(struct sdw_slave *slave,
 291                                         enum sdw_slave_status status)
 292 {
 293         struct  rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
 294
 295         /* Update the status */
 296         rt1308->status = status;
 297
 298         if (status == SDW_SLAVE_UNATTACHED)
 299                 rt1308->hw_init = false;
 300
 301         /*
 302          * Perform initialization only if slave status is present and
 303          * hw_init flag is false
 304          */
 305         if (rt1308->hw_init || rt1308->status != SDW_SLAVE_ATTACHED)
 306                 return 0;
 307
 308         /* perform I/O transfers required for Slave initialization */
 309         return rt1308_io_init(&slave->dev, slave);
 310 }
 311
 312 static int rt1308_bus_config(struct sdw_slave *slave,
 313                                 struct sdw_bus_params *params)
 314 {
 315         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
 316         int ret;
 317
 318         memcpy(&rt1308->params, params, sizeof(*params));
 319
 320         ret = rt1308_clock_config(&slave->dev);
 321         if (ret < 0)
 322                 dev_err(&slave->dev, "Invalid clk config");
 323
 324         return ret;
 325 }
 326
 327 static int rt1308_interrupt_callback(struct sdw_slave *slave,
 328                                         struct sdw_slave_intr_status *status)
 329 {
 330         dev_dbg(&slave->dev,
 331                 "%s control_port_stat=%x", __func__, status->control_port);
 332
 333         return 0;
 334 }
 335
 336 static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
 337         struct snd_kcontrol *kcontrol, int event)
 338 {
 339         struct snd_soc_component *component =
 340                 snd_soc_dapm_to_component(w->dapm);
 341         struct rt1308_sdw_priv *rt1308 =
 342                 snd_soc_component_get_drvdata(component);
 343
 344         switch (event) {
 345         case SND_SOC_DAPM_POST_PMU:
 346                 msleep(30);
 347                 snd_soc_component_update_bits(component,
 348                         RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
 349                         0x3,    0x3);
 350                 msleep(40);
 351                 rt1308_apply_calib_params(rt1308);
 352                 break;
 353         case SND_SOC_DAPM_PRE_PMD:
 354                 snd_soc_component_update_bits(component,
 355                         RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
 356                         0x3, 0);
 357                 usleep_range(150000, 200000);
 358                 break;
 359
 360         default:
 361                 break;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static const char * const rt1308_rx_data_ch_select[] = {
 368         "LR",
 369         "LL",
 370         "RL",
 371         "RR",
 372 };
 373
 374 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum,
 375         RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0,
 376         rt1308_rx_data_ch_select);
 377
 378 static const struct snd_kcontrol_new rt1308_snd_controls[] = {
 379
 380         /* I2S Data Channel Selection */
 381         SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
 382 };
 383
 384 static const struct snd_kcontrol_new rt1308_sto_dac_l =
 385         SOC_DAPM_SINGLE_AUTODISABLE("Switch",
 386                 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
 387                 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
 388
 389 static const struct snd_kcontrol_new rt1308_sto_dac_r =
 390         SOC_DAPM_SINGLE_AUTODISABLE("Switch",
 391                 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
 392                 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
 393
 394 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
 395         /* Audio Interface */
 396         SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
 397
 398         /* Supply Widgets */
 399         SND_SOC_DAPM_SUPPLY("MBIAS20U",
 400                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        7, 0, NULL, 0),
 401         SND_SOC_DAPM_SUPPLY("ALDO",
 402                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        6, 0, NULL, 0),
 403         SND_SOC_DAPM_SUPPLY("DBG",
 404                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        5, 0, NULL, 0),
 405         SND_SOC_DAPM_SUPPLY("DACL",
 406                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        4, 0, NULL, 0),
 407         SND_SOC_DAPM_SUPPLY("CLK25M",
 408                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        2, 0, NULL, 0),
 409         SND_SOC_DAPM_SUPPLY("ADC_R",
 410                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        1, 0, NULL, 0),
 411         SND_SOC_DAPM_SUPPLY("ADC_L",
 412                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        0, 0, NULL, 0),
 413         SND_SOC_DAPM_SUPPLY("DAC Power",
 414                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        3, 0, NULL, 0),
 415
 416         SND_SOC_DAPM_SUPPLY("DLDO",
 417                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  5, 0, NULL, 0),
 418         SND_SOC_DAPM_SUPPLY("VREF",
 419                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  4, 0, NULL, 0),
 420         SND_SOC_DAPM_SUPPLY("MIXER_R",
 421                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  2, 0, NULL, 0),
 422         SND_SOC_DAPM_SUPPLY("MIXER_L",
 423                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  1, 0, NULL, 0),
 424         SND_SOC_DAPM_SUPPLY("MBIAS4U",
 425                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  0, 0, NULL, 0),
 426
 427         SND_SOC_DAPM_SUPPLY("PLL2_LDO",
 428                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0),
 429         SND_SOC_DAPM_SUPPLY("PLL2B",
 430                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0),
 431         SND_SOC_DAPM_SUPPLY("PLL2F",
 432                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0),
 433         SND_SOC_DAPM_SUPPLY("PLL2F2",
 434                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0),
 435         SND_SOC_DAPM_SUPPLY("PLL2B2",
 436                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0),
 437
 438         /* Digital Interface */
 439         SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
 440         SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
 441         SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
 442
 443         /* Output Lines */
 444         SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
 445                 rt1308_classd_event,
 446                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 447         SND_SOC_DAPM_OUTPUT("SPOL"),
 448         SND_SOC_DAPM_OUTPUT("SPOR"),
 449 };
 450
 451 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
 452
 453         { "DAC", NULL, "AIF1RX" },
 454
 455         { "DAC", NULL, "MBIAS20U" },
 456         { "DAC", NULL, "ALDO" },
 457         { "DAC", NULL, "DBG" },
 458         { "DAC", NULL, "DACL" },
 459         { "DAC", NULL, "CLK25M" },
 460         { "DAC", NULL, "ADC_R" },
 461         { "DAC", NULL, "ADC_L" },
 462         { "DAC", NULL, "DLDO" },
 463         { "DAC", NULL, "VREF" },
 464         { "DAC", NULL, "MIXER_R" },
 465         { "DAC", NULL, "MIXER_L" },
 466         { "DAC", NULL, "MBIAS4U" },
 467         { "DAC", NULL, "PLL2_LDO" },
 468         { "DAC", NULL, "PLL2B" },
 469         { "DAC", NULL, "PLL2F" },
 470         { "DAC", NULL, "PLL2F2" },
 471         { "DAC", NULL, "PLL2B2" },
 472
 473         { "DAC L", "Switch", "DAC" },
 474         { "DAC R", "Switch", "DAC" },
 475         { "DAC L", NULL, "DAC Power" },
 476         { "DAC R", NULL, "DAC Power" },
 477
 478         { "CLASS D", NULL, "DAC L" },
 479         { "CLASS D", NULL, "DAC R" },
 480         { "SPOL", NULL, "CLASS D" },
 481         { "SPOR", NULL, "CLASS D" },
 482 };
 483
 484 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
 485                                 int direction)
 486 {
 487         struct sdw_stream_data *stream;
 488
 489         if (!sdw_stream)
 490                 return 0;
 491
 492         stream = kzalloc(sizeof(*stream), GFP_KERNEL);
 493         if (!stream)
 494                 return -ENOMEM;
 495
 496         stream->sdw_stream = sdw_stream;
 497
 498         /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
 499         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
 500                 dai->playback_dma_data = stream;
 501         else
 502                 dai->capture_dma_data = stream;
 503
 504         return 0;
 505 }
 506
 507 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream,
 508                                 struct snd_soc_dai *dai)
 509 {
 510         struct sdw_stream_data *stream;
 511
 512         stream = snd_soc_dai_get_dma_data(dai, substream);
 513         snd_soc_dai_set_dma_data(dai, substream, NULL);
 514         kfree(stream);
 515 }
 516
 517 static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai,
 518                                    unsigned int tx_mask,
 519                                    unsigned int rx_mask,
 520                                    int slots, int slot_width)
 521 {
 522         struct snd_soc_component *component = dai->component;
 523         struct rt1308_sdw_priv *rt1308 =
 524                 snd_soc_component_get_drvdata(component);
 525
 526         if (tx_mask)
 527                 return -EINVAL;
 528
 529         if (slots > 2)
 530                 return -EINVAL;
 531
 532         rt1308->rx_mask = rx_mask;
 533         rt1308->slots = slots;
 534         /* slot_width is not used since it's irrelevant for SoundWire */
 535
 536         return 0;
 537 }
 538
 539 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream,
 540         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 541 {
 542         struct snd_soc_component *component = dai->component;
 543         struct rt1308_sdw_priv *rt1308 =
 544                 snd_soc_component_get_drvdata(component);
 545         struct sdw_stream_config stream_config;
 546         struct sdw_port_config port_config;
 547         enum sdw_data_direction direction;
 548         struct sdw_stream_data *stream;
 549         int retval, port, num_channels, ch_mask;
 550
 551         dev_dbg(dai->dev, "%s %s", __func__, dai->name);
 552         stream = snd_soc_dai_get_dma_data(dai, substream);
 553
 554         if (!stream)
 555                 return -EINVAL;
 556
 557         if (!rt1308->sdw_slave)
 558                 return -EINVAL;
 559
 560         /* SoundWire specific configuration */
 561         /* port 1 for playback */
 562         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 563                 direction = SDW_DATA_DIR_RX;
 564                 port = 1;
 565         } else {
 566                 return -EINVAL;
 567         }
 568
 569         if (rt1308->slots) {
 570                 num_channels = rt1308->slots;
 571                 ch_mask = rt1308->rx_mask;
 572         } else {
 573                 num_channels = params_channels(params);
 574                 ch_mask = (1 << num_channels) - 1;
 575         }
 576
 577         stream_config.frame_rate = params_rate(params);
 578         stream_config.ch_count = num_channels;
 579         stream_config.bps = snd_pcm_format_width(params_format(params));
 580         stream_config.direction = direction;
 581
 582         port_config.ch_mask = ch_mask;
 583         port_config.num = port;
 584
 585         retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config,
 586                                 &port_config, 1, stream->sdw_stream);
 587         if (retval) {
 588                 dev_err(dai->dev, "Unable to configure port\n");
 589                 return retval;
 590         }
 591
 592         return retval;
 593 }
 594
 595 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
 596                                 struct snd_soc_dai *dai)
 597 {
 598         struct snd_soc_component *component = dai->component;
 599         struct rt1308_sdw_priv *rt1308 =
 600                 snd_soc_component_get_drvdata(component);
 601         struct sdw_stream_data *stream =
 602                 snd_soc_dai_get_dma_data(dai, substream);
 603
 604         if (!rt1308->sdw_slave)
 605                 return -EINVAL;
 606
 607         sdw_stream_remove_slave(rt1308->sdw_slave, stream->sdw_stream);
 608         return 0;
 609 }
 610
 611 /*
 612  * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
 613  * port_prep are not defined for now
 614  */
 615 static const struct sdw_slave_ops rt1308_slave_ops = {
 616         .read_prop = rt1308_read_prop,
 617         .interrupt_callback = rt1308_interrupt_callback,
 618         .update_status = rt1308_update_status,
 619         .bus_config = rt1308_bus_config,
 620 };
 621
 622 static int rt1308_sdw_component_probe(struct snd_soc_component *component)
 623 {
 624         int ret;
 625
 626         ret = pm_runtime_resume(component->dev);
 627         if (ret < 0 && ret != -EACCES)
 628                 return ret;
 629
 630         return 0;
 631 }
 632
 633 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = {
 634         .probe = rt1308_sdw_component_probe,
 635         .controls = rt1308_snd_controls,
 636         .num_controls = ARRAY_SIZE(rt1308_snd_controls),
 637         .dapm_widgets = rt1308_dapm_widgets,
 638         .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
 639         .dapm_routes = rt1308_dapm_routes,
 640         .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
 641         .endianness = 1,
 642 };
 643
 644 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
 645         .hw_params = rt1308_sdw_hw_params,
 646         .hw_free        = rt1308_sdw_pcm_hw_free,
 647         .set_stream     = rt1308_set_sdw_stream,
 648         .shutdown       = rt1308_sdw_shutdown,
 649         .set_tdm_slot   = rt1308_sdw_set_tdm_slot,
 650 };
 651
 652 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
 653 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
 654                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
 655                         SNDRV_PCM_FMTBIT_S24_LE)
 656
 657 static struct snd_soc_dai_driver rt1308_sdw_dai[] = {
 658         {
 659                 .name = "rt1308-aif",
 660                 .playback = {
 661                         .stream_name = "DP1 Playback",
 662                         .channels_min = 1,
 663                         .channels_max = 2,
 664                         .rates = RT1308_STEREO_RATES,
 665                         .formats = RT1308_FORMATS,
 666                 },
 667                 .ops = &rt1308_aif_dai_ops,
 668         },
 669 };
 670
 671 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap,
 672                                 struct sdw_slave *slave)
 673 {
 674         struct rt1308_sdw_priv *rt1308;
 675         int ret;
 676
 677         rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL);
 678         if (!rt1308)
 679                 return -ENOMEM;
 680
 681         dev_set_drvdata(dev, rt1308);
 682         rt1308->sdw_slave = slave;
 683         rt1308->regmap = regmap;
 684
 685         /*
 686          * Mark hw_init to false
 687          * HW init will be performed when device reports present
 688          */
 689         rt1308->hw_init = false;
 690         rt1308->first_hw_init = false;
 691
 692         ret =  devm_snd_soc_register_component(dev,
 693                                 &soc_component_sdw_rt1308,
 694                                 rt1308_sdw_dai,
 695                                 ARRAY_SIZE(rt1308_sdw_dai));
 696
 697         dev_dbg(&slave->dev, "%s\n", __func__);
 698
 699         return ret;
 700 }
 701
 702 static int rt1308_sdw_probe(struct sdw_slave *slave,
 703                                 const struct sdw_device_id *id)
 704 {
 705         struct regmap *regmap;
 706
 707         /* Regmap Initialization */
 708         regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap);
 709         if (IS_ERR(regmap))
 710                 return PTR_ERR(regmap);
 711
 712         rt1308_sdw_init(&slave->dev, regmap, slave);
 713
 714         return 0;
 715 }
 716
 717 static int rt1308_sdw_remove(struct sdw_slave *slave)
 718 {
 719         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
 720
 721         if (rt1308->first_hw_init)
 722                 pm_runtime_disable(&slave->dev);
 723
 724         return 0;
 725 }
 726
 727 static const struct sdw_device_id rt1308_id[] = {
 728         SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0),
 729         {},
 730 };
 731 MODULE_DEVICE_TABLE(sdw, rt1308_id);
 732
 733 static int __maybe_unused rt1308_dev_suspend(struct device *dev)
 734 {
 735         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
 736
 737         if (!rt1308->hw_init)
 738                 return 0;
 739
 740         regcache_cache_only(rt1308->regmap, true);
 741
 742         return 0;
 743 }
 744
 745 #define RT1308_PROBE_TIMEOUT 5000
 746
 747 static int __maybe_unused rt1308_dev_resume(struct device *dev)
 748 {
 749         struct sdw_slave *slave = dev_to_sdw_dev(dev);
 750         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
 751         unsigned long time;
 752
 753         if (!rt1308->first_hw_init)
 754                 return 0;
 755
 756         if (!slave->unattach_request)
 757                 goto regmap_sync;
 758
 759         time = wait_for_completion_timeout(&slave->initialization_complete,
 760                                 msecs_to_jiffies(RT1308_PROBE_TIMEOUT));
 761         if (!time) {
 762                 dev_err(&slave->dev, "Initialization not complete, timed out\n");
 763                 sdw_show_ping_status(slave->bus, true);
 764
 765                 return -ETIMEDOUT;
 766         }
 767
 768 regmap_sync:
 769         slave->unattach_request = 0;
 770         regcache_cache_only(rt1308->regmap, false);
 771         regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff);
 772
 773         return 0;
 774 }
 775
 776 static const struct dev_pm_ops rt1308_pm = {
 777         SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume)
 778         SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL)
 779 };
 780
 781 static struct sdw_driver rt1308_sdw_driver = {
 782         .driver = {
 783                 .name = "rt1308",
 784                 .owner = THIS_MODULE,
 785                 .pm = &rt1308_pm,
 786         },
 787         .probe = rt1308_sdw_probe,
 788         .remove = rt1308_sdw_remove,
 789         .ops = &rt1308_slave_ops,
 790         .id_table = rt1308_id,
 791 };
 792 module_sdw_driver(rt1308_sdw_driver);
 793
 794 MODULE_DESCRIPTION("ASoC RT1308 driver SDW");
 795 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
 796 MODULE_LICENSE("GPL v2");