1 // SPDX-License-Identifier: GPL-2.0-only
3 // nau8821.c -- Nuvoton NAU88L21 audio codec driver
5 // Copyright 2021 Nuvoton Technology Corp.
6 // Author: John Hsu <kchsu0@nuvoton.com>
7 // Co-author: Seven Lee <wtli@nuvoton.com>
10 #include <linux/acpi.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/math64.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/initval.h>
22 #include <sound/jack.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/tlv.h>
29 #define NAU8821_JD_ACTIVE_HIGH BIT(0)
31 static int nau8821_quirk;
32 static int quirk_override = -1;
33 module_param_named(quirk, quirk_override, uint, 0444);
34 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
36 #define NAU_FREF_MAX 13500000
37 #define NAU_FVCO_MAX 100000000
38 #define NAU_FVCO_MIN 90000000
40 #define NAU8821_BUTTON SND_JACK_BTN_0
42 /* the maximum frequency of CLK_ADC and CLK_DAC */
43 #define CLK_DA_AD_MAX 6144000
45 static int nau8821_configure_sysclk(struct nau8821 *nau8821,
46 int clk_id, unsigned int freq);
47 static bool nau8821_is_jack_inserted(struct regmap *regmap);
57 struct nau8821_fll_attr {
62 /* scaling for mclk from sysclk_src output */
63 static const struct nau8821_fll_attr mclk_src_scaling[] = {
79 /* ratio for input clk freq */
80 static const struct nau8821_fll_attr fll_ratio[] = {
90 static const struct nau8821_fll_attr fll_pre_scalar[] = {
97 /* over sampling rate */
98 struct nau8821_osr_attr {
100 unsigned int clk_src;
103 static const struct nau8821_osr_attr osr_dac_sel[] = {
104 { 64, 2 }, /* OSR 64, SRC 1/4 */
105 { 256, 0 }, /* OSR 256, SRC 1 */
106 { 128, 1 }, /* OSR 128, SRC 1/2 */
108 { 32, 3 }, /* OSR 32, SRC 1/8 */
111 static const struct nau8821_osr_attr osr_adc_sel[] = {
112 { 32, 3 }, /* OSR 32, SRC 1/8 */
113 { 64, 2 }, /* OSR 64, SRC 1/4 */
114 { 128, 1 }, /* OSR 128, SRC 1/2 */
115 { 256, 0 }, /* OSR 256, SRC 1 */
118 struct nau8821_dmic_speed {
123 static const struct nau8821_dmic_speed dmic_speed_sel[] = {
124 { 0, 0x0 }, /*SPEED 1, SRC 1 */
125 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */
126 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */
127 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */
130 static const struct reg_default nau8821_reg_defaults[] = {
131 { NAU8821_R01_ENA_CTRL, 0x00ff },
132 { NAU8821_R03_CLK_DIVIDER, 0x0050 },
133 { NAU8821_R04_FLL1, 0x0 },
134 { NAU8821_R05_FLL2, 0x00bc },
135 { NAU8821_R06_FLL3, 0x0008 },
136 { NAU8821_R07_FLL4, 0x0010 },
137 { NAU8821_R08_FLL5, 0x4000 },
138 { NAU8821_R09_FLL6, 0x6900 },
139 { NAU8821_R0A_FLL7, 0x0031 },
140 { NAU8821_R0B_FLL8, 0x26e9 },
141 { NAU8821_R0D_JACK_DET_CTRL, 0x0 },
142 { NAU8821_R0F_INTERRUPT_MASK, 0x0 },
143 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff },
144 { NAU8821_R13_DMIC_CTRL, 0x0 },
145 { NAU8821_R1A_GPIO12_CTRL, 0x0 },
146 { NAU8821_R1B_TDM_CTRL, 0x0 },
147 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a },
148 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 },
149 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 },
150 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 },
151 { NAU8821_R21_BIQ0_COF1, 0x0 },
152 { NAU8821_R22_BIQ0_COF2, 0x0 },
153 { NAU8821_R23_BIQ0_COF3, 0x0 },
154 { NAU8821_R24_BIQ0_COF4, 0x0 },
155 { NAU8821_R25_BIQ0_COF5, 0x0 },
156 { NAU8821_R26_BIQ0_COF6, 0x0 },
157 { NAU8821_R27_BIQ0_COF7, 0x0 },
158 { NAU8821_R28_BIQ0_COF8, 0x0 },
159 { NAU8821_R29_BIQ0_COF9, 0x0 },
160 { NAU8821_R2A_BIQ0_COF10, 0x0 },
161 { NAU8821_R2B_ADC_RATE, 0x0002 },
162 { NAU8821_R2C_DAC_CTRL1, 0x0082 },
163 { NAU8821_R2D_DAC_CTRL2, 0x0 },
164 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 },
165 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 },
166 { NAU8821_R31_MUTE_CTRL, 0x0 },
167 { NAU8821_R32_HSVOL_CTRL, 0x0 },
168 { NAU8821_R34_DACR_CTRL, 0xcfcf },
169 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf },
170 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 },
171 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 },
172 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff },
173 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 },
174 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 },
175 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 },
176 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 },
177 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 },
178 { NAU8821_R41_BIQ1_COF1, 0x0 },
179 { NAU8821_R42_BIQ1_COF2, 0x0 },
180 { NAU8821_R43_BIQ1_COF3, 0x0 },
181 { NAU8821_R44_BIQ1_COF4, 0x0 },
182 { NAU8821_R45_BIQ1_COF5, 0x0 },
183 { NAU8821_R46_BIQ1_COF6, 0x0 },
184 { NAU8821_R47_BIQ1_COF7, 0x0 },
185 { NAU8821_R48_BIQ1_COF8, 0x0 },
186 { NAU8821_R49_BIQ1_COF9, 0x0 },
187 { NAU8821_R4A_BIQ1_COF10, 0x0 },
188 { NAU8821_R4B_CLASSG_CTRL, 0x0 },
189 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 },
190 { NAU8821_R4D_IMM_RMS_L, 0x0 },
191 { NAU8821_R53_OTPDOUT_1, 0xaad8 },
192 { NAU8821_R54_OTPDOUT_2, 0x0002 },
193 { NAU8821_R55_MISC_CTRL, 0x0 },
194 { NAU8821_R66_BIAS_ADJ, 0x0 },
195 { NAU8821_R68_TRIM_SETTINGS, 0x0 },
196 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 },
197 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 },
198 { NAU8821_R6B_PGA_MUTE, 0x0 },
199 { NAU8821_R71_ANALOG_ADC_1, 0x0011 },
200 { NAU8821_R72_ANALOG_ADC_2, 0x0020 },
201 { NAU8821_R73_RDAC, 0x0008 },
202 { NAU8821_R74_MIC_BIAS, 0x0006 },
203 { NAU8821_R76_BOOST, 0x0 },
204 { NAU8821_R77_FEPGA, 0x0 },
205 { NAU8821_R7E_PGA_GAIN, 0x0 },
206 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 },
207 { NAU8821_R80_CHARGE_PUMP, 0x0 },
210 static bool nau8821_readable_reg(struct device *dev, unsigned int reg)
213 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
214 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
215 case NAU8821_R0D_JACK_DET_CTRL:
216 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL:
217 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
218 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
219 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
220 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
221 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3:
222 case NAU8821_R51_FUSE_CTRL1:
223 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL:
224 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
225 case NAU8821_R66_BIAS_ADJ:
226 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
227 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
228 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
229 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS:
236 static bool nau8821_writeable_reg(struct device *dev, unsigned int reg)
239 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
240 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
241 case NAU8821_R0D_JACK_DET_CTRL:
242 case NAU8821_R0F_INTERRUPT_MASK:
243 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL:
244 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
245 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
246 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
247 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
248 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL:
249 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3:
250 case NAU8821_R51_FUSE_CTRL1:
251 case NAU8821_R55_MISC_CTRL:
252 case NAU8821_R5A_SOFTWARE_RST:
253 case NAU8821_R66_BIAS_ADJ:
254 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
255 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
256 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
257 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP:
264 static bool nau8821_volatile_reg(struct device *dev, unsigned int reg)
267 case NAU8821_R00_RESET:
268 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS:
269 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10:
270 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10:
271 case NAU8821_R4D_IMM_RMS_L:
272 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2:
273 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
274 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS:
281 static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol,
282 struct snd_ctl_elem_value *ucontrol)
284 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
285 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
287 if (!component->regmap)
290 regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1,
291 ucontrol->value.bytes.data, params->max);
296 static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
299 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
300 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
303 if (!component->regmap)
306 data = kmemdup(ucontrol->value.bytes.data,
307 params->max, GFP_KERNEL | GFP_DMA);
311 regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1,
319 static const char * const nau8821_adc_decimation[] = {
320 "32", "64", "128", "256" };
322 static const struct soc_enum nau8821_adc_decimation_enum =
323 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT,
324 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation);
326 static const char * const nau8821_dac_oversampl[] = {
327 "64", "256", "128", "", "32" };
329 static const struct soc_enum nau8821_dac_oversampl_enum =
330 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT,
331 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl);
333 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400);
334 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
335 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0);
336 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1);
337 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
338 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400);
340 static const struct snd_kcontrol_new nau8821_controls[] = {
341 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1,
342 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT,
343 0xff, 0, adc_vol_tlv),
344 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL,
345 12, 8, 0x0f, 0, sidetone_vol_tlv),
346 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL,
347 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv),
348 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL,
349 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT,
350 0xcf, 0, playback_vol_tlv),
351 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN,
352 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT,
353 37, 0, fepga_gain_tlv),
354 SOC_DOUBLE_TLV("Headphone Crosstalk Volume",
355 NAU8821_R2F_DAC_DGAIN_CTRL,
356 0, 8, 0xff, 0, crosstalk_vol_tlv),
358 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum),
359 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum),
360 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
361 nau8821_biq_coeff_get, nau8821_biq_coeff_put),
362 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL,
363 NAU8821_ADCPHS_SFT, 1, 0),
366 static const struct snd_kcontrol_new nau8821_dmic_mode_switch =
367 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL,
368 NAU8821_DMIC_EN_SFT, 1, 0);
370 static int dmic_clock_control(struct snd_soc_dapm_widget *w,
371 struct snd_kcontrol *k, int event)
373 struct snd_soc_component *component =
374 snd_soc_dapm_to_component(w->dapm);
375 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
376 int i, speed_selection = -1, clk_adc_src, clk_adc;
377 unsigned int clk_divider_r03;
379 /* The DMIC clock is gotten from adc clock divided by
380 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or
381 * less than nau8821->dmic_clk_threshold.
383 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
385 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK)
386 >> NAU8821_CLK_ADC_SRC_SFT;
387 clk_adc = (nau8821->fs * 256) >> clk_adc_src;
389 for (i = 0 ; i < 4 ; i++)
390 if ((clk_adc >> dmic_speed_sel[i].param) <=
391 nau8821->dmic_clk_threshold) {
392 speed_selection = dmic_speed_sel[i].val;
398 dev_dbg(nau8821->dev,
399 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n",
400 clk_adc, nau8821->dmic_clk_threshold,
401 dmic_speed_sel[i].param, dmic_speed_sel[i].val);
402 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL,
403 NAU8821_DMIC_SRC_MASK,
404 (speed_selection << NAU8821_DMIC_SRC_SFT));
409 static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w,
410 struct snd_kcontrol *kcontrol, int event)
412 struct snd_soc_component *component =
413 snd_soc_dapm_to_component(w->dapm);
414 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
417 case SND_SOC_DAPM_POST_PMU:
419 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
420 NAU8821_EN_ADCL, NAU8821_EN_ADCL);
422 case SND_SOC_DAPM_POST_PMD:
423 regmap_update_bits(nau8821->regmap,
424 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCL, 0);
433 static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w,
434 struct snd_kcontrol *kcontrol, int event)
436 struct snd_soc_component *component =
437 snd_soc_dapm_to_component(w->dapm);
438 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
441 case SND_SOC_DAPM_POST_PMU:
443 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
444 NAU8821_EN_ADCR, NAU8821_EN_ADCR);
446 case SND_SOC_DAPM_POST_PMD:
447 regmap_update_bits(nau8821->regmap,
448 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCR, 0);
457 static int nau8821_pump_event(struct snd_soc_dapm_widget *w,
458 struct snd_kcontrol *kcontrol, int event)
460 struct snd_soc_component *component =
461 snd_soc_dapm_to_component(w->dapm);
462 struct nau8821 *nau8821 =
463 snd_soc_component_get_drvdata(component);
466 case SND_SOC_DAPM_POST_PMU:
467 /* Prevent startup click by letting charge pump to ramp up */
469 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
470 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW);
472 case SND_SOC_DAPM_PRE_PMD:
473 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
474 NAU8821_JAMNODCLOW, 0);
483 static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w,
484 struct snd_kcontrol *kcontrol, int event)
486 struct snd_soc_component *component =
487 snd_soc_dapm_to_component(w->dapm);
488 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
491 case SND_SOC_DAPM_PRE_PMU:
492 /* Disables the TESTDAC to let DAC signal pass through. */
493 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
494 NAU8821_BIAS_TESTDAC_EN, 0);
496 case SND_SOC_DAPM_POST_PMD:
497 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
498 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN);
507 static int system_clock_control(struct snd_soc_dapm_widget *w,
508 struct snd_kcontrol *k, int event)
510 struct snd_soc_component *component =
511 snd_soc_dapm_to_component(w->dapm);
512 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
514 if (SND_SOC_DAPM_EVENT_OFF(event)) {
515 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n");
516 /* Set clock source to disable or internal clock before the
517 * playback or capture end. Codec needs clock for Jack
518 * detection and button press if jack inserted; otherwise,
519 * the clock should be closed.
521 if (nau8821_is_jack_inserted(nau8821->regmap)) {
522 nau8821_configure_sysclk(nau8821,
523 NAU8821_CLK_INTERNAL, 0);
525 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
531 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = {
532 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
533 system_clock_control, SND_SOC_DAPM_POST_PMD),
534 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS,
535 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0),
536 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
537 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
538 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2,
539 NAU8821_POWERUP_ADCL_SFT, 0),
540 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2,
541 NAU8821_POWERUP_ADCR_SFT, 0),
542 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL,
543 NAU8821_PUP_PGA_L_SFT, 0, NULL, 0),
544 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL,
545 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0),
546 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL,
547 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event,
548 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
549 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL,
550 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event,
551 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
552 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM,
553 0, 0, &nau8821_dmic_mode_switch),
554 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2,
555 NAU8821_I2S_TRISTATE_SFT, 1),
556 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
558 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC,
559 NAU8821_DACL_EN_SFT, 0, NULL, 0),
560 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC,
561 NAU8821_DACR_EN_SFT, 0, NULL, 0),
562 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC,
563 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0),
564 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC,
565 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0),
566 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL,
567 NAU8821_EN_DACR_SFT, 0),
568 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL,
569 NAU8821_EN_DACL_SFT, 0),
570 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL,
571 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0),
572 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL,
573 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0),
574 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP,
575 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event,
576 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
577 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
578 NAU8821_R7F_POWER_UP_CONTROL,
579 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0),
580 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
581 NAU8821_R7F_POWER_UP_CONTROL,
582 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0),
583 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
584 NAU8821_R7F_POWER_UP_CONTROL,
585 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0),
586 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
587 NAU8821_R7F_POWER_UP_CONTROL,
588 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0),
589 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
590 NAU8821_R7F_POWER_UP_CONTROL,
591 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0),
592 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
593 NAU8821_R7F_POWER_UP_CONTROL,
594 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0),
595 SND_SOC_DAPM_PGA_S("Output DACL", 7,
596 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT,
597 0, nau8821_output_dac_event,
598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
599 SND_SOC_DAPM_PGA_S("Output DACR", 7,
600 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT,
601 0, nau8821_output_dac_event,
602 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
604 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
605 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
606 NAU8821_R0D_JACK_DET_CTRL,
607 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0),
608 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
609 NAU8821_R0D_JACK_DET_CTRL,
610 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0),
612 /* High current HPOL/R boost driver */
613 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
614 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0),
615 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL,
616 NAU8821_CLASSG_EN_SFT, 0, NULL, 0),
618 SND_SOC_DAPM_INPUT("MICL"),
619 SND_SOC_DAPM_INPUT("MICR"),
620 SND_SOC_DAPM_INPUT("DMIC"),
621 SND_SOC_DAPM_OUTPUT("HPOL"),
622 SND_SOC_DAPM_OUTPUT("HPOR"),
625 static const struct snd_soc_dapm_route nau8821_dapm_routes[] = {
626 {"DMIC Enable", "Switch", "DMIC"},
627 {"DMIC Enable", NULL, "DMIC Clock"},
629 {"Frontend PGA L", NULL, "MICL"},
630 {"Frontend PGA R", NULL, "MICR"},
631 {"Frontend PGA L", NULL, "MICBIAS"},
632 {"Frontend PGA R", NULL, "MICBIAS"},
634 {"ADCL Power", NULL, "Frontend PGA L"},
635 {"ADCR Power", NULL, "Frontend PGA R"},
637 {"ADCL Digital path", NULL, "ADCL Power"},
638 {"ADCR Digital path", NULL, "ADCR Power"},
639 {"ADCL Digital path", NULL, "DMIC Enable"},
640 {"ADCR Digital path", NULL, "DMIC Enable"},
642 {"AIFTX", NULL, "ADCL Digital path"},
643 {"AIFTX", NULL, "ADCR Digital path"},
645 {"AIFTX", NULL, "System Clock"},
646 {"AIFRX", NULL, "System Clock"},
648 {"DDACL", NULL, "AIFRX"},
649 {"DDACR", NULL, "AIFRX"},
651 {"HP amp L", NULL, "DDACL"},
652 {"HP amp R", NULL, "DDACR"},
654 {"Charge Pump", NULL, "HP amp L"},
655 {"Charge Pump", NULL, "HP amp R"},
657 {"ADACL", NULL, "Charge Pump"},
658 {"ADACR", NULL, "Charge Pump"},
659 {"ADACL Clock", NULL, "ADACL"},
660 {"ADACR Clock", NULL, "ADACR"},
662 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
663 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
664 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
665 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
666 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
667 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
668 {"Output DACL", NULL, "Output Driver L Stage 3"},
669 {"Output DACR", NULL, "Output Driver R Stage 3"},
671 {"HPOL Pulldown", NULL, "Output DACL"},
672 {"HPOR Pulldown", NULL, "Output DACR"},
673 {"HP Boost Driver", NULL, "HPOL Pulldown"},
674 {"HP Boost Driver", NULL, "HPOR Pulldown"},
676 {"Class G", NULL, "HP Boost Driver"},
677 {"HPOL", NULL, "Class G"},
678 {"HPOR", NULL, "Class G"},
681 static const struct nau8821_osr_attr *
682 nau8821_get_osr(struct nau8821 *nau8821, int stream)
686 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
687 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr);
688 osr &= NAU8821_DAC_OVERSAMPLE_MASK;
689 if (osr >= ARRAY_SIZE(osr_dac_sel))
691 return &osr_dac_sel[osr];
693 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr);
694 osr &= NAU8821_ADC_SYNC_DOWN_MASK;
695 if (osr >= ARRAY_SIZE(osr_adc_sel))
697 return &osr_adc_sel[osr];
701 static int nau8821_dai_startup(struct snd_pcm_substream *substream,
702 struct snd_soc_dai *dai)
704 struct snd_soc_component *component = dai->component;
705 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
706 const struct nau8821_osr_attr *osr;
708 osr = nau8821_get_osr(nau8821, substream->stream);
709 if (!osr || !osr->osr)
712 return snd_pcm_hw_constraint_minmax(substream->runtime,
713 SNDRV_PCM_HW_PARAM_RATE,
714 0, CLK_DA_AD_MAX / osr->osr);
717 static int nau8821_hw_params(struct snd_pcm_substream *substream,
718 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
720 struct snd_soc_component *component = dai->component;
721 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
722 unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div;
723 const struct nau8821_osr_attr *osr;
725 nau8821->fs = params_rate(params);
726 /* CLK_DAC or CLK_ADC = OSR * FS
727 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
728 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
729 * values must be selected such that the maximum frequency is less
732 osr = nau8821_get_osr(nau8821, substream->stream);
733 if (!osr || !osr->osr)
735 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX)
737 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
738 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
739 NAU8821_CLK_DAC_SRC_MASK,
740 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT);
742 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
743 NAU8821_CLK_ADC_SRC_MASK,
744 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT);
746 /* make BCLK and LRC divde configuration if the codec as master. */
747 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val);
748 if (ctrl_val & NAU8821_I2S_MS_MASTER) {
749 /* get the bclk and fs ratio */
750 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs;
753 else if (bclk_fs <= 64)
755 else if (bclk_fs <= 128)
760 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
761 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK,
762 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div);
765 switch (params_width(params)) {
767 val_len |= NAU8821_I2S_DL_16;
770 val_len |= NAU8821_I2S_DL_20;
773 val_len |= NAU8821_I2S_DL_24;
776 val_len |= NAU8821_I2S_DL_32;
782 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
783 NAU8821_I2S_DL_MASK, val_len);
788 static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
790 struct snd_soc_component *component = codec_dai->component;
791 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
792 unsigned int ctrl1_val = 0, ctrl2_val = 0;
794 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
795 case SND_SOC_DAIFMT_CBP_CFP:
796 ctrl2_val |= NAU8821_I2S_MS_MASTER;
798 case SND_SOC_DAIFMT_CBC_CFC:
804 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
805 case SND_SOC_DAIFMT_NB_NF:
807 case SND_SOC_DAIFMT_IB_NF:
808 ctrl1_val |= NAU8821_I2S_BP_INV;
814 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
815 case SND_SOC_DAIFMT_I2S:
816 ctrl1_val |= NAU8821_I2S_DF_I2S;
818 case SND_SOC_DAIFMT_LEFT_J:
819 ctrl1_val |= NAU8821_I2S_DF_LEFT;
821 case SND_SOC_DAIFMT_RIGHT_J:
822 ctrl1_val |= NAU8821_I2S_DF_RIGTH;
824 case SND_SOC_DAIFMT_DSP_A:
825 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
827 case SND_SOC_DAIFMT_DSP_B:
828 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
829 ctrl1_val |= NAU8821_I2S_PCMB_EN;
835 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
836 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK |
837 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val);
838 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
839 NAU8821_I2S_MS_MASK, ctrl2_val);
844 static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute,
847 struct snd_soc_component *component = dai->component;
848 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
849 unsigned int val = 0;
852 val = NAU8821_DAC_SOFT_MUTE;
854 return regmap_update_bits(nau8821->regmap,
855 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val);
858 static const struct snd_soc_dai_ops nau8821_dai_ops = {
859 .startup = nau8821_dai_startup,
860 .hw_params = nau8821_hw_params,
861 .set_fmt = nau8821_set_dai_fmt,
862 .mute_stream = nau8821_digital_mute,
863 .no_capture_mute = 1,
866 #define NAU8821_RATES SNDRV_PCM_RATE_8000_192000
867 #define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
868 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
870 static struct snd_soc_dai_driver nau8821_dai = {
871 .name = NUVOTON_CODEC_DAI,
873 .stream_name = "Playback",
876 .rates = NAU8821_RATES,
877 .formats = NAU8821_FORMATS,
880 .stream_name = "Capture",
883 .rates = NAU8821_RATES,
884 .formats = NAU8821_FORMATS,
886 .ops = &nau8821_dai_ops,
890 static bool nau8821_is_jack_inserted(struct regmap *regmap)
892 bool active_high, is_high;
895 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet);
896 active_high = jkdet & NAU8821_JACK_POLARITY;
897 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status);
898 is_high = status & NAU8821_GPIO2_IN;
899 /* return jack connection status according to jack insertion logic
900 * active high or active low.
902 return active_high == is_high;
905 static void nau8821_int_status_clear_all(struct regmap *regmap)
907 int active_irq, clear_irq, i;
909 /* Reset the intrruption status from rightmost bit if the corres-
910 * ponding irq event occurs.
912 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq);
913 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) {
914 clear_irq = (0x1 << i);
915 if (active_irq & clear_irq)
917 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
921 static void nau8821_eject_jack(struct nau8821 *nau8821)
923 struct snd_soc_dapm_context *dapm = nau8821->dapm;
924 struct regmap *regmap = nau8821->regmap;
925 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
927 /* Detach 2kOhm Resistors from MICBIAS to MICGND */
928 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
929 NAU8821_MICBIAS_JKR2, 0);
930 /* HPL/HPR short to ground */
931 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
932 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
933 snd_soc_component_disable_pin(component, "MICBIAS");
934 snd_soc_dapm_sync(dapm);
936 /* Clear all interruption status */
937 nau8821_int_status_clear_all(regmap);
939 /* Enable the insertion interruption, disable the ejection inter-
940 * ruption, and then bypass de-bounce circuit.
942 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
943 NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS,
944 NAU8821_IRQ_EJECT_DIS);
945 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
946 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
947 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
948 NAU8821_IRQ_EJECT_EN);
950 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
951 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS);
953 /* Close clock for jack type detection at manual mode */
954 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
955 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
957 /* Recover to normal channel input */
958 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
959 NAU8821_ADC_R_SRC_EN, 0);
960 if (nau8821->key_enable) {
961 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
962 NAU8821_IRQ_KEY_RELEASE_EN |
963 NAU8821_IRQ_KEY_PRESS_EN,
964 NAU8821_IRQ_KEY_RELEASE_EN |
965 NAU8821_IRQ_KEY_PRESS_EN);
966 regmap_update_bits(regmap,
967 NAU8821_R12_INTERRUPT_DIS_CTRL,
968 NAU8821_IRQ_KEY_RELEASE_DIS |
969 NAU8821_IRQ_KEY_PRESS_DIS,
970 NAU8821_IRQ_KEY_RELEASE_DIS |
971 NAU8821_IRQ_KEY_PRESS_DIS);
976 static void nau8821_jdet_work(struct work_struct *work)
978 struct nau8821 *nau8821 =
979 container_of(work, struct nau8821, jdet_work);
980 struct snd_soc_dapm_context *dapm = nau8821->dapm;
981 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
982 struct regmap *regmap = nau8821->regmap;
983 int jack_status_reg, mic_detected, event = 0, event_mask = 0;
985 snd_soc_component_force_enable_pin(component, "MICBIAS");
986 snd_soc_dapm_sync(dapm);
989 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg);
990 mic_detected = !(jack_status_reg & NAU8821_KEYDET);
992 dev_dbg(nau8821->dev, "Headset connected\n");
993 event |= SND_JACK_HEADSET;
995 /* 2kOhm Resistor from MICBIAS to MICGND1 */
996 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
997 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2);
998 /* Latch Right Channel Analog data
999 * input into the Right Channel Filter
1001 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1002 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN);
1003 if (nau8821->key_enable) {
1004 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1005 NAU8821_IRQ_KEY_RELEASE_EN |
1006 NAU8821_IRQ_KEY_PRESS_EN, 0);
1007 regmap_update_bits(regmap,
1008 NAU8821_R12_INTERRUPT_DIS_CTRL,
1009 NAU8821_IRQ_KEY_RELEASE_DIS |
1010 NAU8821_IRQ_KEY_PRESS_DIS, 0);
1013 dev_dbg(nau8821->dev, "Headphone connected\n");
1014 event |= SND_JACK_HEADPHONE;
1015 snd_soc_component_disable_pin(component, "MICBIAS");
1016 snd_soc_dapm_sync(dapm);
1018 event_mask |= SND_JACK_HEADSET;
1019 snd_soc_jack_report(nau8821->jack, event, event_mask);
1022 /* Enable interruptions with internal clock. */
1023 static void nau8821_setup_inserted_irq(struct nau8821 *nau8821)
1025 struct regmap *regmap = nau8821->regmap;
1027 /* Enable internal VCO needed for interruptions */
1028 if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE)
1029 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0);
1031 /* Chip needs one FSCLK cycle in order to generate interruptions,
1032 * as we cannot guarantee one will be provided by the system. Turning
1033 * master mode on then off enables us to generate that FSCLK cycle
1034 * with a minimum of contention on the clock bus.
1036 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1037 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER);
1038 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1039 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE);
1041 /* Not bypass de-bounce circuit */
1042 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1043 NAU8821_JACK_DET_DB_BYPASS, 0);
1045 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1046 NAU8821_IRQ_EJECT_EN, 0);
1047 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1048 NAU8821_IRQ_EJECT_DIS, 0);
1051 static irqreturn_t nau8821_interrupt(int irq, void *data)
1053 struct nau8821 *nau8821 = (struct nau8821 *)data;
1054 struct regmap *regmap = nau8821->regmap;
1055 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1057 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) {
1058 dev_err(nau8821->dev, "failed to read irq status\n");
1062 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq);
1064 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) ==
1065 NAU8821_JACK_EJECT_DETECTED) {
1066 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1067 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS);
1068 nau8821_eject_jack(nau8821);
1069 event_mask |= SND_JACK_HEADSET;
1070 clear_irq = NAU8821_JACK_EJECT_IRQ_MASK;
1071 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) {
1072 event |= NAU8821_BUTTON;
1073 event_mask |= NAU8821_BUTTON;
1074 clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ;
1075 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) {
1076 event_mask = NAU8821_BUTTON;
1077 clear_irq = NAU8821_KEY_RELEASE_IRQ;
1078 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) ==
1079 NAU8821_JACK_INSERT_DETECTED) {
1080 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1081 NAU8821_MICDET_MASK, NAU8821_MICDET_EN);
1082 if (nau8821_is_jack_inserted(regmap)) {
1083 /* detect microphone and jack type */
1084 cancel_work_sync(&nau8821->jdet_work);
1085 schedule_work(&nau8821->jdet_work);
1086 /* Turn off insertion interruption at manual mode */
1087 regmap_update_bits(regmap,
1088 NAU8821_R12_INTERRUPT_DIS_CTRL,
1089 NAU8821_IRQ_INSERT_DIS,
1090 NAU8821_IRQ_INSERT_DIS);
1091 regmap_update_bits(regmap,
1092 NAU8821_R0F_INTERRUPT_MASK,
1093 NAU8821_IRQ_INSERT_EN,
1094 NAU8821_IRQ_INSERT_EN);
1095 nau8821_setup_inserted_irq(nau8821);
1097 dev_warn(nau8821->dev,
1098 "Inserted IRQ fired but not connected\n");
1099 nau8821_eject_jack(nau8821);
1104 clear_irq = active_irq;
1105 /* clears the rightmost interruption */
1106 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
1109 snd_soc_jack_report(nau8821->jack, event, event_mask);
1114 static const struct regmap_config nau8821_regmap_config = {
1115 .val_bits = NAU8821_REG_DATA_LEN,
1116 .reg_bits = NAU8821_REG_ADDR_LEN,
1118 .max_register = NAU8821_REG_MAX,
1119 .readable_reg = nau8821_readable_reg,
1120 .writeable_reg = nau8821_writeable_reg,
1121 .volatile_reg = nau8821_volatile_reg,
1123 .cache_type = REGCACHE_RBTREE,
1124 .reg_defaults = nau8821_reg_defaults,
1125 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults),
1128 static int nau8821_component_probe(struct snd_soc_component *component)
1130 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1131 struct snd_soc_dapm_context *dapm =
1132 snd_soc_component_get_dapm(component);
1134 nau8821->dapm = dapm;
1140 * nau8821_calc_fll_param - Calculate FLL parameters.
1141 * @fll_in: external clock provided to codec.
1142 * @fs: sampling rate.
1143 * @fll_param: Pointer to structure of FLL parameters.
1145 * Calculate FLL parameters to configure codec.
1147 * Returns 0 for success or negative error code.
1149 static int nau8821_calc_fll_param(unsigned int fll_in,
1150 unsigned int fs, struct nau8821_fll *fll_param)
1153 unsigned int fref, i, fvco_sel;
1155 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by
1156 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1157 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK
1159 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1160 fref = fll_in >> fll_pre_scalar[i].param;
1161 if (fref <= NAU_FREF_MAX)
1164 if (i == ARRAY_SIZE(fll_pre_scalar))
1166 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1168 /* Choose the FLL ratio based on FREF */
1169 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1170 if (fref >= fll_ratio[i].param)
1173 if (i == ARRAY_SIZE(fll_ratio))
1175 fll_param->ratio = fll_ratio[i].val;
1177 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1178 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be
1179 * guaranteed across the full range of operation.
1180 * FDCO = freq_out * 2 * mclk_src_scaling
1183 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1184 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1185 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1186 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1192 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1194 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1196 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional
1197 * input based on FDCO, FREF and FLL ratio.
1199 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio);
1200 fll_param->fll_int = (fvco >> 24) & 0x3ff;
1201 fll_param->fll_frac = fvco & 0xffffff;
1206 static void nau8821_fll_apply(struct nau8821 *nau8821,
1207 struct nau8821_fll *fll_param)
1209 struct regmap *regmap = nau8821->regmap;
1211 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1212 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK,
1213 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src);
1214 /* Make DSP operate at high speed for better performance. */
1215 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1216 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK,
1217 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT));
1218 /* FLL 24-bit fractional input */
1219 regmap_write(regmap, NAU8821_R0A_FLL7,
1220 (fll_param->fll_frac >> 16) & 0xff);
1221 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff);
1222 /* FLL 10-bit integer input */
1223 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1224 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int);
1225 /* FLL pre-scaler */
1226 regmap_update_bits(regmap, NAU8821_R07_FLL4,
1227 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK,
1229 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT));
1230 /* select divided VCO input */
1231 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1232 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF);
1233 /* Disable free-running mode */
1234 regmap_update_bits(regmap,
1235 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0);
1236 if (fll_param->fll_frac) {
1237 /* set FLL loop filter enable and cutoff frequency at 500Khz */
1238 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1239 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1240 NAU8821_FLL_FTR_SW_MASK,
1241 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1242 NAU8821_FLL_FTR_SW_FILTER);
1243 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1244 NAU8821_SDM_EN | NAU8821_CUTOFF500,
1245 NAU8821_SDM_EN | NAU8821_CUTOFF500);
1247 /* disable FLL loop filter and cutoff frequency */
1248 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1249 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1250 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU);
1251 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1252 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0);
1257 * nau8821_set_fll - FLL configuration of nau8821
1258 * @component: codec component
1259 * @pll_id: PLL requested
1260 * @source: clock source
1261 * @freq_in: frequency of input clock source
1262 * @freq_out: must be 256*Fs in order to achieve the best performance
1264 * The FLL function can select BCLK or MCLK as the input clock source.
1266 * Returns 0 if the parameters have been applied successfully
1267 * or negative error code.
1269 static int nau8821_set_fll(struct snd_soc_component *component,
1270 int pll_id, int source, unsigned int freq_in, unsigned int freq_out)
1272 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1273 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param;
1277 ret = nau8821_calc_fll_param(freq_in, fs, fll_param);
1279 dev_err(nau8821->dev,
1280 "Unsupported input clock %d to output clock %d\n",
1284 dev_dbg(nau8821->dev,
1285 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1286 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac,
1287 fll_param->fll_int, fll_param->clk_ref_div);
1289 nau8821_fll_apply(nau8821, fll_param);
1291 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
1292 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1297 static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap)
1299 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1300 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK);
1301 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1303 /* Make DSP operate as default setting for power saving. */
1304 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1305 NAU8821_ICTRL_LATCH_MASK, 0);
1308 static int nau8821_configure_sysclk(struct nau8821 *nau8821,
1309 int clk_id, unsigned int freq)
1311 struct regmap *regmap = nau8821->regmap;
1314 case NAU8821_CLK_DIS:
1315 /* Clock provided externally and disable internal VCO clock */
1316 nau8821_configure_mclk_as_sysclk(regmap);
1318 case NAU8821_CLK_MCLK:
1319 nau8821_configure_mclk_as_sysclk(regmap);
1320 /* MCLK not changed by clock tree */
1321 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1322 NAU8821_CLK_MCLK_SRC_MASK, 0);
1324 case NAU8821_CLK_INTERNAL:
1325 if (nau8821_is_jack_inserted(regmap)) {
1326 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1327 NAU8821_DCO_EN, NAU8821_DCO_EN);
1328 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1329 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1330 /* Decrease the VCO frequency and make DSP operate
1331 * as default setting for power saving.
1333 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1334 NAU8821_CLK_MCLK_SRC_MASK, 0xf);
1335 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1336 NAU8821_ICTRL_LATCH_MASK |
1337 NAU8821_FLL_RATIO_MASK, 0x10);
1338 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1339 NAU8821_SDM_EN, NAU8821_SDM_EN);
1342 case NAU8821_CLK_FLL_MCLK:
1343 /* Higher FLL reference input frequency can only set lower
1344 * gain error, such as 0000 for input reference from MCLK
1347 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1348 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1349 NAU8821_FLL_CLK_SRC_MCLK | 0);
1351 case NAU8821_CLK_FLL_BLK:
1352 /* If FLL reference input is from low frequency source,
1353 * higher error gain can apply such as 0xf which has
1354 * the most sensitive gain error correction threshold,
1355 * Therefore, FLL has the most accurate DCO to
1358 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1359 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1360 NAU8821_FLL_CLK_SRC_BLK |
1361 (0xf << NAU8821_GAIN_ERR_SFT));
1363 case NAU8821_CLK_FLL_FS:
1364 /* If FLL reference input is from low frequency source,
1365 * higher error gain can apply such as 0xf which has
1366 * the most sensitive gain error correction threshold,
1367 * Therefore, FLL has the most accurate DCO to
1370 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1371 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1372 NAU8821_FLL_CLK_SRC_FS |
1373 (0xf << NAU8821_GAIN_ERR_SFT));
1376 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id);
1379 nau8821->clk_id = clk_id;
1380 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1386 static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id,
1387 int source, unsigned int freq, int dir)
1389 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1391 return nau8821_configure_sysclk(nau8821, clk_id, freq);
1394 static int nau8821_resume_setup(struct nau8821 *nau8821)
1396 struct regmap *regmap = nau8821->regmap;
1398 /* Close clock when jack type detection at manual mode */
1399 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
1401 /* Clear all interruption status */
1402 nau8821_int_status_clear_all(regmap);
1404 /* Enable both insertion and ejection interruptions, and then
1405 * bypass de-bounce circuit.
1407 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1408 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0);
1409 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1410 NAU8821_JACK_DET_DB_BYPASS,
1411 NAU8821_JACK_DET_DB_BYPASS);
1412 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1413 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0);
1419 static int nau8821_set_bias_level(struct snd_soc_component *component,
1420 enum snd_soc_bias_level level)
1422 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1423 struct regmap *regmap = nau8821->regmap;
1426 case SND_SOC_BIAS_ON:
1429 case SND_SOC_BIAS_PREPARE:
1432 case SND_SOC_BIAS_STANDBY:
1433 /* Setup codec configuration after resume */
1434 if (snd_soc_component_get_bias_level(component) ==
1436 nau8821_resume_setup(nau8821);
1439 case SND_SOC_BIAS_OFF:
1440 /* HPL/HPR short to ground */
1441 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1442 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
1444 /* Reset the configuration of jack type for detection.
1445 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2.
1447 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1448 NAU8821_MICBIAS_JKR2, 0);
1449 /* Turn off all interruptions before system shutdown.
1450 * Keep theinterruption quiet before resume
1453 regmap_write(regmap,
1454 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff);
1455 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1456 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
1457 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN);
1467 static int __maybe_unused nau8821_suspend(struct snd_soc_component *component)
1469 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1472 disable_irq(nau8821->irq);
1473 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1474 /* Power down codec power; don't support button wakeup */
1475 snd_soc_component_disable_pin(component, "MICBIAS");
1476 snd_soc_dapm_sync(nau8821->dapm);
1477 regcache_cache_only(nau8821->regmap, true);
1478 regcache_mark_dirty(nau8821->regmap);
1483 static int __maybe_unused nau8821_resume(struct snd_soc_component *component)
1485 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1487 regcache_cache_only(nau8821->regmap, false);
1488 regcache_sync(nau8821->regmap);
1490 enable_irq(nau8821->irq);
1495 static const struct snd_soc_component_driver nau8821_component_driver = {
1496 .probe = nau8821_component_probe,
1497 .set_sysclk = nau8821_set_sysclk,
1498 .set_pll = nau8821_set_fll,
1499 .set_bias_level = nau8821_set_bias_level,
1500 .suspend = nau8821_suspend,
1501 .resume = nau8821_resume,
1502 .controls = nau8821_controls,
1503 .num_controls = ARRAY_SIZE(nau8821_controls),
1504 .dapm_widgets = nau8821_dapm_widgets,
1505 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets),
1506 .dapm_routes = nau8821_dapm_routes,
1507 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes),
1508 .suspend_bias_off = 1,
1510 .use_pmdown_time = 1,
1515 * nau8821_enable_jack_detect - Specify a jack for event reporting
1517 * @component: component to register the jack with
1518 * @jack: jack to use to report headset and button events on
1520 * After this function has been called the headset insert/remove and button
1521 * events will be routed to the given jack. Jack can be null to stop
1524 int nau8821_enable_jack_detect(struct snd_soc_component *component,
1525 struct snd_soc_jack *jack)
1527 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1530 nau8821->jack = jack;
1531 /* Initiate jack detection work queue */
1532 INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work);
1533 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL,
1534 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1535 "nau8821", nau8821);
1537 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n",
1544 EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect);
1546 static void nau8821_reset_chip(struct regmap *regmap)
1548 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1549 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1552 static void nau8821_print_device_properties(struct nau8821 *nau8821)
1554 struct device *dev = nau8821->dev;
1556 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable);
1557 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable);
1558 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up);
1559 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity);
1560 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage);
1561 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance);
1562 dev_dbg(dev, "jack-insert-debounce: %d\n",
1563 nau8821->jack_insert_debounce);
1564 dev_dbg(dev, "jack-eject-debounce: %d\n",
1565 nau8821->jack_eject_debounce);
1566 dev_dbg(dev, "dmic-clk-threshold: %d\n",
1567 nau8821->dmic_clk_threshold);
1568 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable);
1571 static int nau8821_read_device_properties(struct device *dev,
1572 struct nau8821 *nau8821)
1576 nau8821->jkdet_enable = device_property_read_bool(dev,
1577 "nuvoton,jkdet-enable");
1578 nau8821->jkdet_pull_enable = device_property_read_bool(dev,
1579 "nuvoton,jkdet-pull-enable");
1580 nau8821->jkdet_pull_up = device_property_read_bool(dev,
1581 "nuvoton,jkdet-pull-up");
1582 nau8821->key_enable = device_property_read_bool(dev,
1583 "nuvoton,key-enable");
1584 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1585 &nau8821->jkdet_polarity);
1587 nau8821->jkdet_polarity = 1;
1588 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1589 &nau8821->micbias_voltage);
1591 nau8821->micbias_voltage = 6;
1592 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1593 &nau8821->vref_impedance);
1595 nau8821->vref_impedance = 2;
1596 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
1597 &nau8821->jack_insert_debounce);
1599 nau8821->jack_insert_debounce = 7;
1600 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1601 &nau8821->jack_eject_debounce);
1603 nau8821->jack_eject_debounce = 0;
1604 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold",
1605 &nau8821->dmic_clk_threshold);
1607 nau8821->dmic_clk_threshold = 3072000;
1612 static void nau8821_init_regs(struct nau8821 *nau8821)
1614 struct regmap *regmap = nau8821->regmap;
1616 /* Enable Bias/Vmid */
1617 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1618 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID);
1619 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1620 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN);
1621 /* VMID Tieoff setting and enable TESTDAC.
1622 * This sets the analog DAC inputs to a '0' input signal to avoid
1623 * any glitches due to power up transients in both the analog and
1624 * digital DAC circuit.
1626 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1627 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN,
1628 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) |
1629 NAU8821_BIAS_TESTDAC_EN);
1630 /* Disable short Frame Sync detection logic */
1631 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT,
1632 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET);
1633 /* Disable Boost Driver, Automatic Short circuit protection enable */
1634 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1635 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1636 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN,
1637 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1638 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN);
1639 /* Class G timer 64ms */
1640 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL,
1641 NAU8821_CLASSG_TIMER_MASK,
1642 0x20 << NAU8821_CLASSG_TIMER_SFT);
1643 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1644 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2,
1645 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1646 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB,
1647 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1648 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB);
1649 /* Disable DACR/L power */
1650 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP,
1651 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0);
1652 /* DAC clock delay 2ns, VREF */
1653 regmap_update_bits(regmap, NAU8821_R73_RDAC,
1654 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK,
1655 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) |
1656 (0x3 << NAU8821_DAC_VREF_SFT));
1658 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1659 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage);
1660 /* Default oversampling/decimations settings are unusable
1661 * (audible hiss). Set it to something better.
1663 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1664 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64);
1665 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1,
1666 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64);
1669 static int nau8821_setup_irq(struct nau8821 *nau8821)
1671 struct regmap *regmap = nau8821->regmap;
1673 /* Jack detection */
1674 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1675 NAU8821_JKDET_OUTPUT_EN,
1676 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN);
1677 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1678 NAU8821_JKDET_PULL_EN,
1679 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN);
1680 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1681 NAU8821_JKDET_PULL_UP,
1682 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0);
1683 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1684 NAU8821_JACK_POLARITY,
1685 /* jkdet_polarity - 1 is for active-low */
1686 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY);
1687 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1688 NAU8821_JACK_INSERT_DEBOUNCE_MASK,
1689 nau8821->jack_insert_debounce <<
1690 NAU8821_JACK_INSERT_DEBOUNCE_SFT);
1691 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1692 NAU8821_JACK_EJECT_DEBOUNCE_MASK,
1693 nau8821->jack_eject_debounce <<
1694 NAU8821_JACK_EJECT_DEBOUNCE_SFT);
1695 /* Pull up IRQ pin */
1696 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1697 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN |
1698 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP |
1699 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN);
1700 /* Disable interruption before codec initiation done */
1701 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1702 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5);
1707 /* Please keep this list alphabetically sorted */
1708 static const struct dmi_system_id nau8821_quirk_table[] = {
1710 /* Positivo CW14Q01P-V2 */
1712 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
1713 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P-V2"),
1715 .driver_data = (void *)(NAU8821_JD_ACTIVE_HIGH),
1720 static void nau8821_check_quirks(void)
1722 const struct dmi_system_id *dmi_id;
1724 if (quirk_override != -1) {
1725 nau8821_quirk = quirk_override;
1729 dmi_id = dmi_first_match(nau8821_quirk_table);
1731 nau8821_quirk = (unsigned long)dmi_id->driver_data;
1734 static int nau8821_i2c_probe(struct i2c_client *i2c)
1736 struct device *dev = &i2c->dev;
1737 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev);
1741 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL);
1744 nau8821_read_device_properties(dev, nau8821);
1746 i2c_set_clientdata(i2c, nau8821);
1748 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config);
1749 if (IS_ERR(nau8821->regmap))
1750 return PTR_ERR(nau8821->regmap);
1753 nau8821->irq = i2c->irq;
1755 nau8821_check_quirks();
1757 if (nau8821_quirk & NAU8821_JD_ACTIVE_HIGH)
1758 nau8821->jkdet_polarity = 0;
1760 nau8821_print_device_properties(nau8821);
1762 nau8821_reset_chip(nau8821->regmap);
1763 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value);
1765 dev_err(dev, "Failed to read device id (%d)\n", ret);
1768 nau8821_init_regs(nau8821);
1771 nau8821_setup_irq(nau8821);
1773 ret = devm_snd_soc_register_component(&i2c->dev,
1774 &nau8821_component_driver, &nau8821_dai, 1);
1779 static const struct i2c_device_id nau8821_i2c_ids[] = {
1783 MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids);
1786 static const struct of_device_id nau8821_of_ids[] = {
1787 { .compatible = "nuvoton,nau8821", },
1790 MODULE_DEVICE_TABLE(of, nau8821_of_ids);
1794 static const struct acpi_device_id nau8821_acpi_match[] = {
1798 MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match);
1801 static struct i2c_driver nau8821_driver = {
1804 .of_match_table = of_match_ptr(nau8821_of_ids),
1805 .acpi_match_table = ACPI_PTR(nau8821_acpi_match),
1807 .probe_new = nau8821_i2c_probe,
1808 .id_table = nau8821_i2c_ids,
1810 module_i2c_driver(nau8821_driver);
1812 MODULE_DESCRIPTION("ASoC nau8821 driver");
1813 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>");
1814 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>");
1815 MODULE_LICENSE("GPL");