codecs/max98373-sdw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (c) 2020, Maxim Integrated
   3
   4 #include <linux/acpi.h>
   5 #include <linux/delay.h>
   6 #include <linux/module.h>
   7 #include <linux/mod_devicetable.h>
   8 #include <linux/pm_runtime.h>
   9 #include <linux/regmap.h>
  10 #include <linux/slab.h>
  11 #include <sound/pcm.h>
  12 #include <sound/pcm_params.h>
  13 #include <sound/soc.h>
  14 #include <sound/tlv.h>
  15 #include <linux/of.h>
  16 #include <linux/soundwire/sdw.h>
  17 #include <linux/soundwire/sdw_type.h>
  18 #include <linux/soundwire/sdw_registers.h>
  19 #include "max98373.h"
  20 #include "max98373-sdw.h"
  21
  22 struct sdw_stream_data {
  23         struct sdw_stream_runtime *sdw_stream;
  24 };
  25
  26 static const u32 max98373_sdw_cache_reg[] = {
  27         MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK,
  28         MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK,
  29         MAX98373_R20B6_BDE_CUR_STATE_READBACK,
  30 };
  31
  32 static struct reg_default max98373_reg[] = {
  33         {MAX98373_R0040_SCP_INIT_STAT_1, 0x00},
  34         {MAX98373_R0041_SCP_INIT_MASK_1, 0x00},
  35         {MAX98373_R0042_SCP_INIT_STAT_2, 0x00},
  36         {MAX98373_R0044_SCP_CTRL, 0x00},
  37         {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00},
  38         {MAX98373_R0046_SCP_DEV_NUMBER, 0x00},
  39         {MAX98373_R0050_SCP_DEV_ID_0, 0x21},
  40         {MAX98373_R0051_SCP_DEV_ID_1, 0x01},
  41         {MAX98373_R0052_SCP_DEV_ID_2, 0x9F},
  42         {MAX98373_R0053_SCP_DEV_ID_3, 0x87},
  43         {MAX98373_R0054_SCP_DEV_ID_4, 0x08},
  44         {MAX98373_R0055_SCP_DEV_ID_5, 0x00},
  45         {MAX98373_R0060_SCP_FRAME_CTLR, 0x00},
  46         {MAX98373_R0070_SCP_FRAME_CTLR, 0x00},
  47         {MAX98373_R0100_DP1_INIT_STAT, 0x00},
  48         {MAX98373_R0101_DP1_INIT_MASK, 0x00},
  49         {MAX98373_R0102_DP1_PORT_CTRL, 0x00},
  50         {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00},
  51         {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00},
  52         {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00},
  53         {MAX98373_R0120_DP1_CHANNEL_EN, 0x00},
  54         {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00},
  55         {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00},
  56         {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00},
  57         {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00},
  58         {MAX98373_R0126_DP1_HCTRL, 0x00},
  59         {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00},
  60         {MAX98373_R0130_DP1_CHANNEL_EN, 0x00},
  61         {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00},
  62         {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00},
  63         {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00},
  64         {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00},
  65         {MAX98373_R0136_DP1_HCTRL, 0x0136},
  66         {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00},
  67         {MAX98373_R0300_DP3_INIT_STAT, 0x00},
  68         {MAX98373_R0301_DP3_INIT_MASK, 0x00},
  69         {MAX98373_R0302_DP3_PORT_CTRL, 0x00},
  70         {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00},
  71         {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00},
  72         {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00},
  73         {MAX98373_R0320_DP3_CHANNEL_EN, 0x00},
  74         {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00},
  75         {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00},
  76         {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00},
  77         {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00},
  78         {MAX98373_R0326_DP3_HCTRL, 0x00},
  79         {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00},
  80         {MAX98373_R0330_DP3_CHANNEL_EN, 0x00},
  81         {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00},
  82         {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00},
  83         {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00},
  84         {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00},
  85         {MAX98373_R0336_DP3_HCTRL, 0x00},
  86         {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00},
  87         {MAX98373_R2000_SW_RESET, 0x00},
  88         {MAX98373_R2001_INT_RAW1, 0x00},
  89         {MAX98373_R2002_INT_RAW2, 0x00},
  90         {MAX98373_R2003_INT_RAW3, 0x00},
  91         {MAX98373_R2004_INT_STATE1, 0x00},
  92         {MAX98373_R2005_INT_STATE2, 0x00},
  93         {MAX98373_R2006_INT_STATE3, 0x00},
  94         {MAX98373_R2007_INT_FLAG1, 0x00},
  95         {MAX98373_R2008_INT_FLAG2, 0x00},
  96         {MAX98373_R2009_INT_FLAG3, 0x00},
  97         {MAX98373_R200A_INT_EN1, 0x00},
  98         {MAX98373_R200B_INT_EN2, 0x00},
  99         {MAX98373_R200C_INT_EN3, 0x00},
 100         {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
 101         {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
 102         {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
 103         {MAX98373_R2010_IRQ_CTRL, 0x00},
 104         {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
 105         {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
 106         {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
 107         {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
 108         {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
 109         {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
 110         {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
 111         {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
 112         {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
 113         {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
 114         {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
 115         {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
 116         {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
 117         {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
 118         {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
 119         {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
 120         {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
 121         {MAX98373_R202B_PCM_RX_EN, 0x00},
 122         {MAX98373_R202C_PCM_TX_EN, 0x00},
 123         {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
 124         {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
 125         {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
 126         {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
 127         {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
 128         {MAX98373_R2034_ICC_TX_CNTL, 0x00},
 129         {MAX98373_R2035_ICC_TX_EN, 0x00},
 130         {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
 131         {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
 132         {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
 133         {MAX98373_R203F_AMP_DSP_CFG, 0x02},
 134         {MAX98373_R2040_TONE_GEN_CFG, 0x00},
 135         {MAX98373_R2041_AMP_CFG, 0x03},
 136         {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
 137         {MAX98373_R2043_AMP_EN, 0x00},
 138         {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
 139         {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
 140         {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
 141         {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
 142         {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
 143         {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
 144         {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
 145         {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
 146         {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
 147         {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
 148         {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
 149         {MAX98373_R2097_BDE_L1_THRESH, 0x00},
 150         {MAX98373_R2098_BDE_L2_THRESH, 0x00},
 151         {MAX98373_R2099_BDE_L3_THRESH, 0x00},
 152         {MAX98373_R209A_BDE_L4_THRESH, 0x00},
 153         {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
 154         {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
 155         {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
 156         {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
 157         {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
 158         {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
 159         {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
 160         {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
 161         {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
 162         {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
 163         {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
 164         {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
 165         {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
 166         {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
 167         {MAX98373_R20B5_BDE_EN, 0x00},
 168         {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
 169         {MAX98373_R20D1_DHT_CFG, 0x01},
 170         {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
 171         {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
 172         {MAX98373_R20D4_DHT_EN, 0x00},
 173         {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
 174         {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
 175         {MAX98373_R20E2_LIMITER_EN, 0x00},
 176         {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
 177         {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
 178         {MAX98373_R21FF_REV_ID, 0x42},
 179 };
 180
 181 static bool max98373_readable_register(struct device *dev, unsigned int reg)
 182 {
 183         switch (reg) {
 184         case MAX98373_R21FF_REV_ID:
 185         case MAX98373_R2010_IRQ_CTRL:
 186         /* SoundWire Control Port Registers */
 187         case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
 188         /* Soundwire Data Port 1 Registers */
 189         case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
 190         /* Soundwire Data Port 3 Registers */
 191         case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
 192         case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3:
 193         case MAX98373_R2014_THERM_WARN_THRESH
 194                 ... MAX98373_R2018_THERM_FOLDBACK_EN:
 195         case MAX98373_R201E_PIN_DRIVE_STRENGTH
 196                 ... MAX98373_R2036_SOUNDWIRE_CTRL:
 197         case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
 198         case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
 199                 ... MAX98373_R2047_IV_SENSE_ADC_EN:
 200         case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
 201                 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
 202         case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
 203         case MAX98373_R2097_BDE_L1_THRESH
 204                 ... MAX98373_R209B_BDE_THRESH_HYST:
 205         case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
 206         case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 207         case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
 208         case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
 209         case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
 210                 ... MAX98373_R20FF_GLOBAL_SHDN:
 211                 return true;
 212         default:
 213                 return false;
 214         }
 215 };
 216
 217 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
 218 {
 219         switch (reg) {
 220         case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
 221         case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
 222         case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 223         case MAX98373_R20FF_GLOBAL_SHDN:
 224         case MAX98373_R21FF_REV_ID:
 225         /* SoundWire Control Port Registers */
 226         case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
 227         /* Soundwire Data Port 1 Registers */
 228         case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
 229         /* Soundwire Data Port 3 Registers */
 230         case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
 231         case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
 232                 return true;
 233         default:
 234                 return false;
 235         }
 236 }
 237
 238 static const struct regmap_config max98373_sdw_regmap = {
 239         .reg_bits = 32,
 240         .val_bits = 8,
 241         .max_register = MAX98373_R21FF_REV_ID,
 242         .reg_defaults  = max98373_reg,
 243         .num_reg_defaults = ARRAY_SIZE(max98373_reg),
 244         .readable_reg = max98373_readable_register,
 245         .volatile_reg = max98373_volatile_reg,
 246         .cache_type = REGCACHE_RBTREE,
 247         .use_single_read = true,
 248         .use_single_write = true,
 249 };
 250
 251 /* Power management functions and structure */
 252 static __maybe_unused int max98373_suspend(struct device *dev)
 253 {
 254         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 255         int i;
 256
 257         /* cache feedback register values before suspend */
 258         for (i = 0; i < max98373->cache_num; i++)
 259                 regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val);
 260
 261         regcache_cache_only(max98373->regmap, true);
 262
 263         return 0;
 264 }
 265
 266 #define MAX98373_PROBE_TIMEOUT 5000
 267
 268 static __maybe_unused int max98373_resume(struct device *dev)
 269 {
 270         struct sdw_slave *slave = dev_to_sdw_dev(dev);
 271         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 272         unsigned long time;
 273
 274         if (!max98373->first_hw_init)
 275                 return 0;
 276
 277         if (!slave->unattach_request)
 278                 goto regmap_sync;
 279
 280         time = wait_for_completion_timeout(&slave->initialization_complete,
 281                                            msecs_to_jiffies(MAX98373_PROBE_TIMEOUT));
 282         if (!time) {
 283                 dev_err(dev, "Initialization not complete, timed out\n");
 284                 sdw_show_ping_status(slave->bus, true);
 285
 286                 return -ETIMEDOUT;
 287         }
 288
 289 regmap_sync:
 290         slave->unattach_request = 0;
 291         regcache_cache_only(max98373->regmap, false);
 292         regcache_sync(max98373->regmap);
 293
 294         return 0;
 295 }
 296
 297 static const struct dev_pm_ops max98373_pm = {
 298         SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
 299         SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL)
 300 };
 301
 302 static int max98373_read_prop(struct sdw_slave *slave)
 303 {
 304         struct sdw_slave_prop *prop = &slave->prop;
 305         int nval, i;
 306         u32 bit;
 307         unsigned long addr;
 308         struct sdw_dpn_prop *dpn;
 309
 310         prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
 311
 312         /* BITMAP: 00001000  Dataport 3 is active */
 313         prop->source_ports = BIT(3);
 314         /* BITMAP: 00000010  Dataport 1 is active */
 315         prop->sink_ports = BIT(1);
 316         prop->paging_support = true;
 317         prop->clk_stop_timeout = 20;
 318
 319         nval = hweight32(prop->source_ports);
 320         prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
 321                                           sizeof(*prop->src_dpn_prop),
 322                                           GFP_KERNEL);
 323         if (!prop->src_dpn_prop)
 324                 return -ENOMEM;
 325
 326         i = 0;
 327         dpn = prop->src_dpn_prop;
 328         addr = prop->source_ports;
 329         for_each_set_bit(bit, &addr, 32) {
 330                 dpn[i].num = bit;
 331                 dpn[i].type = SDW_DPN_FULL;
 332                 dpn[i].simple_ch_prep_sm = true;
 333                 dpn[i].ch_prep_timeout = 10;
 334                 i++;
 335         }
 336
 337         /* do this again for sink now */
 338         nval = hweight32(prop->sink_ports);
 339         prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
 340                                            sizeof(*prop->sink_dpn_prop),
 341                                            GFP_KERNEL);
 342         if (!prop->sink_dpn_prop)
 343                 return -ENOMEM;
 344
 345         i = 0;
 346         dpn = prop->sink_dpn_prop;
 347         addr = prop->sink_ports;
 348         for_each_set_bit(bit, &addr, 32) {
 349                 dpn[i].num = bit;
 350                 dpn[i].type = SDW_DPN_FULL;
 351                 dpn[i].simple_ch_prep_sm = true;
 352                 dpn[i].ch_prep_timeout = 10;
 353                 i++;
 354         }
 355
 356         /* set the timeout values */
 357         prop->clk_stop_timeout = 20;
 358
 359         return 0;
 360 }
 361
 362 static int max98373_io_init(struct sdw_slave *slave)
 363 {
 364         struct device *dev = &slave->dev;
 365         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 366
 367         if (max98373->first_hw_init) {
 368                 regcache_cache_only(max98373->regmap, false);
 369                 regcache_cache_bypass(max98373->regmap, true);
 370         }
 371
 372         /*
 373          * PM runtime is only enabled when a Slave reports as Attached
 374          */
 375         if (!max98373->first_hw_init) {
 376                 /* set autosuspend parameters */
 377                 pm_runtime_set_autosuspend_delay(dev, 3000);
 378                 pm_runtime_use_autosuspend(dev);
 379
 380                 /* update count of parent 'active' children */
 381                 pm_runtime_set_active(dev);
 382
 383                 /* make sure the device does not suspend immediately */
 384                 pm_runtime_mark_last_busy(dev);
 385
 386                 pm_runtime_enable(dev);
 387         }
 388
 389         pm_runtime_get_noresume(dev);
 390
 391         /* Software Reset */
 392         max98373_reset(max98373, dev);
 393
 394         /* Set soundwire mode */
 395         regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3);
 396         /* Enable ADC */
 397         regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3);
 398         /* Set default Soundwire clock */
 399         regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5);
 400         /* Set default sampling rate for speaker and IVDAC */
 401         regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
 402         /* IV default slot configuration */
 403         regmap_write(max98373->regmap,
 404                      MAX98373_R2020_PCM_TX_HIZ_EN_1,
 405                      0xFF);
 406         regmap_write(max98373->regmap,
 407                      MAX98373_R2021_PCM_TX_HIZ_EN_2,
 408                      0xFF);
 409         /* L/R mix configuration */
 410         regmap_write(max98373->regmap,
 411                      MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 412                      0x80);
 413         regmap_write(max98373->regmap,
 414                      MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
 415                      0x1);
 416         /* Enable DC blocker */
 417         regmap_write(max98373->regmap,
 418                      MAX98373_R203F_AMP_DSP_CFG,
 419                      0x3);
 420         /* Enable IMON VMON DC blocker */
 421         regmap_write(max98373->regmap,
 422                      MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
 423                      0x7);
 424         /* voltage, current slot configuration */
 425         regmap_write(max98373->regmap,
 426                      MAX98373_R2022_PCM_TX_SRC_1,
 427                      (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
 428                      max98373->v_slot) & 0xFF);
 429         if (max98373->v_slot < 8)
 430                 regmap_update_bits(max98373->regmap,
 431                                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
 432                                    1 << max98373->v_slot, 0);
 433         else
 434                 regmap_update_bits(max98373->regmap,
 435                                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
 436                                    1 << (max98373->v_slot - 8), 0);
 437
 438         if (max98373->i_slot < 8)
 439                 regmap_update_bits(max98373->regmap,
 440                                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
 441                                    1 << max98373->i_slot, 0);
 442         else
 443                 regmap_update_bits(max98373->regmap,
 444                                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
 445                                    1 << (max98373->i_slot - 8), 0);
 446
 447         /* speaker feedback slot configuration */
 448         regmap_write(max98373->regmap,
 449                      MAX98373_R2023_PCM_TX_SRC_2,
 450                      max98373->spkfb_slot & 0xFF);
 451
 452         /* Set interleave mode */
 453         if (max98373->interleave_mode)
 454                 regmap_update_bits(max98373->regmap,
 455                                    MAX98373_R2024_PCM_DATA_FMT_CFG,
 456                                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
 457                                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
 458
 459         /* Speaker enable */
 460         regmap_update_bits(max98373->regmap,
 461                            MAX98373_R2043_AMP_EN,
 462                            MAX98373_SPK_EN_MASK, 1);
 463
 464         regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1);
 465         regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1);
 466
 467         if (max98373->first_hw_init) {
 468                 regcache_cache_bypass(max98373->regmap, false);
 469                 regcache_mark_dirty(max98373->regmap);
 470         }
 471
 472         max98373->first_hw_init = true;
 473         max98373->hw_init = true;
 474
 475         pm_runtime_mark_last_busy(dev);
 476         pm_runtime_put_autosuspend(dev);
 477
 478         return 0;
 479 }
 480
 481 static int max98373_clock_calculate(struct sdw_slave *slave,
 482                                     unsigned int clk_freq)
 483 {
 484         int x, y;
 485         static const int max98373_clk_family[] = {
 486                 7680000, 8400000, 9600000, 11289600,
 487                 12000000, 12288000, 13000000
 488         };
 489
 490         for (x = 0; x < 4; x++)
 491                 for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++)
 492                         if (clk_freq == (max98373_clk_family[y] >> x))
 493                                 return (x << 3) + y;
 494
 495         /* Set default clock (12.288 Mhz) if the value is not in the list */
 496         dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n",
 497                 clk_freq);
 498         return 0x5;
 499 }
 500
 501 static int max98373_clock_config(struct sdw_slave *slave,
 502                                  struct sdw_bus_params *params)
 503 {
 504         struct device *dev = &slave->dev;
 505         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 506         unsigned int clk_freq, value;
 507
 508         clk_freq = (params->curr_dr_freq >> 1);
 509
 510         /*
 511          *      Select the proper value for the register based on the
 512          *      requested clock. If the value is not in the list,
 513          *      use reasonable default - 12.288 Mhz
 514          */
 515         value = max98373_clock_calculate(slave, clk_freq);
 516
 517         /* SWCLK */
 518         regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value);
 519
 520         /* The default Sampling Rate value for IV is 48KHz*/
 521         regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
 522
 523         return 0;
 524 }
 525
 526 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
 527 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
 528
 529 static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream,
 530                                       struct snd_pcm_hw_params *params,
 531                                       struct snd_soc_dai *dai)
 532 {
 533         struct snd_soc_component *component = dai->component;
 534         struct max98373_priv *max98373 =
 535                 snd_soc_component_get_drvdata(component);
 536
 537         struct sdw_stream_config stream_config;
 538         struct sdw_port_config port_config;
 539         enum sdw_data_direction direction;
 540         struct sdw_stream_data *stream;
 541         int ret, chan_sz, sampling_rate;
 542
 543         stream = snd_soc_dai_get_dma_data(dai, substream);
 544
 545         if (!stream)
 546                 return -EINVAL;
 547
 548         if (!max98373->slave)
 549                 return -EINVAL;
 550
 551         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 552                 direction = SDW_DATA_DIR_RX;
 553                 port_config.num = 1;
 554         } else {
 555                 direction = SDW_DATA_DIR_TX;
 556                 port_config.num = 3;
 557         }
 558
 559         stream_config.frame_rate = params_rate(params);
 560         stream_config.bps = snd_pcm_format_width(params_format(params));
 561         stream_config.direction = direction;
 562
 563         if (max98373->slot && direction == SDW_DATA_DIR_RX) {
 564                 stream_config.ch_count = max98373->slot;
 565                 port_config.ch_mask = max98373->rx_mask;
 566         } else {
 567                 /* only IV are supported by capture */
 568                 if (direction == SDW_DATA_DIR_TX)
 569                         stream_config.ch_count = 2;
 570                 else
 571                         stream_config.ch_count = params_channels(params);
 572
 573                 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
 574         }
 575
 576         ret = sdw_stream_add_slave(max98373->slave, &stream_config,
 577                                    &port_config, 1, stream->sdw_stream);
 578         if (ret) {
 579                 dev_err(dai->dev, "Unable to configure port\n");
 580                 return ret;
 581         }
 582
 583         if (params_channels(params) > 16) {
 584                 dev_err(component->dev, "Unsupported channels %d\n",
 585                         params_channels(params));
 586                 return -EINVAL;
 587         }
 588
 589         /* Channel size configuration */
 590         switch (snd_pcm_format_width(params_format(params))) {
 591         case 16:
 592                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
 593                 break;
 594         case 24:
 595                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
 596                 break;
 597         case 32:
 598                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
 599                 break;
 600         default:
 601                 dev_err(component->dev, "Channel size unsupported %d\n",
 602                         params_format(params));
 603                 return -EINVAL;
 604         }
 605
 606         max98373->ch_size = snd_pcm_format_width(params_format(params));
 607
 608         regmap_update_bits(max98373->regmap,
 609                            MAX98373_R2024_PCM_DATA_FMT_CFG,
 610                            MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
 611
 612         dev_dbg(component->dev, "Format supported %d", params_format(params));
 613
 614         /* Sampling rate configuration */
 615         switch (params_rate(params)) {
 616         case 8000:
 617                 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
 618                 break;
 619         case 11025:
 620                 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
 621                 break;
 622         case 12000:
 623                 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
 624                 break;
 625         case 16000:
 626                 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
 627                 break;
 628         case 22050:
 629                 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
 630                 break;
 631         case 24000:
 632                 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
 633                 break;
 634         case 32000:
 635                 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
 636                 break;
 637         case 44100:
 638                 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
 639                 break;
 640         case 48000:
 641                 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
 642                 break;
 643         case 88200:
 644                 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
 645                 break;
 646         case 96000:
 647                 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
 648                 break;
 649         default:
 650                 dev_err(component->dev, "Rate %d is not supported\n",
 651                         params_rate(params));
 652                 return -EINVAL;
 653         }
 654
 655         /* set correct sampling frequency */
 656         regmap_update_bits(max98373->regmap,
 657                            MAX98373_R2028_PCM_SR_SETUP_2,
 658                            MAX98373_PCM_SR_SET2_SR_MASK,
 659                            sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
 660
 661         /* set sampling rate of IV */
 662         regmap_update_bits(max98373->regmap,
 663                            MAX98373_R2028_PCM_SR_SETUP_2,
 664                            MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
 665                            sampling_rate);
 666
 667         return 0;
 668 }
 669
 670 static int max98373_pcm_hw_free(struct snd_pcm_substream *substream,
 671                                 struct snd_soc_dai *dai)
 672 {
 673         struct snd_soc_component *component = dai->component;
 674         struct max98373_priv *max98373 =
 675                 snd_soc_component_get_drvdata(component);
 676         struct sdw_stream_data *stream =
 677                 snd_soc_dai_get_dma_data(dai, substream);
 678
 679         if (!max98373->slave)
 680                 return -EINVAL;
 681
 682         sdw_stream_remove_slave(max98373->slave, stream->sdw_stream);
 683         return 0;
 684 }
 685
 686 static int max98373_set_sdw_stream(struct snd_soc_dai *dai,
 687                                    void *sdw_stream, int direction)
 688 {
 689         struct sdw_stream_data *stream;
 690
 691         if (!sdw_stream)
 692                 return 0;
 693
 694         stream = kzalloc(sizeof(*stream), GFP_KERNEL);
 695         if (!stream)
 696                 return -ENOMEM;
 697
 698         stream->sdw_stream = sdw_stream;
 699
 700         /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
 701         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
 702                 dai->playback_dma_data = stream;
 703         else
 704                 dai->capture_dma_data = stream;
 705
 706         return 0;
 707 }
 708
 709 static void max98373_shutdown(struct snd_pcm_substream *substream,
 710                               struct snd_soc_dai *dai)
 711 {
 712         struct sdw_stream_data *stream;
 713
 714         stream = snd_soc_dai_get_dma_data(dai, substream);
 715         snd_soc_dai_set_dma_data(dai, substream, NULL);
 716         kfree(stream);
 717 }
 718
 719 static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai,
 720                                      unsigned int tx_mask,
 721                                      unsigned int rx_mask,
 722                                      int slots, int slot_width)
 723 {
 724         struct snd_soc_component *component = dai->component;
 725         struct max98373_priv *max98373 =
 726                 snd_soc_component_get_drvdata(component);
 727
 728         /* tx_mask is unused since it's irrelevant for I/V feedback */
 729         if (tx_mask)
 730                 return -EINVAL;
 731
 732         if (!rx_mask && !slots && !slot_width)
 733                 max98373->tdm_mode = false;
 734         else
 735                 max98373->tdm_mode = true;
 736
 737         max98373->rx_mask = rx_mask;
 738         max98373->slot = slots;
 739
 740         return 0;
 741 }
 742
 743 static const struct snd_soc_dai_ops max98373_dai_sdw_ops = {
 744         .hw_params = max98373_sdw_dai_hw_params,
 745         .hw_free = max98373_pcm_hw_free,
 746         .set_stream = max98373_set_sdw_stream,
 747         .shutdown = max98373_shutdown,
 748         .set_tdm_slot = max98373_sdw_set_tdm_slot,
 749 };
 750
 751 static struct snd_soc_dai_driver max98373_sdw_dai[] = {
 752         {
 753                 .name = "max98373-aif1",
 754                 .playback = {
 755                         .stream_name = "HiFi Playback",
 756                         .channels_min = 1,
 757                         .channels_max = 2,
 758                         .rates = MAX98373_RATES,
 759                         .formats = MAX98373_FORMATS,
 760                 },
 761                 .capture = {
 762                         .stream_name = "HiFi Capture",
 763                         .channels_min = 1,
 764                         .channels_max = 2,
 765                         .rates = MAX98373_RATES,
 766                         .formats = MAX98373_FORMATS,
 767                 },
 768                 .ops = &max98373_dai_sdw_ops,
 769         }
 770 };
 771
 772 static int max98373_init(struct sdw_slave *slave, struct regmap *regmap)
 773 {
 774         struct max98373_priv *max98373;
 775         int ret;
 776         int i;
 777         struct device *dev = &slave->dev;
 778
 779         /*  Allocate and assign private driver data structure  */
 780         max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL);
 781         if (!max98373)
 782                 return -ENOMEM;
 783
 784         dev_set_drvdata(dev, max98373);
 785         max98373->regmap = regmap;
 786         max98373->slave = slave;
 787
 788         max98373->cache_num = ARRAY_SIZE(max98373_sdw_cache_reg);
 789         max98373->cache = devm_kcalloc(dev, max98373->cache_num,
 790                                        sizeof(*max98373->cache),
 791                                        GFP_KERNEL);
 792         if (!max98373->cache)
 793                 return -ENOMEM;
 794
 795         for (i = 0; i < max98373->cache_num; i++)
 796                 max98373->cache[i].reg = max98373_sdw_cache_reg[i];
 797
 798         /* Read voltage and slot configuration */
 799         max98373_slot_config(dev, max98373);
 800
 801         max98373->hw_init = false;
 802         max98373->first_hw_init = false;
 803
 804         /* codec registration  */
 805         ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw,
 806                                               max98373_sdw_dai,
 807                                               ARRAY_SIZE(max98373_sdw_dai));
 808         if (ret < 0)
 809                 dev_err(dev, "Failed to register codec: %d\n", ret);
 810
 811         return ret;
 812 }
 813
 814 static int max98373_update_status(struct sdw_slave *slave,
 815                                   enum sdw_slave_status status)
 816 {
 817         struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
 818
 819         if (status == SDW_SLAVE_UNATTACHED)
 820                 max98373->hw_init = false;
 821
 822         /*
 823          * Perform initialization only if slave status is SDW_SLAVE_ATTACHED
 824          */
 825         if (max98373->hw_init || status != SDW_SLAVE_ATTACHED)
 826                 return 0;
 827
 828         /* perform I/O transfers required for Slave initialization */
 829         return max98373_io_init(slave);
 830 }
 831
 832 static int max98373_bus_config(struct sdw_slave *slave,
 833                                struct sdw_bus_params *params)
 834 {
 835         int ret;
 836
 837         ret = max98373_clock_config(slave, params);
 838         if (ret < 0)
 839                 dev_err(&slave->dev, "Invalid clk config");
 840
 841         return ret;
 842 }
 843
 844 /*
 845  * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
 846  * port_prep are not defined for now
 847  */
 848 static struct sdw_slave_ops max98373_slave_ops = {
 849         .read_prop = max98373_read_prop,
 850         .update_status = max98373_update_status,
 851         .bus_config = max98373_bus_config,
 852 };
 853
 854 static int max98373_sdw_probe(struct sdw_slave *slave,
 855                               const struct sdw_device_id *id)
 856 {
 857         struct regmap *regmap;
 858
 859         /* Regmap Initialization */
 860         regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap);
 861         if (IS_ERR(regmap))
 862                 return PTR_ERR(regmap);
 863
 864         return max98373_init(slave, regmap);
 865 }
 866
 867 static int max98373_sdw_remove(struct sdw_slave *slave)
 868 {
 869         struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
 870
 871         if (max98373->first_hw_init)
 872                 pm_runtime_disable(&slave->dev);
 873
 874         return 0;
 875 }
 876
 877 #if defined(CONFIG_OF)
 878 static const struct of_device_id max98373_of_match[] = {
 879         { .compatible = "maxim,max98373", },
 880         {},
 881 };
 882 MODULE_DEVICE_TABLE(of, max98373_of_match);
 883 #endif
 884
 885 #ifdef CONFIG_ACPI
 886 static const struct acpi_device_id max98373_acpi_match[] = {
 887         { "MX98373", 0 },
 888         {},
 889 };
 890 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
 891 #endif
 892
 893 static const struct sdw_device_id max98373_id[] = {
 894         SDW_SLAVE_ENTRY(0x019F, 0x8373, 0),
 895         {},
 896 };
 897 MODULE_DEVICE_TABLE(sdw, max98373_id);
 898
 899 static struct sdw_driver max98373_sdw_driver = {
 900         .driver = {
 901                 .name = "max98373",
 902                 .owner = THIS_MODULE,
 903                 .of_match_table = of_match_ptr(max98373_of_match),
 904                 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
 905                 .pm = &max98373_pm,
 906         },
 907         .probe = max98373_sdw_probe,
 908         .remove = max98373_sdw_remove,
 909         .ops = &max98373_slave_ops,
 910         .id_table = max98373_id,
 911 };
 912
 913 module_sdw_driver(max98373_sdw_driver);
 914
 915 MODULE_DESCRIPTION("ASoC MAX98373 driver SDW");
 916 MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>");
 917 MODULE_LICENSE("GPL v2");