codecs/cs35l41.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // cs35l41.c -- CS35l41 ALSA SoC audio driver
   4 //
   5 // Copyright 2017-2021 Cirrus Logic, Inc.
   6 //
   7 // Author: David Rhodes <david.rhodes@cirrus.com>
   8
   9 #include <linux/acpi.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/property.h>
  19 #include <sound/initval.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/soc.h>
  23 #include <sound/soc-dapm.h>
  24 #include <sound/tlv.h>
  25
  26 #include "cs35l41.h"
  27
  28 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = {
  29         "VA",
  30         "VP",
  31 };
  32
  33 struct cs35l41_pll_sysclk_config {
  34         int freq;
  35         int clk_cfg;
  36 };
  37
  38 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = {
  39         { 32768,        0x00 },
  40         { 8000,         0x01 },
  41         { 11025,        0x02 },
  42         { 12000,        0x03 },
  43         { 16000,        0x04 },
  44         { 22050,        0x05 },
  45         { 24000,        0x06 },
  46         { 32000,        0x07 },
  47         { 44100,        0x08 },
  48         { 48000,        0x09 },
  49         { 88200,        0x0A },
  50         { 96000,        0x0B },
  51         { 128000,       0x0C },
  52         { 176400,       0x0D },
  53         { 192000,       0x0E },
  54         { 256000,       0x0F },
  55         { 352800,       0x10 },
  56         { 384000,       0x11 },
  57         { 512000,       0x12 },
  58         { 705600,       0x13 },
  59         { 750000,       0x14 },
  60         { 768000,       0x15 },
  61         { 1000000,      0x16 },
  62         { 1024000,      0x17 },
  63         { 1200000,      0x18 },
  64         { 1411200,      0x19 },
  65         { 1500000,      0x1A },
  66         { 1536000,      0x1B },
  67         { 2000000,      0x1C },
  68         { 2048000,      0x1D },
  69         { 2400000,      0x1E },
  70         { 2822400,      0x1F },
  71         { 3000000,      0x20 },
  72         { 3072000,      0x21 },
  73         { 3200000,      0x22 },
  74         { 4000000,      0x23 },
  75         { 4096000,      0x24 },
  76         { 4800000,      0x25 },
  77         { 5644800,      0x26 },
  78         { 6000000,      0x27 },
  79         { 6144000,      0x28 },
  80         { 6250000,      0x29 },
  81         { 6400000,      0x2A },
  82         { 6500000,      0x2B },
  83         { 6750000,      0x2C },
  84         { 7526400,      0x2D },
  85         { 8000000,      0x2E },
  86         { 8192000,      0x2F },
  87         { 9600000,      0x30 },
  88         { 11289600,     0x31 },
  89         { 12000000,     0x32 },
  90         { 12288000,     0x33 },
  91         { 12500000,     0x34 },
  92         { 12800000,     0x35 },
  93         { 13000000,     0x36 },
  94         { 13500000,     0x37 },
  95         { 19200000,     0x38 },
  96         { 22579200,     0x39 },
  97         { 24000000,     0x3A },
  98         { 24576000,     0x3B },
  99         { 25000000,     0x3C },
 100         { 25600000,     0x3D },
 101         { 26000000,     0x3E },
 102         { 27000000,     0x3F },
 103 };
 104
 105 struct cs35l41_fs_mon_config {
 106         int freq;
 107         unsigned int fs1;
 108         unsigned int fs2;
 109 };
 110
 111 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = {
 112         { 32768,        2254,   3754 },
 113         { 8000,         9220,   15364 },
 114         { 11025,        6148,   10244 },
 115         { 12000,        6148,   10244 },
 116         { 16000,        4612,   7684 },
 117         { 22050,        3076,   5124 },
 118         { 24000,        3076,   5124 },
 119         { 32000,        2308,   3844 },
 120         { 44100,        1540,   2564 },
 121         { 48000,        1540,   2564 },
 122         { 88200,        772,    1284 },
 123         { 96000,        772,    1284 },
 124         { 128000,       580,    964 },
 125         { 176400,       388,    644 },
 126         { 192000,       388,    644 },
 127         { 256000,       292,    484 },
 128         { 352800,       196,    324 },
 129         { 384000,       196,    324 },
 130         { 512000,       148,    244 },
 131         { 705600,       100,    164 },
 132         { 750000,       100,    164 },
 133         { 768000,       100,    164 },
 134         { 1000000,      76,     124 },
 135         { 1024000,      76,     124 },
 136         { 1200000,      64,     104 },
 137         { 1411200,      52,     84 },
 138         { 1500000,      52,     84 },
 139         { 1536000,      52,     84 },
 140         { 2000000,      40,     64 },
 141         { 2048000,      40,     64 },
 142         { 2400000,      34,     54 },
 143         { 2822400,      28,     44 },
 144         { 3000000,      28,     44 },
 145         { 3072000,      28,     44 },
 146         { 3200000,      27,     42 },
 147         { 4000000,      22,     34 },
 148         { 4096000,      22,     34 },
 149         { 4800000,      19,     29 },
 150         { 5644800,      16,     24 },
 151         { 6000000,      16,     24 },
 152         { 6144000,      16,     24 },
 153 };
 154
 155 static int cs35l41_get_fs_mon_config_index(int freq)
 156 {
 157         int i;
 158
 159         for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) {
 160                 if (cs35l41_fs_mon[i].freq == freq)
 161                         return i;
 162         }
 163
 164         return -EINVAL;
 165 }
 166
 167 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv,
 168                 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
 169                 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200));
 170 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 50, 100, 0);
 171
 172 static const struct snd_kcontrol_new dre_ctrl =
 173         SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0);
 174
 175 static const char * const cs35l41_pcm_sftramp_text[] =  {
 176         "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"
 177 };
 178
 179 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp,
 180                             CS35L41_AMP_DIG_VOL_CTRL, 0,
 181                             cs35l41_pcm_sftramp_text);
 182
 183 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w,
 184                                   struct snd_kcontrol *kcontrol, int event)
 185 {
 186         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 187         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 188         int ret;
 189
 190         switch (event) {
 191         case SND_SOC_DAPM_PRE_PMU:
 192                 if (cs35l41->dsp.cs_dsp.booted)
 193                         return 0;
 194
 195                 return wm_adsp_early_event(w, kcontrol, event);
 196         case SND_SOC_DAPM_PRE_PMD:
 197                 if (cs35l41->dsp.preloaded)
 198                         return 0;
 199
 200                 if (cs35l41->dsp.cs_dsp.running) {
 201                         ret = wm_adsp_event(w, kcontrol, event);
 202                         if (ret)
 203                                 return ret;
 204                 }
 205
 206                 return wm_adsp_early_event(w, kcontrol, event);
 207         default:
 208                 return 0;
 209         }
 210 }
 211
 212 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w,
 213                                 struct snd_kcontrol *kcontrol, int event)
 214 {
 215         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 216         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 217         unsigned int fw_status;
 218         int ret;
 219
 220         switch (event) {
 221         case SND_SOC_DAPM_POST_PMU:
 222                 if (!cs35l41->dsp.cs_dsp.running)
 223                         return wm_adsp_event(w, kcontrol, event);
 224
 225                 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status);
 226                 if (ret < 0) {
 227                         dev_err(cs35l41->dev,
 228                                 "Failed to read firmware status: %d\n", ret);
 229                         return ret;
 230                 }
 231
 232                 switch (fw_status) {
 233                 case CSPL_MBOX_STS_RUNNING:
 234                 case CSPL_MBOX_STS_PAUSED:
 235                         break;
 236                 default:
 237                         dev_err(cs35l41->dev, "Firmware status is invalid: %u\n",
 238                                 fw_status);
 239                         return -EINVAL;
 240                 }
 241
 242                 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
 243                                                  CSPL_MBOX_CMD_RESUME);
 244         case SND_SOC_DAPM_PRE_PMD:
 245                 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
 246                                                  CSPL_MBOX_CMD_PAUSE);
 247         default:
 248                 return 0;
 249         }
 250 }
 251
 252 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"};
 253 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32};
 254 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum,
 255                                   CS35L41_DAC_PCM1_SRC,
 256                                   0, CS35L41_ASP_SOURCE_MASK,
 257                                   cs35l41_pcm_source_texts,
 258                                   cs35l41_pcm_source_values);
 259
 260 static const struct snd_kcontrol_new pcm_source_mux =
 261         SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum);
 262
 263 static const char * const cs35l41_tx_input_texts[] = {
 264         "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON",
 265         "VPMON", "VBSTMON", "DSPTX1", "DSPTX2"
 266 };
 267
 268 static const unsigned int cs35l41_tx_input_values[] = {
 269         0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2,
 270         CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON,
 271         CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2
 272 };
 273
 274 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum,
 275                                   CS35L41_ASP_TX1_SRC,
 276                                   0, CS35L41_ASP_SOURCE_MASK,
 277                                   cs35l41_tx_input_texts,
 278                                   cs35l41_tx_input_values);
 279
 280 static const struct snd_kcontrol_new asp_tx1_mux =
 281         SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum);
 282
 283 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum,
 284                                   CS35L41_ASP_TX2_SRC,
 285                                   0, CS35L41_ASP_SOURCE_MASK,
 286                                   cs35l41_tx_input_texts,
 287                                   cs35l41_tx_input_values);
 288
 289 static const struct snd_kcontrol_new asp_tx2_mux =
 290         SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum);
 291
 292 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum,
 293                                   CS35L41_ASP_TX3_SRC,
 294                                   0, CS35L41_ASP_SOURCE_MASK,
 295                                   cs35l41_tx_input_texts,
 296                                   cs35l41_tx_input_values);
 297
 298 static const struct snd_kcontrol_new asp_tx3_mux =
 299         SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum);
 300
 301 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum,
 302                                   CS35L41_ASP_TX4_SRC,
 303                                   0, CS35L41_ASP_SOURCE_MASK,
 304                                   cs35l41_tx_input_texts,
 305                                   cs35l41_tx_input_values);
 306
 307 static const struct snd_kcontrol_new asp_tx4_mux =
 308         SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum);
 309
 310 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum,
 311                                   CS35L41_DSP1_RX1_SRC,
 312                                   0, CS35L41_ASP_SOURCE_MASK,
 313                                   cs35l41_tx_input_texts,
 314                                   cs35l41_tx_input_values);
 315
 316 static const struct snd_kcontrol_new dsp_rx1_mux =
 317         SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum);
 318
 319 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum,
 320                                   CS35L41_DSP1_RX2_SRC,
 321                                   0, CS35L41_ASP_SOURCE_MASK,
 322                                   cs35l41_tx_input_texts,
 323                                   cs35l41_tx_input_values);
 324
 325 static const struct snd_kcontrol_new dsp_rx2_mux =
 326         SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum);
 327
 328 static const struct snd_kcontrol_new cs35l41_aud_controls[] = {
 329         SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL,
 330                           3, 0x4CF, 0x391, dig_vol_tlv),
 331         SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0,
 332                        amp_gain_tlv),
 333         SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
 334         SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0),
 335         SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0),
 336         SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0),
 337         SOC_SINGLE("Aux Noise Gate CH1 Switch",
 338                    CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0),
 339         SOC_SINGLE("Aux Noise Gate CH1 Entry Delay",
 340                    CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0),
 341         SOC_SINGLE("Aux Noise Gate CH1 Threshold",
 342                    CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0),
 343         SOC_SINGLE("Aux Noise Gate CH2 Entry Delay",
 344                    CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0),
 345         SOC_SINGLE("Aux Noise Gate CH2 Switch",
 346                    CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0),
 347         SOC_SINGLE("Aux Noise Gate CH2 Threshold",
 348                    CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0),
 349         SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0),
 350         SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0),
 351         SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL,
 352                    CS35L41_AMP_INV_PCM_SHIFT, 1, 0),
 353         SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL,
 354                    CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0),
 355         WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
 356         WM_ADSP_FW_CONTROL("DSP1", 0),
 357 };
 358
 359 static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable)
 360 {
 361         switch (cs35l41->hw_cfg.bst_type) {
 362         case CS35L41_INT_BOOST:
 363                 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF;
 364                 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
 365                                 enable << CS35L41_BST_EN_SHIFT);
 366                 break;
 367         default:
 368                 break;
 369         }
 370 }
 371
 372 static irqreturn_t cs35l41_irq(int irq, void *data)
 373 {
 374         struct cs35l41_private *cs35l41 = data;
 375         unsigned int status[4] = { 0, 0, 0, 0 };
 376         unsigned int masks[4] = { 0, 0, 0, 0 };
 377         unsigned int i;
 378         int ret;
 379
 380         ret = pm_runtime_resume_and_get(cs35l41->dev);
 381         if (ret < 0) {
 382                 dev_err(cs35l41->dev,
 383                         "pm_runtime_resume_and_get failed in %s: %d\n",
 384                         __func__, ret);
 385                 return IRQ_NONE;
 386         }
 387
 388         ret = IRQ_NONE;
 389
 390         for (i = 0; i < ARRAY_SIZE(status); i++) {
 391                 regmap_read(cs35l41->regmap,
 392                             CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE),
 393                             &status[i]);
 394                 regmap_read(cs35l41->regmap,
 395                             CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE),
 396                             &masks[i]);
 397         }
 398
 399         /* Check to see if unmasked bits are active */
 400         if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
 401             !(status[2] & ~masks[2]) && !(status[3] & ~masks[3]))
 402                 goto done;
 403
 404         if (status[3] & CS35L41_OTP_BOOT_DONE) {
 405                 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4,
 406                                    CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE);
 407         }
 408
 409         /*
 410          * The following interrupts require a
 411          * protection release cycle to get the
 412          * speaker out of Safe-Mode.
 413          */
 414         if (status[0] & CS35L41_AMP_SHORT_ERR) {
 415                 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n");
 416                 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
 417                              CS35L41_AMP_SHORT_ERR);
 418                 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
 419                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 420                                    CS35L41_AMP_SHORT_ERR_RLS,
 421                                    CS35L41_AMP_SHORT_ERR_RLS);
 422                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 423                                    CS35L41_AMP_SHORT_ERR_RLS, 0);
 424                 ret = IRQ_HANDLED;
 425         }
 426
 427         if (status[0] & CS35L41_TEMP_WARN) {
 428                 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n");
 429                 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
 430                              CS35L41_TEMP_WARN);
 431                 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
 432                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 433                                    CS35L41_TEMP_WARN_ERR_RLS,
 434                                    CS35L41_TEMP_WARN_ERR_RLS);
 435                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 436                                    CS35L41_TEMP_WARN_ERR_RLS, 0);
 437                 ret = IRQ_HANDLED;
 438         }
 439
 440         if (status[0] & CS35L41_TEMP_ERR) {
 441                 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n");
 442                 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
 443                              CS35L41_TEMP_ERR);
 444                 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
 445                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 446                                    CS35L41_TEMP_ERR_RLS,
 447                                    CS35L41_TEMP_ERR_RLS);
 448                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 449                                    CS35L41_TEMP_ERR_RLS, 0);
 450                 ret = IRQ_HANDLED;
 451         }
 452
 453         if (status[0] & CS35L41_BST_OVP_ERR) {
 454                 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n");
 455                 cs35l41_boost_enable(cs35l41, 0);
 456                 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
 457                              CS35L41_BST_OVP_ERR);
 458                 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
 459                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 460                                    CS35L41_BST_OVP_ERR_RLS,
 461                                    CS35L41_BST_OVP_ERR_RLS);
 462                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 463                                    CS35L41_BST_OVP_ERR_RLS, 0);
 464                 cs35l41_boost_enable(cs35l41, 1);
 465                 ret = IRQ_HANDLED;
 466         }
 467
 468         if (status[0] & CS35L41_BST_DCM_UVP_ERR) {
 469                 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n");
 470                 cs35l41_boost_enable(cs35l41, 0);
 471                 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
 472                              CS35L41_BST_DCM_UVP_ERR);
 473                 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
 474                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 475                                    CS35L41_BST_UVP_ERR_RLS,
 476                                    CS35L41_BST_UVP_ERR_RLS);
 477                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 478                                    CS35L41_BST_UVP_ERR_RLS, 0);
 479                 cs35l41_boost_enable(cs35l41, 1);
 480                 ret = IRQ_HANDLED;
 481         }
 482
 483         if (status[0] & CS35L41_BST_SHORT_ERR) {
 484                 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n");
 485                 cs35l41_boost_enable(cs35l41, 0);
 486                 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
 487                              CS35L41_BST_SHORT_ERR);
 488                 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
 489                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 490                                    CS35L41_BST_SHORT_ERR_RLS,
 491                                    CS35L41_BST_SHORT_ERR_RLS);
 492                 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN,
 493                                    CS35L41_BST_SHORT_ERR_RLS, 0);
 494                 cs35l41_boost_enable(cs35l41, 1);
 495                 ret = IRQ_HANDLED;
 496         }
 497
 498 done:
 499         pm_runtime_mark_last_busy(cs35l41->dev);
 500         pm_runtime_put_autosuspend(cs35l41->dev);
 501
 502         return ret;
 503 }
 504
 505 static const struct reg_sequence cs35l41_pup_patch[] = {
 506         { CS35L41_TEST_KEY_CTL, 0x00000055 },
 507         { CS35L41_TEST_KEY_CTL, 0x000000AA },
 508         { 0x00002084, 0x002F1AA0 },
 509         { CS35L41_TEST_KEY_CTL, 0x000000CC },
 510         { CS35L41_TEST_KEY_CTL, 0x00000033 },
 511 };
 512
 513 static const struct reg_sequence cs35l41_pdn_patch[] = {
 514         { CS35L41_TEST_KEY_CTL, 0x00000055 },
 515         { CS35L41_TEST_KEY_CTL, 0x000000AA },
 516         { 0x00002084, 0x002F1AA3 },
 517         { CS35L41_TEST_KEY_CTL, 0x000000CC },
 518         { CS35L41_TEST_KEY_CTL, 0x00000033 },
 519 };
 520
 521 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w,
 522                                   struct snd_kcontrol *kcontrol, int event)
 523 {
 524         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 525         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 526         unsigned int val;
 527         int ret = 0;
 528
 529         switch (event) {
 530         case SND_SOC_DAPM_PRE_PMU:
 531                 regmap_multi_reg_write_bypassed(cs35l41->regmap,
 532                                                 cs35l41_pup_patch,
 533                                                 ARRAY_SIZE(cs35l41_pup_patch));
 534
 535                 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 1);
 536                 break;
 537         case SND_SOC_DAPM_POST_PMD:
 538                 cs35l41_global_enable(cs35l41->regmap, cs35l41->hw_cfg.bst_type, 0);
 539
 540                 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
 541                                                val, val &  CS35L41_PDN_DONE_MASK,
 542                                                1000, 100000);
 543                 if (ret)
 544                         dev_warn(cs35l41->dev, "PDN failed: %d\n", ret);
 545
 546                 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1,
 547                              CS35L41_PDN_DONE_MASK);
 548
 549                 regmap_multi_reg_write_bypassed(cs35l41->regmap,
 550                                                 cs35l41_pdn_patch,
 551                                                 ARRAY_SIZE(cs35l41_pdn_patch));
 552                 break;
 553         default:
 554                 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event);
 555                 ret = -EINVAL;
 556         }
 557
 558         return ret;
 559 }
 560
 561 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = {
 562         SND_SOC_DAPM_SPK("DSP1 Preload", NULL),
 563         SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0,
 564                               cs35l41_dsp_preload_ev,
 565                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
 566         SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0,
 567                                cs35l41_dsp_audio_ev,
 568                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 569
 570         SND_SOC_DAPM_OUTPUT("SPK"),
 571
 572         SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0),
 573         SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0),
 574         SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0),
 575         SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0),
 576         SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0),
 577         SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0),
 578
 579         SND_SOC_DAPM_SIGGEN("VSENSE"),
 580         SND_SOC_DAPM_SIGGEN("ISENSE"),
 581         SND_SOC_DAPM_SIGGEN("VP"),
 582         SND_SOC_DAPM_SIGGEN("VBST"),
 583         SND_SOC_DAPM_SIGGEN("TEMP"),
 584
 585         SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0),
 586         SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0),
 587         SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0),
 588         SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0),
 589         SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0),
 590
 591         SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 592         SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 593         SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 594         SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 595         SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
 596
 597         SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0),
 598
 599         SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0,
 600                                cs35l41_main_amp_event,
 601                                SND_SOC_DAPM_POST_PMD |  SND_SOC_DAPM_PRE_PMU),
 602
 603         SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux),
 604         SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux),
 605         SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux),
 606         SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux),
 607         SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux),
 608         SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux),
 609         SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux),
 610         SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl),
 611 };
 612
 613 static const struct snd_soc_dapm_route cs35l41_audio_map[] = {
 614         {"DSP RX1 Source", "ASPRX1", "ASPRX1"},
 615         {"DSP RX1 Source", "ASPRX2", "ASPRX2"},
 616         {"DSP RX2 Source", "ASPRX1", "ASPRX1"},
 617         {"DSP RX2 Source", "ASPRX2", "ASPRX2"},
 618
 619         {"DSP1", NULL, "DSP RX1 Source"},
 620         {"DSP1", NULL, "DSP RX2 Source"},
 621
 622         {"ASP TX1 Source", "VMON", "VMON ADC"},
 623         {"ASP TX1 Source", "IMON", "IMON ADC"},
 624         {"ASP TX1 Source", "VPMON", "VPMON ADC"},
 625         {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"},
 626         {"ASP TX1 Source", "DSPTX1", "DSP1"},
 627         {"ASP TX1 Source", "DSPTX2", "DSP1"},
 628         {"ASP TX1 Source", "ASPRX1", "ASPRX1" },
 629         {"ASP TX1 Source", "ASPRX2", "ASPRX2" },
 630         {"ASP TX2 Source", "VMON", "VMON ADC"},
 631         {"ASP TX2 Source", "IMON", "IMON ADC"},
 632         {"ASP TX2 Source", "VPMON", "VPMON ADC"},
 633         {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"},
 634         {"ASP TX2 Source", "DSPTX1", "DSP1"},
 635         {"ASP TX2 Source", "DSPTX2", "DSP1"},
 636         {"ASP TX2 Source", "ASPRX1", "ASPRX1" },
 637         {"ASP TX2 Source", "ASPRX2", "ASPRX2" },
 638         {"ASP TX3 Source", "VMON", "VMON ADC"},
 639         {"ASP TX3 Source", "IMON", "IMON ADC"},
 640         {"ASP TX3 Source", "VPMON", "VPMON ADC"},
 641         {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"},
 642         {"ASP TX3 Source", "DSPTX1", "DSP1"},
 643         {"ASP TX3 Source", "DSPTX2", "DSP1"},
 644         {"ASP TX3 Source", "ASPRX1", "ASPRX1" },
 645         {"ASP TX3 Source", "ASPRX2", "ASPRX2" },
 646         {"ASP TX4 Source", "VMON", "VMON ADC"},
 647         {"ASP TX4 Source", "IMON", "IMON ADC"},
 648         {"ASP TX4 Source", "VPMON", "VPMON ADC"},
 649         {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"},
 650         {"ASP TX4 Source", "DSPTX1", "DSP1"},
 651         {"ASP TX4 Source", "DSPTX2", "DSP1"},
 652         {"ASP TX4 Source", "ASPRX1", "ASPRX1" },
 653         {"ASP TX4 Source", "ASPRX2", "ASPRX2" },
 654         {"ASPTX1", NULL, "ASP TX1 Source"},
 655         {"ASPTX2", NULL, "ASP TX2 Source"},
 656         {"ASPTX3", NULL, "ASP TX3 Source"},
 657         {"ASPTX4", NULL, "ASP TX4 Source"},
 658         {"AMP Capture", NULL, "ASPTX1"},
 659         {"AMP Capture", NULL, "ASPTX2"},
 660         {"AMP Capture", NULL, "ASPTX3"},
 661         {"AMP Capture", NULL, "ASPTX4"},
 662
 663         {"DSP1", NULL, "VMON"},
 664         {"DSP1", NULL, "IMON"},
 665         {"DSP1", NULL, "VPMON"},
 666         {"DSP1", NULL, "VBSTMON"},
 667         {"DSP1", NULL, "TEMPMON"},
 668
 669         {"VMON ADC", NULL, "VMON"},
 670         {"IMON ADC", NULL, "IMON"},
 671         {"VPMON ADC", NULL, "VPMON"},
 672         {"VBSTMON ADC", NULL, "VBSTMON"},
 673         {"TEMPMON ADC", NULL, "TEMPMON"},
 674
 675         {"VMON ADC", NULL, "VSENSE"},
 676         {"IMON ADC", NULL, "ISENSE"},
 677         {"VPMON ADC", NULL, "VP"},
 678         {"VBSTMON ADC", NULL, "VBST"},
 679         {"TEMPMON ADC", NULL, "TEMP"},
 680
 681         {"DSP1 Preload", NULL, "DSP1 Preloader"},
 682         {"DSP1", NULL, "DSP1 Preloader"},
 683
 684         {"ASPRX1", NULL, "AMP Playback"},
 685         {"ASPRX2", NULL, "AMP Playback"},
 686         {"DRE", "Switch", "CLASS H"},
 687         {"Main AMP", NULL, "CLASS H"},
 688         {"Main AMP", NULL, "DRE"},
 689         {"SPK", NULL, "Main AMP"},
 690
 691         {"PCM Source", "ASP", "ASPRX1"},
 692         {"PCM Source", "DSP", "DSP1"},
 693         {"CLASS H", NULL, "PCM Source"},
 694 };
 695
 696 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n,
 697                                    unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot)
 698 {
 699         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
 700
 701         return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot);
 702 }
 703
 704 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 705 {
 706         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
 707         unsigned int daifmt = 0;
 708
 709         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 710         case SND_SOC_DAIFMT_CBP_CFP:
 711                 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK;
 712                 break;
 713         case SND_SOC_DAIFMT_CBC_CFC:
 714                 break;
 715         default:
 716                 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n");
 717                 return -EINVAL;
 718         }
 719
 720         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 721         case SND_SOC_DAIFMT_DSP_A:
 722                 break;
 723         case SND_SOC_DAIFMT_I2S:
 724                 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT;
 725                 break;
 726         default:
 727                 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n");
 728                 return -EINVAL;
 729         }
 730
 731         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 732         case SND_SOC_DAIFMT_NB_IF:
 733                 daifmt |= CS35L41_LRCLK_INV_MASK;
 734                 break;
 735         case SND_SOC_DAIFMT_IB_NF:
 736                 daifmt |= CS35L41_SCLK_INV_MASK;
 737                 break;
 738         case SND_SOC_DAIFMT_IB_IF:
 739                 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK;
 740                 break;
 741         case SND_SOC_DAIFMT_NB_NF:
 742                 break;
 743         default:
 744                 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n");
 745                 return -EINVAL;
 746         }
 747
 748         return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
 749                                   CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK |
 750                                   CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK |
 751                                   CS35L41_SCLK_INV_MASK, daifmt);
 752 }
 753
 754 struct cs35l41_global_fs_config {
 755         int rate;
 756         int fs_cfg;
 757 };
 758
 759 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = {
 760         { 12000,        0x01 },
 761         { 24000,        0x02 },
 762         { 48000,        0x03 },
 763         { 96000,        0x04 },
 764         { 192000,       0x05 },
 765         { 11025,        0x09 },
 766         { 22050,        0x0A },
 767         { 44100,        0x0B },
 768         { 88200,        0x0C },
 769         { 176400,       0x0D },
 770         { 8000,         0x11 },
 771         { 16000,        0x12 },
 772         { 32000,        0x13 },
 773 };
 774
 775 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream,
 776                                  struct snd_pcm_hw_params *params,
 777                                  struct snd_soc_dai *dai)
 778 {
 779         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
 780         unsigned int rate = params_rate(params);
 781         u8 asp_wl;
 782         int i;
 783
 784         for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) {
 785                 if (rate == cs35l41_fs_rates[i].rate)
 786                         break;
 787         }
 788
 789         if (i >= ARRAY_SIZE(cs35l41_fs_rates)) {
 790                 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate);
 791                 return -EINVAL;
 792         }
 793
 794         asp_wl = params_width(params);
 795
 796         if (i < ARRAY_SIZE(cs35l41_fs_rates))
 797                 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL,
 798                                    CS35L41_GLOBAL_FS_MASK,
 799                                    cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT);
 800
 801         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 802                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
 803                                    CS35L41_ASP_WIDTH_RX_MASK,
 804                                    asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT);
 805                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL,
 806                                    CS35L41_ASP_RX_WL_MASK,
 807                                    asp_wl << CS35L41_ASP_RX_WL_SHIFT);
 808         } else {
 809                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
 810                                    CS35L41_ASP_WIDTH_TX_MASK,
 811                                    asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT);
 812                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL,
 813                                    CS35L41_ASP_TX_WL_MASK,
 814                                    asp_wl << CS35L41_ASP_TX_WL_SHIFT);
 815         }
 816
 817         return 0;
 818 }
 819
 820 static int cs35l41_get_clk_config(int freq)
 821 {
 822         int i;
 823
 824         for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) {
 825                 if (cs35l41_pll_sysclk[i].freq == freq)
 826                         return cs35l41_pll_sysclk[i].clk_cfg;
 827         }
 828
 829         return -EINVAL;
 830 }
 831
 832 static const unsigned int cs35l41_src_rates[] = {
 833         8000, 12000, 11025, 16000, 22050, 24000, 32000,
 834         44100, 48000, 88200, 96000, 176400, 192000
 835 };
 836
 837 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = {
 838         .count = ARRAY_SIZE(cs35l41_src_rates),
 839         .list = cs35l41_src_rates,
 840 };
 841
 842 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream,
 843                                struct snd_soc_dai *dai)
 844 {
 845         if (substream->runtime)
 846                 return snd_pcm_hw_constraint_list(substream->runtime, 0,
 847                                                   SNDRV_PCM_HW_PARAM_RATE,
 848                                                   &cs35l41_constraints);
 849         return 0;
 850 }
 851
 852 static int cs35l41_component_set_sysclk(struct snd_soc_component *component,
 853                                         int clk_id, int source,
 854                                         unsigned int freq, int dir)
 855 {
 856         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 857         int extclk_cfg, clksrc;
 858
 859         switch (clk_id) {
 860         case CS35L41_CLKID_SCLK:
 861                 clksrc = CS35L41_PLLSRC_SCLK;
 862                 break;
 863         case CS35L41_CLKID_LRCLK:
 864                 clksrc = CS35L41_PLLSRC_LRCLK;
 865                 break;
 866         case CS35L41_CLKID_MCLK:
 867                 clksrc = CS35L41_PLLSRC_MCLK;
 868                 break;
 869         default:
 870                 dev_err(cs35l41->dev, "Invalid CLK Config\n");
 871                 return -EINVAL;
 872         }
 873
 874         extclk_cfg = cs35l41_get_clk_config(freq);
 875
 876         if (extclk_cfg < 0) {
 877                 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n",
 878                         extclk_cfg, freq);
 879                 return -EINVAL;
 880         }
 881
 882         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 883                            CS35L41_PLL_OPENLOOP_MASK,
 884                            1 << CS35L41_PLL_OPENLOOP_SHIFT);
 885         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 886                            CS35L41_REFCLK_FREQ_MASK,
 887                            extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT);
 888         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 889                            CS35L41_PLL_CLK_EN_MASK,
 890                            0 << CS35L41_PLL_CLK_EN_SHIFT);
 891         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 892                            CS35L41_PLL_CLK_SEL_MASK, clksrc);
 893         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 894                            CS35L41_PLL_OPENLOOP_MASK,
 895                            0 << CS35L41_PLL_OPENLOOP_SHIFT);
 896         regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
 897                            CS35L41_PLL_CLK_EN_MASK,
 898                            1 << CS35L41_PLL_CLK_EN_SHIFT);
 899
 900         return 0;
 901 }
 902
 903 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai,
 904                                   int clk_id, unsigned int freq, int dir)
 905 {
 906         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
 907         unsigned int fs1_val;
 908         unsigned int fs2_val;
 909         unsigned int val;
 910         int fsindex;
 911
 912         fsindex = cs35l41_get_fs_mon_config_index(freq);
 913         if (fsindex < 0) {
 914                 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq);
 915                 return -EINVAL;
 916         }
 917
 918         dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq);
 919
 920         if (freq <= 6144000) {
 921                 /* Use the lookup table */
 922                 fs1_val = cs35l41_fs_mon[fsindex].fs1;
 923                 fs2_val = cs35l41_fs_mon[fsindex].fs2;
 924         } else {
 925                 /* Use hard-coded values */
 926                 fs1_val = 0x10;
 927                 fs2_val = 0x24;
 928         }
 929
 930         val = fs1_val;
 931         val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK;
 932         regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val);
 933
 934         return 0;
 935 }
 936
 937 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41)
 938 {
 939         struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;
 940         int ret;
 941
 942         if (!hw_cfg->valid)
 943                 return -EINVAL;
 944
 945         if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH)
 946                 return -EINVAL;
 947
 948         /* Required */
 949         ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg);
 950         if (ret)
 951                 return ret;
 952
 953         /* Optional */
 954         if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0)
 955                 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK,
 956                                    hw_cfg->dout_hiz);
 957
 958         return 0;
 959 }
 960
 961 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = {
 962         {"Main AMP", NULL, "VSPK"},
 963 };
 964
 965 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = {
 966         SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0),
 967 };
 968
 969 static int cs35l41_component_probe(struct snd_soc_component *component)
 970 {
 971         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 972         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 973         int ret;
 974
 975         if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) {
 976                 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget,
 977                                                 ARRAY_SIZE(cs35l41_ext_bst_widget));
 978                 if (ret)
 979                         return ret;
 980
 981                 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes,
 982                                               ARRAY_SIZE(cs35l41_ext_bst_routes));
 983                 if (ret)
 984                         return ret;
 985         }
 986
 987         return wm_adsp2_component_probe(&cs35l41->dsp, component);
 988 }
 989
 990 static void cs35l41_component_remove(struct snd_soc_component *component)
 991 {
 992         struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
 993
 994         wm_adsp2_component_remove(&cs35l41->dsp, component);
 995 }
 996
 997 static const struct snd_soc_dai_ops cs35l41_ops = {
 998         .startup = cs35l41_pcm_startup,
 999         .set_fmt = cs35l41_set_dai_fmt,
1000         .hw_params = cs35l41_pcm_hw_params,
1001         .set_sysclk = cs35l41_dai_set_sysclk,
1002         .set_channel_map = cs35l41_set_channel_map,
1003 };
1004
1005 static struct snd_soc_dai_driver cs35l41_dai[] = {
1006         {
1007                 .name = "cs35l41-pcm",
1008                 .id = 0,
1009                 .playback = {
1010                         .stream_name = "AMP Playback",
1011                         .channels_min = 1,
1012                         .channels_max = 2,
1013                         .rates = SNDRV_PCM_RATE_KNOT,
1014                         .formats = CS35L41_RX_FORMATS,
1015                 },
1016                 .capture = {
1017                         .stream_name = "AMP Capture",
1018                         .channels_min = 1,
1019                         .channels_max = 4,
1020                         .rates = SNDRV_PCM_RATE_KNOT,
1021                         .formats = CS35L41_TX_FORMATS,
1022                 },
1023                 .ops = &cs35l41_ops,
1024                 .symmetric_rate = 1,
1025         },
1026 };
1027
1028 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = {
1029         .name = "cs35l41-codec",
1030         .probe = cs35l41_component_probe,
1031         .remove = cs35l41_component_remove,
1032
1033         .dapm_widgets = cs35l41_dapm_widgets,
1034         .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets),
1035         .dapm_routes = cs35l41_audio_map,
1036         .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map),
1037
1038         .controls = cs35l41_aud_controls,
1039         .num_controls = ARRAY_SIZE(cs35l41_aud_controls),
1040         .set_sysclk = cs35l41_component_set_sysclk,
1041
1042         .endianness = 1,
1043 };
1044
1045 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg)
1046 {
1047         struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1;
1048         struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2;
1049         unsigned int val;
1050         int ret;
1051
1052         ret = device_property_read_u32(dev, "cirrus,boost-type", &val);
1053         if (ret >= 0)
1054                 hw_cfg->bst_type = val;
1055
1056         ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val);
1057         if (ret >= 0)
1058                 hw_cfg->bst_ipk = val;
1059         else
1060                 hw_cfg->bst_ipk = -1;
1061
1062         ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val);
1063         if (ret >= 0)
1064                 hw_cfg->bst_ind = val;
1065         else
1066                 hw_cfg->bst_ind = -1;
1067
1068         ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val);
1069         if (ret >= 0)
1070                 hw_cfg->bst_cap = val;
1071         else
1072                 hw_cfg->bst_cap = -1;
1073
1074         ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val);
1075         if (ret >= 0)
1076                 hw_cfg->dout_hiz = val;
1077         else
1078                 hw_cfg->dout_hiz = -1;
1079
1080         /* GPIO1 Pin Config */
1081         gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert");
1082         gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable");
1083         ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val);
1084         if (ret >= 0) {
1085                 gpio1->func = val;
1086                 gpio1->valid = true;
1087         }
1088
1089         /* GPIO2 Pin Config */
1090         gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert");
1091         gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable");
1092         ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val);
1093         if (ret >= 0) {
1094                 gpio2->func = val;
1095                 gpio2->valid = true;
1096         }
1097
1098         hw_cfg->valid = true;
1099
1100         return 0;
1101 }
1102
1103 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)
1104 {
1105         struct wm_adsp *dsp;
1106         int ret;
1107
1108         dsp = &cs35l41->dsp;
1109         dsp->part = "cs35l41";
1110         dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */
1111         dsp->toggle_preload = true;
1112
1113         cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp);
1114
1115         ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap);
1116         if (ret < 0)
1117                 return ret;
1118
1119         ret = wm_halo_init(dsp);
1120         if (ret) {
1121                 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret);
1122                 return ret;
1123         }
1124
1125         ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC,
1126                            CS35L41_INPUT_SRC_VPMON);
1127         if (ret < 0) {
1128                 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret);
1129                 goto err_dsp;
1130         }
1131         ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC,
1132                            CS35L41_INPUT_SRC_CLASSH);
1133         if (ret < 0) {
1134                 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret);
1135                 goto err_dsp;
1136         }
1137         ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC,
1138                            CS35L41_INPUT_SRC_TEMPMON);
1139         if (ret < 0) {
1140                 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret);
1141                 goto err_dsp;
1142         }
1143         ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC,
1144                            CS35L41_INPUT_SRC_RSVD);
1145         if (ret < 0) {
1146                 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret);
1147                 goto err_dsp;
1148         }
1149
1150         return 0;
1151
1152 err_dsp:
1153         wm_adsp2_remove(dsp);
1154
1155         return ret;
1156 }
1157
1158 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41)
1159 {
1160         acpi_handle handle = ACPI_HANDLE(cs35l41->dev);
1161         const char *sub;
1162
1163         /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */
1164         if (!handle)
1165                 return 0;
1166
1167         sub = acpi_get_subsystem_id(handle);
1168         if (IS_ERR(sub)) {
1169                 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */
1170                 if (PTR_ERR(sub) == -ENODATA)
1171                         return 0;
1172                 else
1173                         return PTR_ERR(sub);
1174         }
1175
1176         cs35l41->dsp.system_name = sub;
1177         dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name);
1178
1179         return 0;
1180 }
1181
1182 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg)
1183 {
1184         u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match;
1185         int irq_pol = 0;
1186         int ret;
1187
1188         if (hw_cfg) {
1189                 cs35l41->hw_cfg = *hw_cfg;
1190         } else {
1191                 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg);
1192                 if (ret != 0)
1193                         return ret;
1194         }
1195
1196         for (i = 0; i < CS35L41_NUM_SUPPLIES; i++)
1197                 cs35l41->supplies[i].supply = cs35l41_supplies[i];
1198
1199         ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES,
1200                                       cs35l41->supplies);
1201         if (ret != 0) {
1202                 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret);
1203                 return ret;
1204         }
1205
1206         ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1207         if (ret != 0) {
1208                 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret);
1209                 return ret;
1210         }
1211
1212         /* returning NULL can be an option if in stereo mode */
1213         cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset",
1214                                                       GPIOD_OUT_LOW);
1215         if (IS_ERR(cs35l41->reset_gpio)) {
1216                 ret = PTR_ERR(cs35l41->reset_gpio);
1217                 cs35l41->reset_gpio = NULL;
1218                 if (ret == -EBUSY) {
1219                         dev_info(cs35l41->dev,
1220                                  "Reset line busy, assuming shared reset\n");
1221                 } else {
1222                         dev_err(cs35l41->dev,
1223                                 "Failed to get reset GPIO: %d\n", ret);
1224                         goto err;
1225                 }
1226         }
1227         if (cs35l41->reset_gpio) {
1228                 /* satisfy minimum reset pulse width spec */
1229                 usleep_range(2000, 2100);
1230                 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
1231         }
1232
1233         usleep_range(2000, 2100);
1234
1235         ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4,
1236                                        int_status, int_status & CS35L41_OTP_BOOT_DONE,
1237                                        1000, 100000);
1238         if (ret) {
1239                 dev_err(cs35l41->dev,
1240                         "Failed waiting for OTP_BOOT_DONE: %d\n", ret);
1241                 goto err;
1242         }
1243
1244         regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status);
1245         if (int_status & CS35L41_OTP_BOOT_ERR) {
1246                 dev_err(cs35l41->dev, "OTP Boot error\n");
1247                 ret = -EINVAL;
1248                 goto err;
1249         }
1250
1251         ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, &regid);
1252         if (ret < 0) {
1253                 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret);
1254                 goto err;
1255         }
1256
1257         ret = regmap_read(cs35l41->regmap, CS35L41_REVID, &reg_revid);
1258         if (ret < 0) {
1259                 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret);
1260                 goto err;
1261         }
1262
1263         mtl_revid = reg_revid & CS35L41_MTLREVID_MASK;
1264
1265         /* CS35L41 will have even MTLREVID
1266          * CS35L41R will have odd MTLREVID
1267          */
1268         chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID;
1269         if (regid != chipid_match) {
1270                 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n",
1271                         regid, chipid_match);
1272                 ret = -ENODEV;
1273                 goto err;
1274         }
1275
1276         cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1277
1278         ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid);
1279         if (ret)
1280                 goto err;
1281
1282         ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap);
1283         if (ret < 0) {
1284                 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret);
1285                 goto err;
1286         }
1287
1288         cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1289
1290         irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg);
1291
1292         /* Set interrupt masks for critical errors */
1293         regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1,
1294                      CS35L41_INT1_MASK_DEFAULT);
1295
1296         ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq,
1297                                         IRQF_ONESHOT | IRQF_SHARED | irq_pol,
1298                                         "cs35l41", cs35l41);
1299         if (ret != 0) {
1300                 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret);
1301                 goto err;
1302         }
1303
1304         ret = cs35l41_set_pdata(cs35l41);
1305         if (ret < 0) {
1306                 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret);
1307                 goto err;
1308         }
1309
1310         ret = cs35l41_acpi_get_name(cs35l41);
1311         if (ret < 0)
1312                 goto err;
1313
1314         ret = cs35l41_dsp_init(cs35l41);
1315         if (ret < 0)
1316                 goto err;
1317
1318         pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000);
1319         pm_runtime_use_autosuspend(cs35l41->dev);
1320         pm_runtime_mark_last_busy(cs35l41->dev);
1321         pm_runtime_set_active(cs35l41->dev);
1322         pm_runtime_get_noresume(cs35l41->dev);
1323         pm_runtime_enable(cs35l41->dev);
1324
1325         ret = devm_snd_soc_register_component(cs35l41->dev,
1326                                               &soc_component_dev_cs35l41,
1327                                               cs35l41_dai, ARRAY_SIZE(cs35l41_dai));
1328         if (ret < 0) {
1329                 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret);
1330                 goto err_pm;
1331         }
1332
1333         pm_runtime_put_autosuspend(cs35l41->dev);
1334
1335         dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n",
1336                  regid, reg_revid);
1337
1338         return 0;
1339
1340 err_pm:
1341         pm_runtime_dont_use_autosuspend(cs35l41->dev);
1342         pm_runtime_disable(cs35l41->dev);
1343         pm_runtime_put_noidle(cs35l41->dev);
1344
1345         wm_adsp2_remove(&cs35l41->dsp);
1346 err:
1347         cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1348         regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1349         gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1350
1351         return ret;
1352 }
1353 EXPORT_SYMBOL_GPL(cs35l41_probe);
1354
1355 void cs35l41_remove(struct cs35l41_private *cs35l41)
1356 {
1357         pm_runtime_get_sync(cs35l41->dev);
1358         pm_runtime_dont_use_autosuspend(cs35l41->dev);
1359         pm_runtime_disable(cs35l41->dev);
1360
1361         regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
1362         kfree(cs35l41->dsp.system_name);
1363         wm_adsp2_remove(&cs35l41->dsp);
1364         cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1365
1366         pm_runtime_put_noidle(cs35l41->dev);
1367
1368         regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1369         gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1370 }
1371 EXPORT_SYMBOL_GPL(cs35l41_remove);
1372
1373 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev)
1374 {
1375         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1376
1377         dev_dbg(cs35l41->dev, "Runtime suspend\n");
1378
1379         if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1380                 return 0;
1381
1382         cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1383
1384         regcache_cache_only(cs35l41->regmap, true);
1385         regcache_mark_dirty(cs35l41->regmap);
1386
1387         return 0;
1388 }
1389
1390 static int __maybe_unused cs35l41_runtime_resume(struct device *dev)
1391 {
1392         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1393         int ret;
1394
1395         dev_dbg(cs35l41->dev, "Runtime resume\n");
1396
1397         if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1398                 return 0;
1399
1400         regcache_cache_only(cs35l41->regmap, false);
1401
1402         ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap);
1403         if (ret)
1404                 return ret;
1405
1406         /* Test key needs to be unlocked to allow the OTP settings to re-apply */
1407         cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1408         ret = regcache_sync(cs35l41->regmap);
1409         cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1410         if (ret) {
1411                 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret);
1412                 return ret;
1413         }
1414         cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg);
1415
1416         return 0;
1417 }
1418
1419 static int __maybe_unused cs35l41_sys_suspend(struct device *dev)
1420 {
1421         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1422
1423         dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n");
1424         disable_irq(cs35l41->irq);
1425
1426         return 0;
1427 }
1428
1429 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev)
1430 {
1431         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1432
1433         dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n");
1434         enable_irq(cs35l41->irq);
1435
1436         return 0;
1437 }
1438
1439 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev)
1440 {
1441         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1442
1443         dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n");
1444         disable_irq(cs35l41->irq);
1445
1446         return 0;
1447 }
1448
1449 static int __maybe_unused cs35l41_sys_resume(struct device *dev)
1450 {
1451         struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1452
1453         dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n");
1454         enable_irq(cs35l41->irq);
1455
1456         return 0;
1457 }
1458
1459 const struct dev_pm_ops cs35l41_pm_ops = {
1460         SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL)
1461
1462         SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume)
1463         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq)
1464 };
1465 EXPORT_SYMBOL_GPL(cs35l41_pm_ops);
1466
1467 MODULE_DESCRIPTION("ASoC CS35L41 driver");
1468 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
1469 MODULE_LICENSE("GPL");