2 * Copyright 2015 Linaro Ltd.
3 * Copyright (C) 2014 ZTE Corporation.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
12 #include <linux/clk-provider.h>
13 #include <linux/spinlock.h>
15 #define PNAME(x) static const char *x[]
17 struct zx_pll_config {
25 void __iomem *reg_base;
26 const struct zx_pll_config *lookup_table; /* order by rate asc */
29 u8 pd_bit; /* power down bit */
30 u8 lock_bit; /* pll lock flag bit */
33 #define PLL_RATE(_rate, _cfg0, _cfg1) \
40 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \
42 .reg_base = (void __iomem *) _reg, \
43 .lookup_table = _table, \
44 .count = ARRAY_SIZE(_table), \
47 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
48 CLK_GET_RATE_NOCACHE), \
52 * The pd_bit is not available on ZX296718, so let's pass something
53 * bigger than 31, e.g. 0xff, to indicate that.
55 #define ZX296718_PLL(_name, _parent, _reg, _table) \
56 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
63 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \
66 .reg = (void __iomem *) _reg, \
70 .hw.init = CLK_HW_INIT(_name, \
73 _flag | CLK_IGNORE_UNUSED), \
78 struct zx_clk_fixed_factor {
79 struct clk_fixed_factor factor;
83 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \
88 .hw.init = CLK_HW_INIT(_name, \
90 &clk_fixed_factor_ops, \
101 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \
104 .reg = (void __iomem *) _reg, \
105 .mask = BIT(_width) - 1, \
109 .hw.init = CLK_HW_INIT_PARENTS(_name, \
117 #define MUX(_id, _name, _parent, _reg, _shift, _width) \
118 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
121 struct clk_divider div;
125 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \
128 .reg = (void __iomem *) _reg, \
134 .hw.init = CLK_HW_INIT(_name, \
142 struct clk_zx_audio_divider {
144 void __iomem *reg_base;
145 unsigned int rate_count;
150 #define AUDIO_DIV(_id, _name, _parent, _reg) \
152 .reg_base = (void __iomem *) _reg, \
154 .hw.init = CLK_HW_INIT(_name, \
161 struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
162 unsigned long flags, void __iomem *reg_base,
163 const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
165 struct clk_zx_audio {
167 void __iomem *reg_base;
170 struct clk *clk_register_zx_audio(const char *name,
171 const char * const parent_name,
172 unsigned long flags, void __iomem *reg_base);
174 extern const struct clk_ops zx_pll_ops;
175 extern const struct clk_ops zx_audio_div_ops;