1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #ifndef __QCOM_CLK_ALPHA_PLL_H__
9 #define __QCOM_CLK_ALPHA_PLL_H__
11 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
16 CLK_ALPHA_PLL_TYPE_DEFAULT,
17 CLK_ALPHA_PLL_TYPE_HUAYRA,
18 CLK_ALPHA_PLL_TYPE_BRAMMO,
19 CLK_ALPHA_PLL_TYPE_FABIA,
20 CLK_ALPHA_PLL_TYPE_TRION,
21 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
22 CLK_ALPHA_PLL_TYPE_AGERA,
23 CLK_ALPHA_PLL_TYPE_ZONDA,
24 CLK_ALPHA_PLL_TYPE_LUCID_EVO,
25 CLK_ALPHA_PLL_TYPE_LUCID_OLE,
26 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
27 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
28 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
29 CLK_ALPHA_PLL_TYPE_STROMER,
30 CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
31 CLK_ALPHA_PLL_TYPE_MAX,
44 PLL_OFF_CONFIG_CTL_U1,
57 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
60 unsigned long min_freq;
61 unsigned long max_freq;
65 #define VCO(a, b, c) { \
72 * struct clk_alpha_pll - phase locked loop (PLL)
73 * @offset: base address of registers
74 * @vco_table: array of VCO settings
75 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
76 * @clkr: regmap clock handle
78 struct clk_alpha_pll {
82 const struct pll_vco *vco_table;
84 #define SUPPORTS_OFFLINE_REQ BIT(0)
85 #define SUPPORTS_FSM_MODE BIT(2)
86 #define SUPPORTS_DYNAMIC_UPDATE BIT(3)
87 #define SUPPORTS_FSM_LEGACY_MODE BIT(4)
90 struct clk_regmap clkr;
94 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
95 * @offset: base address of registers
96 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
97 * @width: width of post-divider
98 * @post_div_shift: shift to differentiate between odd & even post-divider
99 * @post_div_table: table with PLL odd and even post-divider settings
100 * @num_post_div: Number of PLL post-divider settings
102 * @clkr: regmap clock handle
104 struct clk_alpha_pll_postdiv {
109 struct clk_regmap clkr;
111 const struct clk_div_table *post_div_table;
115 struct alpha_pll_config {
120 u32 config_ctl_hi_val;
121 u32 config_ctl_hi1_val;
124 u32 user_ctl_hi1_val;
128 u32 test_ctl_hi_mask;
129 u32 test_ctl_hi1_val;
130 u32 test_ctl_hi2_val;
131 u32 main_output_mask;
133 u32 aux2_output_mask;
134 u32 early_output_mask;
148 extern const struct clk_ops clk_alpha_pll_ops;
149 extern const struct clk_ops clk_alpha_pll_fixed_ops;
150 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
151 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
152 extern const struct clk_ops clk_alpha_pll_huayra_ops;
153 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
154 extern const struct clk_ops clk_alpha_pll_stromer_ops;
155 extern const struct clk_ops clk_alpha_pll_stromer_plus_ops;
157 extern const struct clk_ops clk_alpha_pll_fabia_ops;
158 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
159 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
161 extern const struct clk_ops clk_alpha_pll_trion_ops;
162 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
163 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
165 extern const struct clk_ops clk_alpha_pll_lucid_ops;
166 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
167 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
168 extern const struct clk_ops clk_alpha_pll_agera_ops;
170 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
171 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
172 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
174 extern const struct clk_ops clk_alpha_pll_zonda_ops;
175 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
177 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
178 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
179 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
180 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
181 #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
182 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
183 #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
185 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
186 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
188 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
189 const struct alpha_pll_config *config);
190 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
191 const struct alpha_pll_config *config);
192 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
193 const struct alpha_pll_config *config);
194 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
195 const struct alpha_pll_config *config);
196 #define clk_lucid_pll_configure(pll, regmap, config) \
197 clk_trion_pll_configure(pll, regmap, config)
199 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
200 const struct alpha_pll_config *config);
201 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
202 const struct alpha_pll_config *config);
203 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
204 const struct alpha_pll_config *config);
205 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
206 const struct alpha_pll_config *config);
207 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
208 const struct alpha_pll_config *config);