1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
7 * The Si5341 has 10 outputs and 5 synthesizers.
8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
11 * The Si5342 and Si5344 are smaller versions of the Si5345.
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/gcd.h>
18 #include <linux/math64.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <asm/unaligned.h>
25 #define SI5341_NUM_INPUTS 4
27 #define SI5340_MAX_NUM_OUTPUTS 4
28 #define SI5341_MAX_NUM_OUTPUTS 10
29 #define SI5342_MAX_NUM_OUTPUTS 2
30 #define SI5344_MAX_NUM_OUTPUTS 4
31 #define SI5345_MAX_NUM_OUTPUTS 10
33 #define SI5340_NUM_SYNTH 4
34 #define SI5341_NUM_SYNTH 5
35 #define SI5342_NUM_SYNTH 2
36 #define SI5344_NUM_SYNTH 4
37 #define SI5345_NUM_SYNTH 5
39 /* Range of the synthesizer fractional divider */
40 #define SI5341_SYNTH_N_MIN 10
41 #define SI5341_SYNTH_N_MAX 4095
43 /* The chip can get its input clock from 3 input pins or an XTAL */
45 /* There is one PLL running at 13500–14256 MHz */
46 #define SI5341_PLL_VCO_MIN 13500000000ull
47 #define SI5341_PLL_VCO_MAX 14256000000ull
49 /* The 5 frequency synthesizers obtain their input from the PLL */
50 struct clk_si5341_synth {
52 struct clk_si5341 *data;
55 #define to_clk_si5341_synth(_hw) \
56 container_of(_hw, struct clk_si5341_synth, hw)
58 /* The output stages can be connected to any synth (full mux) */
59 struct clk_si5341_output {
61 struct clk_si5341 *data;
64 #define to_clk_si5341_output(_hw) \
65 container_of(_hw, struct clk_si5341_output, hw)
69 struct regmap *regmap;
70 struct i2c_client *i2c_client;
71 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
72 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
73 struct clk *input_clk[SI5341_NUM_INPUTS];
74 const char *input_clk_name[SI5341_NUM_INPUTS];
75 const u16 *reg_output_offset;
76 const u16 *reg_rdiv_offset;
77 u64 freq_vco; /* 13500–14256 MHz */
82 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
84 struct clk_si5341_output_config {
85 u8 out_format_drv_bits;
91 #define SI5341_PAGE 0x0001
92 #define SI5341_PN_BASE 0x0002
93 #define SI5341_DEVICE_REV 0x0005
94 #define SI5341_STATUS 0x000C
95 #define SI5341_LOS 0x000D
96 #define SI5341_STATUS_STICKY 0x0011
97 #define SI5341_LOS_STICKY 0x0012
98 #define SI5341_SOFT_RST 0x001C
99 #define SI5341_IN_SEL 0x0021
100 #define SI5341_DEVICE_READY 0x00FE
101 #define SI5341_XAXB_CFG 0x090E
102 #define SI5341_IN_EN 0x0949
103 #define SI5341_INX_TO_PFD_EN 0x094A
106 #define SI5341_STATUS_SYSINCAL BIT(0)
107 #define SI5341_STATUS_LOSXAXB BIT(1)
108 #define SI5341_STATUS_LOSREF BIT(2)
109 #define SI5341_STATUS_LOL BIT(3)
111 /* Input selection */
112 #define SI5341_IN_SEL_MASK 0x06
113 #define SI5341_IN_SEL_SHIFT 1
114 #define SI5341_IN_SEL_REGCTRL 0x01
115 #define SI5341_INX_TO_PFD_SHIFT 4
117 /* XTAL config bits */
118 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
119 #define SI5341_XAXB_CFG_PDNB BIT(1)
121 /* Input dividers (48-bit) */
122 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
123 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
124 #define SI5341_PX_UPD 0x0230
126 /* PLL configuration */
127 #define SI5341_PLL_M_NUM 0x0235
128 #define SI5341_PLL_M_DEN 0x023B
130 /* Output configuration */
131 #define SI5341_OUT_CONFIG(output) \
132 ((output)->data->reg_output_offset[(output)->index])
133 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
134 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
135 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
136 #define SI5341_OUT_R_REG(output) \
137 ((output)->data->reg_rdiv_offset[(output)->index])
139 /* Synthesize N divider */
140 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
141 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
142 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
144 /* Synthesizer output enable, phase bypass, power mode */
145 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
146 #define SI5341_SYNTH_N_PIBYP 0x0A04
147 #define SI5341_SYNTH_N_PDNB 0x0A05
148 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
150 #define SI5341_REGISTER_MAX 0xBFF
152 /* SI5341_OUT_CONFIG bits */
153 #define SI5341_OUT_CFG_PDN BIT(0)
154 #define SI5341_OUT_CFG_OE BIT(1)
155 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
157 /* Static configuration (to be moved to firmware) */
158 struct si5341_reg_default {
163 static const char * const si5341_input_clock_names[] = {
164 "in0", "in1", "in2", "xtal"
167 /* Output configuration registers 0..9 are not quite logically organized */
168 /* Also for si5345 */
169 static const u16 si5341_reg_output_offset[] = {
182 /* for si5340, si5342 and si5344 */
183 static const u16 si5340_reg_output_offset[] = {
190 /* The location of the R divider registers */
191 static const u16 si5341_reg_rdiv_offset[] = {
203 static const u16 si5340_reg_rdiv_offset[] = {
211 * Programming sequence from ClockBuilder, settings to initialize the system
212 * using only the XTAL input, without pre-divider.
213 * This also contains settings that aren't mentioned anywhere in the datasheet.
214 * The "known" settings like synth and output configuration are done later.
216 static const struct si5341_reg_default si5341_reg_defaults[] = {
217 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
218 { 0x0018, 0xFF }, /* INT mask */
219 { 0x0021, 0x0F }, /* Select XTAL as input */
220 { 0x0022, 0x00 }, /* Not in datasheet */
221 { 0x002B, 0x02 }, /* SPI config */
222 { 0x002C, 0x20 }, /* LOS enable for XTAL */
223 { 0x002D, 0x00 }, /* LOS timing */
234 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
239 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
240 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
241 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
242 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
243 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
244 { 0x009E, 0x00 }, /* Not in datasheet */
245 { 0x0102, 0x01 }, /* Enable outputs */
246 { 0x013F, 0x00 }, /* Not in datasheet */
247 { 0x0140, 0x00 }, /* Not in datasheet */
248 { 0x0141, 0x40 }, /* OUT LOS */
249 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
253 { 0x0206, 0x00 }, /* PXAXB (2^x) */
254 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
293 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
294 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
301 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
302 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
303 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
332 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
333 { 0x0359, 0x00 }, /* Nx_DELAY */
342 { 0x0362, 0x00 }, /* Nx_DELAY end */
343 { 0x0802, 0x00 }, /* Not in datasheet */
344 { 0x0803, 0x00 }, /* Not in datasheet */
345 { 0x0804, 0x00 }, /* Not in datasheet */
346 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
347 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
348 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
349 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
350 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
351 { 0x0A02, 0x00 }, /* Not in datasheet */
352 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
353 { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
354 { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
357 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
358 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
359 u64 *val1, u32 *val2)
364 err = regmap_bulk_read(regmap, reg, r, 10);
368 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
369 (get_unaligned_le32(r));
370 *val2 = get_unaligned_le32(&r[6]);
375 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
376 u64 n_num, u32 n_den)
380 /* Shift left as far as possible without overflowing */
381 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
386 /* 44 bits (6 bytes) numerator */
387 put_unaligned_le32(n_num, r);
388 r[4] = (n_num >> 32) & 0xff;
389 r[5] = (n_num >> 40) & 0x0f;
390 /* 32 bits denominator */
391 put_unaligned_le32(n_den, &r[6]);
393 /* Program the fraction */
394 return regmap_bulk_write(regmap, reg, r, sizeof(r));
397 /* VCO, we assume it runs at a constant frequency */
398 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
399 unsigned long parent_rate)
401 struct clk_si5341 *data = to_clk_si5341(hw);
408 /* Assume that PDIV is not being used, just read the PLL setting */
409 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
414 if (!m_num || !m_den)
418 * Though m_num is 64-bit, only the upper bits are actually used. While
419 * calculating m_num and m_den, they are shifted as far as possible to
420 * the left. To avoid 96-bit division here, we just shift them back so
421 * we can do with just 64 bits.
425 while (res & 0xffff00000000ULL) {
430 do_div(res, (m_den >> shift));
432 /* We cannot return the actual frequency in 32 bit, store it locally */
433 data->freq_vco = res;
435 /* Report kHz since the value is out of range */
438 return (unsigned long)res;
441 static int si5341_clk_get_selected_input(struct clk_si5341 *data)
446 err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
450 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
453 static u8 si5341_clk_get_parent(struct clk_hw *hw)
455 struct clk_si5341 *data = to_clk_si5341(hw);
456 int res = si5341_clk_get_selected_input(data);
459 return 0; /* Apparently we cannot report errors */
464 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
469 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
470 /* Enable register-based input selection */
471 val |= SI5341_IN_SEL_REGCTRL;
473 err = regmap_update_bits(data->regmap,
474 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
479 /* Enable input buffer for selected input */
480 err = regmap_update_bits(data->regmap,
481 SI5341_IN_EN, 0x07, BIT(index));
485 /* Enables the input to phase detector */
486 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
487 0x7 << SI5341_INX_TO_PFD_SHIFT,
488 BIT(index + SI5341_INX_TO_PFD_SHIFT));
492 /* Power down XTAL oscillator and buffer */
493 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
494 SI5341_XAXB_CFG_PDNB, 0);
499 * Set the P divider to "1". There's no explanation in the
500 * datasheet of these registers, but the clockbuilder software
501 * programs a "1" when the input is being used.
503 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
507 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
511 /* Set update PDIV bit */
512 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
516 /* Disable all input buffers */
517 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
521 /* Disable input to phase detector */
522 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
523 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
527 /* Power up XTAL oscillator and buffer */
528 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
529 SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
537 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
539 struct clk_si5341 *data = to_clk_si5341(hw);
541 return si5341_clk_reparent(data, index);
544 static const struct clk_ops si5341_clk_ops = {
545 .set_parent = si5341_clk_set_parent,
546 .get_parent = si5341_clk_get_parent,
547 .recalc_rate = si5341_clk_recalc_rate,
550 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
552 /* The synthesizer is on if all power and enable bits are set */
553 static int si5341_synth_clk_is_on(struct clk_hw *hw)
555 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
558 u8 index = synth->index;
560 err = regmap_read(synth->data->regmap,
561 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
565 if (!(val & BIT(index)))
568 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
572 if (!(val & BIT(index)))
575 /* This bit must be 0 for the synthesizer to receive clock input */
576 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
580 return !(val & BIT(index));
583 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
585 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
586 u8 index = synth->index; /* In range 0..5 */
587 u8 mask = BIT(index);
590 regmap_update_bits(synth->data->regmap,
591 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
593 regmap_update_bits(synth->data->regmap,
594 SI5341_SYNTH_N_PDNB, mask, 0);
595 /* Disable clock input to synth (set to 1 to disable) */
596 regmap_update_bits(synth->data->regmap,
597 SI5341_SYNTH_N_CLK_DIS, mask, mask);
600 static int si5341_synth_clk_prepare(struct clk_hw *hw)
602 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
604 u8 index = synth->index;
605 u8 mask = BIT(index);
608 err = regmap_update_bits(synth->data->regmap,
609 SI5341_SYNTH_N_PDNB, mask, mask);
613 /* Enable clock input to synth (set bit to 0 to enable) */
614 err = regmap_update_bits(synth->data->regmap,
615 SI5341_SYNTH_N_CLK_DIS, mask, 0);
620 return regmap_update_bits(synth->data->regmap,
621 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
624 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
625 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
626 unsigned long parent_rate)
628 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
634 err = si5341_decode_44_32(synth->data->regmap,
635 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
638 /* Check for bogus/uninitialized settings */
639 if (!n_num || !n_den)
643 * n_num and n_den are shifted left as much as possible, so to prevent
644 * overflow in 64-bit math, we shift n_den 4 bits to the right
646 f = synth->data->freq_vco;
649 /* Now we need to to 64-bit division: f/n_num */
650 /* And compensate for the 4 bits we dropped */
651 f = div64_u64(f, (n_num >> 4));
656 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
657 unsigned long *parent_rate)
659 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
662 /* The synthesizer accuracy is such that anything in range will work */
663 f = synth->data->freq_vco;
664 do_div(f, SI5341_SYNTH_N_MAX);
668 f = synth->data->freq_vco;
669 do_div(f, SI5341_SYNTH_N_MIN);
676 static int si5341_synth_program(struct clk_si5341_synth *synth,
677 u64 n_num, u32 n_den, bool is_integer)
680 u8 index = synth->index;
682 err = si5341_encode_44_32(synth->data->regmap,
683 SI5341_SYNTH_N_NUM(index), n_num, n_den);
685 err = regmap_update_bits(synth->data->regmap,
686 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
690 return regmap_write(synth->data->regmap,
691 SI5341_SYNTH_N_UPD(index), 0x01);
695 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
696 unsigned long parent_rate)
698 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
705 n_num = synth->data->freq_vco;
707 /* see if there's an integer solution */
708 r = do_div(n_num, rate);
709 is_integer = (r == 0);
711 /* Integer divider equal to n_num */
714 /* Calculate a fractional solution */
721 dev_dbg(&synth->data->i2c_client->dev,
722 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
723 synth->index, n_num, n_den,
724 is_integer ? "int" : "frac");
726 return si5341_synth_program(synth, n_num, n_den, is_integer);
729 static const struct clk_ops si5341_synth_clk_ops = {
730 .is_prepared = si5341_synth_clk_is_on,
731 .prepare = si5341_synth_clk_prepare,
732 .unprepare = si5341_synth_clk_unprepare,
733 .recalc_rate = si5341_synth_clk_recalc_rate,
734 .round_rate = si5341_synth_clk_round_rate,
735 .set_rate = si5341_synth_clk_set_rate,
738 static int si5341_output_clk_is_on(struct clk_hw *hw)
740 struct clk_si5341_output *output = to_clk_si5341_output(hw);
744 err = regmap_read(output->data->regmap,
745 SI5341_OUT_CONFIG(output), &val);
749 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
750 return (val & 0x03) == SI5341_OUT_CFG_OE;
753 /* Disables and then powers down the output */
754 static void si5341_output_clk_unprepare(struct clk_hw *hw)
756 struct clk_si5341_output *output = to_clk_si5341_output(hw);
758 regmap_update_bits(output->data->regmap,
759 SI5341_OUT_CONFIG(output),
760 SI5341_OUT_CFG_OE, 0);
761 regmap_update_bits(output->data->regmap,
762 SI5341_OUT_CONFIG(output),
763 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
766 /* Powers up and then enables the output */
767 static int si5341_output_clk_prepare(struct clk_hw *hw)
769 struct clk_si5341_output *output = to_clk_si5341_output(hw);
772 err = regmap_update_bits(output->data->regmap,
773 SI5341_OUT_CONFIG(output),
774 SI5341_OUT_CFG_PDN, 0);
778 return regmap_update_bits(output->data->regmap,
779 SI5341_OUT_CONFIG(output),
780 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
783 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
784 unsigned long parent_rate)
786 struct clk_si5341_output *output = to_clk_si5341_output(hw);
792 err = regmap_read(output->data->regmap,
793 SI5341_OUT_CONFIG(output), &val);
797 /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
798 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
799 return parent_rate / 2;
801 err = regmap_bulk_read(output->data->regmap,
802 SI5341_OUT_R_REG(output), r, 3);
806 /* Calculate value as 24-bit integer*/
807 r_divider = r[2] << 16 | r[1] << 8 | r[0];
809 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
813 /* Divider is 2*(Rx_REG+1) */
818 return parent_rate / r_divider;
821 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
822 unsigned long *parent_rate)
829 r = *parent_rate >> 1;
831 /* If rate is an even divisor, no changes to parent required */
832 if (r && !(r % rate))
835 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
836 if (rate > 200000000) {
837 /* minimum r-divider is 2 */
840 /* Take a parent frequency near 400 MHz */
841 r = (400000000u / rate) & ~1;
843 *parent_rate = r * rate;
845 /* We cannot change our parent's rate, report what we can do */
847 rate = *parent_rate / (r << 1);
853 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
854 unsigned long parent_rate)
856 struct clk_si5341_output *output = to_clk_si5341_output(hw);
864 /* Frequency divider is (r_div + 1) * 2 */
865 r_div = (parent_rate / rate) >> 1;
869 else if (r_div >= BIT(24))
874 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
875 err = regmap_update_bits(output->data->regmap,
876 SI5341_OUT_CONFIG(output),
877 SI5341_OUT_CFG_RDIV_FORCE2,
878 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
882 /* Always write Rx_REG, because a zero value disables the divider */
883 r[0] = r_div ? (r_div & 0xff) : 1;
884 r[1] = (r_div >> 8) & 0xff;
885 r[2] = (r_div >> 16) & 0xff;
886 err = regmap_bulk_write(output->data->regmap,
887 SI5341_OUT_R_REG(output), r, 3);
892 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
894 return regmap_update_bits(output->data->regmap,
895 SI5341_OUT_MUX_SEL(output), 0x07, index);
898 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
900 struct clk_si5341_output *output = to_clk_si5341_output(hw);
902 if (index >= output->data->num_synth)
905 return si5341_output_reparent(output, index);
908 static u8 si5341_output_get_parent(struct clk_hw *hw)
910 struct clk_si5341_output *output = to_clk_si5341_output(hw);
913 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
918 static const struct clk_ops si5341_output_clk_ops = {
919 .is_prepared = si5341_output_clk_is_on,
920 .prepare = si5341_output_clk_prepare,
921 .unprepare = si5341_output_clk_unprepare,
922 .recalc_rate = si5341_output_clk_recalc_rate,
923 .round_rate = si5341_output_clk_round_rate,
924 .set_rate = si5341_output_clk_set_rate,
925 .set_parent = si5341_output_set_parent,
926 .get_parent = si5341_output_get_parent,
930 * The chip can be bought in a pre-programmed version, or one can program the
931 * NVM in the chip to boot up in a preset mode. This routine tries to determine
932 * if that's the case, or if we need to reset and program everything from
933 * scratch. Returns negative error, or true/false.
935 static int si5341_is_programmed_already(struct clk_si5341 *data)
940 /* Read the PLL divider value, it must have a non-zero value */
941 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
946 return !!get_unaligned_le32(r);
949 static struct clk_hw *
950 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
952 struct clk_si5341 *data = _data;
953 unsigned int idx = clkspec->args[1];
954 unsigned int group = clkspec->args[0];
958 if (idx >= data->num_outputs) {
959 dev_err(&data->i2c_client->dev,
960 "invalid output index %u\n", idx);
961 return ERR_PTR(-EINVAL);
963 return &data->clk[idx].hw;
965 if (idx >= data->num_synth) {
966 dev_err(&data->i2c_client->dev,
967 "invalid synthesizer index %u\n", idx);
968 return ERR_PTR(-EINVAL);
970 return &data->synth[idx].hw;
973 dev_err(&data->i2c_client->dev,
974 "invalid PLL index %u\n", idx);
975 return ERR_PTR(-EINVAL);
979 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
980 return ERR_PTR(-EINVAL);
984 static int si5341_probe_chip_id(struct clk_si5341 *data)
990 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
993 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
997 model = get_unaligned_le16(reg);
999 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
1000 model, reg[2], reg[3]);
1004 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
1005 data->num_synth = SI5340_NUM_SYNTH;
1006 data->reg_output_offset = si5340_reg_output_offset;
1007 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1010 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
1011 data->num_synth = SI5341_NUM_SYNTH;
1012 data->reg_output_offset = si5341_reg_output_offset;
1013 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1016 data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
1017 data->num_synth = SI5342_NUM_SYNTH;
1018 data->reg_output_offset = si5340_reg_output_offset;
1019 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1022 data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
1023 data->num_synth = SI5344_NUM_SYNTH;
1024 data->reg_output_offset = si5340_reg_output_offset;
1025 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1028 data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1029 data->num_synth = SI5345_NUM_SYNTH;
1030 data->reg_output_offset = si5341_reg_output_offset;
1031 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1034 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1039 data->chip_id = model;
1044 /* Read active settings into the regmap cache for later reference */
1045 static int si5341_read_settings(struct clk_si5341 *data)
1051 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1055 err = regmap_bulk_read(data->regmap,
1056 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1060 err = regmap_bulk_read(data->regmap,
1061 SI5341_SYNTH_N_CLK_DIS, r, 1);
1065 for (i = 0; i < data->num_synth; ++i) {
1066 err = regmap_bulk_read(data->regmap,
1067 SI5341_SYNTH_N_NUM(i), r, 10);
1072 for (i = 0; i < data->num_outputs; ++i) {
1073 err = regmap_bulk_read(data->regmap,
1074 data->reg_output_offset[i], r, 4);
1078 err = regmap_bulk_read(data->regmap,
1079 data->reg_rdiv_offset[i], r, 3);
1087 static int si5341_write_multiple(struct clk_si5341 *data,
1088 const struct si5341_reg_default *values, unsigned int num_values)
1093 for (i = 0; i < num_values; ++i) {
1094 res = regmap_write(data->regmap,
1095 values[i].address, values[i].value);
1097 dev_err(&data->i2c_client->dev,
1098 "Failed to write %#x:%#x\n",
1099 values[i].address, values[i].value);
1107 static const struct si5341_reg_default si5341_preamble[] = {
1115 static const struct si5341_reg_default si5345_preamble[] = {
1120 static int si5341_send_preamble(struct clk_si5341 *data)
1125 /* For revision 2 and up, the values are slightly different */
1126 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1130 /* Write "preamble" as specified by datasheet */
1131 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1135 /* The si5342..si5345 require a different preamble */
1136 if (data->chip_id > 0x5341)
1137 res = si5341_write_multiple(data,
1138 si5345_preamble, ARRAY_SIZE(si5345_preamble));
1140 res = si5341_write_multiple(data,
1141 si5341_preamble, ARRAY_SIZE(si5341_preamble));
1145 /* Datasheet specifies a 300ms wait after sending the preamble */
1151 /* Perform a soft reset and write post-amble */
1152 static int si5341_finalize_defaults(struct clk_si5341 *data)
1157 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1161 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1163 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1167 /* The si5342..si5345 have an additional post-amble */
1168 if (data->chip_id > 0x5341) {
1169 res = regmap_write(data->regmap, 0x540, 0x0);
1174 /* Datasheet does not explain these nameless registers */
1175 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1178 res = regmap_write(data->regmap, 0x0B25, 0x02);
1186 static const struct regmap_range si5341_regmap_volatile_range[] = {
1187 regmap_reg_range(0x000C, 0x0012), /* Status */
1188 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1189 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1190 /* Update bits for P divider and synth config */
1191 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1192 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1193 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1194 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1195 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1196 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1199 static const struct regmap_access_table si5341_regmap_volatile = {
1200 .yes_ranges = si5341_regmap_volatile_range,
1201 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1204 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1205 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1208 .range_max = SI5341_REGISTER_MAX,
1209 .selector_reg = SI5341_PAGE,
1210 .selector_mask = 0xff,
1211 .selector_shift = 0,
1217 static int si5341_wait_device_ready(struct i2c_client *client)
1221 /* Datasheet warns: Any attempt to read or write any register other
1222 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1223 * NVM programming and may corrupt the register contents, as they are
1224 * read from NVM. Note that this includes accesses to the PAGE register.
1225 * Also: DEVICE_READY is available on every register page, so no page
1226 * change is needed to read it.
1227 * Do this outside regmap to avoid automatic PAGE register access.
1228 * May take up to 300ms to complete.
1230 for (count = 0; count < 15; ++count) {
1231 s32 result = i2c_smbus_read_byte_data(client,
1232 SI5341_DEVICE_READY);
1239 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1243 static const struct regmap_config si5341_regmap_config = {
1246 .cache_type = REGCACHE_RBTREE,
1247 .ranges = si5341_regmap_ranges,
1248 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1249 .max_register = SI5341_REGISTER_MAX,
1250 .volatile_table = &si5341_regmap_volatile,
1253 static int si5341_dt_parse_dt(struct i2c_client *client,
1254 struct clk_si5341_output_config *config)
1256 struct device_node *child;
1257 struct device_node *np = client->dev.of_node;
1261 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1262 SI5341_MAX_NUM_OUTPUTS);
1264 for_each_child_of_node(np, child) {
1265 if (of_property_read_u32(child, "reg", &num)) {
1266 dev_err(&client->dev, "missing reg property of %s\n",
1271 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1272 dev_err(&client->dev, "invalid clkout %d\n", num);
1276 if (!of_property_read_u32(child, "silabs,format", &val)) {
1277 /* Set cm and ampl conservatively to 3v3 settings */
1279 case 1: /* normal differential */
1280 config[num].out_cm_ampl_bits = 0x33;
1282 case 2: /* low-power differential */
1283 config[num].out_cm_ampl_bits = 0x13;
1285 case 4: /* LVCMOS */
1286 config[num].out_cm_ampl_bits = 0x33;
1287 /* Set SI recommended impedance for LVCMOS */
1288 config[num].out_format_drv_bits |= 0xc0;
1291 dev_err(&client->dev,
1292 "invalid silabs,format %u for %u\n",
1296 config[num].out_format_drv_bits &= ~0x07;
1297 config[num].out_format_drv_bits |= val & 0x07;
1298 /* Always enable the SYNC feature */
1299 config[num].out_format_drv_bits |= 0x08;
1302 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1304 dev_err(&client->dev,
1305 "invalid silabs,common-mode %u\n",
1309 config[num].out_cm_ampl_bits &= 0xf0;
1310 config[num].out_cm_ampl_bits |= val & 0x0f;
1313 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1315 dev_err(&client->dev,
1316 "invalid silabs,amplitude %u\n",
1320 config[num].out_cm_ampl_bits &= 0x0f;
1321 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1324 if (of_property_read_bool(child, "silabs,disable-high"))
1325 config[num].out_format_drv_bits |= 0x10;
1327 config[num].synth_master =
1328 of_property_read_bool(child, "silabs,synth-master");
1330 config[num].always_on =
1331 of_property_read_bool(child, "always-on");
1342 * If not pre-configured, calculate and set the PLL configuration manually.
1343 * For low-jitter performance, the PLL should be set such that the synthesizers
1344 * only need integer division.
1345 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1346 * the chip to generate any frequency on its outputs, but jitter performance
1347 * may be sub-optimal.
1349 static int si5341_initialize_pll(struct clk_si5341 *data)
1351 struct device_node *np = data->i2c_client->dev.of_node;
1356 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1357 dev_err(&data->i2c_client->dev,
1358 "PLL configuration requires silabs,pll-m-num\n");
1360 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1361 dev_err(&data->i2c_client->dev,
1362 "PLL configuration requires silabs,pll-m-den\n");
1365 if (!m_num || !m_den) {
1366 dev_err(&data->i2c_client->dev,
1367 "PLL configuration invalid, assume 14GHz\n");
1368 sel = si5341_clk_get_selected_input(data);
1372 m_den = clk_get_rate(data->input_clk[sel]) / 10;
1376 return si5341_encode_44_32(data->regmap,
1377 SI5341_PLL_M_NUM, m_num, m_den);
1380 static int si5341_clk_select_active_input(struct clk_si5341 *data)
1386 res = si5341_clk_get_selected_input(data);
1390 /* If the current register setting is invalid, pick the first input */
1391 if (!data->input_clk[res]) {
1392 dev_dbg(&data->i2c_client->dev,
1393 "Input %d not connected, rerouting\n", res);
1395 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1396 if (data->input_clk[i]) {
1402 dev_err(&data->i2c_client->dev,
1403 "No clock input available\n");
1408 /* Make sure the selected clock is also enabled and routed */
1409 err = si5341_clk_reparent(data, res);
1413 err = clk_prepare_enable(data->input_clk[res]);
1420 static int si5341_probe(struct i2c_client *client,
1421 const struct i2c_device_id *id)
1423 struct clk_si5341 *data;
1424 struct clk_init_data init;
1426 const char *root_clock_name;
1427 const char *synth_clock_names[SI5341_NUM_SYNTH];
1430 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1431 bool initialization_required;
1434 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1438 data->i2c_client = client;
1440 /* Must be done before otherwise touching hardware */
1441 err = si5341_wait_device_ready(client);
1445 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1446 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1447 if (IS_ERR(input)) {
1448 if (PTR_ERR(input) == -EPROBE_DEFER)
1449 return -EPROBE_DEFER;
1450 data->input_clk_name[i] = si5341_input_clock_names[i];
1452 data->input_clk[i] = input;
1453 data->input_clk_name[i] = __clk_get_name(input);
1457 err = si5341_dt_parse_dt(client, config);
1461 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1463 init.name = client->dev.of_node->name;
1464 root_clock_name = init.name;
1466 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1467 if (IS_ERR(data->regmap))
1468 return PTR_ERR(data->regmap);
1470 i2c_set_clientdata(client, data);
1472 err = si5341_probe_chip_id(data);
1476 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1477 initialization_required = true;
1479 err = si5341_is_programmed_already(data);
1483 initialization_required = !err;
1486 if (initialization_required) {
1487 /* Populate the regmap cache in preparation for "cache only" */
1488 err = si5341_read_settings(data);
1492 err = si5341_send_preamble(data);
1497 * We intend to send all 'final' register values in a single
1498 * transaction. So cache all register writes until we're done
1501 regcache_cache_only(data->regmap, true);
1503 /* Write the configuration pairs from the firmware blob */
1504 err = si5341_write_multiple(data, si5341_reg_defaults,
1505 ARRAY_SIZE(si5341_reg_defaults));
1510 /* Input must be up and running at this point */
1511 err = si5341_clk_select_active_input(data);
1515 if (initialization_required) {
1516 /* PLL configuration is required */
1517 err = si5341_initialize_pll(data);
1522 /* Register the PLL */
1523 init.parent_names = data->input_clk_name;
1524 init.num_parents = SI5341_NUM_INPUTS;
1525 init.ops = &si5341_clk_ops;
1527 data->hw.init = &init;
1529 err = devm_clk_hw_register(&client->dev, &data->hw);
1531 dev_err(&client->dev, "clock registration failed\n");
1535 init.num_parents = 1;
1536 init.parent_names = &root_clock_name;
1537 init.ops = &si5341_synth_clk_ops;
1538 for (i = 0; i < data->num_synth; ++i) {
1539 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1540 "%s.N%u", client->dev.of_node->name, i);
1541 init.name = synth_clock_names[i];
1542 data->synth[i].index = i;
1543 data->synth[i].data = data;
1544 data->synth[i].hw.init = &init;
1545 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1547 dev_err(&client->dev,
1548 "synth N%u registration failed\n", i);
1552 init.num_parents = data->num_synth;
1553 init.parent_names = synth_clock_names;
1554 init.ops = &si5341_output_clk_ops;
1555 for (i = 0; i < data->num_outputs; ++i) {
1556 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1557 client->dev.of_node->name, i);
1558 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1559 data->clk[i].index = i;
1560 data->clk[i].data = data;
1561 data->clk[i].hw.init = &init;
1562 if (config[i].out_format_drv_bits & 0x07) {
1563 regmap_write(data->regmap,
1564 SI5341_OUT_FORMAT(&data->clk[i]),
1565 config[i].out_format_drv_bits);
1566 regmap_write(data->regmap,
1567 SI5341_OUT_CM(&data->clk[i]),
1568 config[i].out_cm_ampl_bits);
1570 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1571 kfree(init.name); /* clock framework made a copy of the name */
1573 dev_err(&client->dev,
1574 "output %u registration failed\n", i);
1577 if (config[i].always_on)
1578 clk_prepare(data->clk[i].hw.clk);
1581 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get,
1584 dev_err(&client->dev, "unable to add clk provider\n");
1588 if (initialization_required) {
1590 regcache_cache_only(data->regmap, false);
1591 err = regcache_sync(data->regmap);
1595 err = si5341_finalize_defaults(data);
1600 /* wait for device to report input clock present and PLL lock */
1601 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
1602 !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
1605 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
1609 /* clear sticky alarm bits from initialization */
1610 err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1612 dev_err(&client->dev, "unable to clear sticky status\n");
1616 /* Free the names, clk framework makes copies */
1617 for (i = 0; i < data->num_synth; ++i)
1618 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1623 static const struct i2c_device_id si5341_id[] = {
1631 MODULE_DEVICE_TABLE(i2c, si5341_id);
1633 static const struct of_device_id clk_si5341_of_match[] = {
1634 { .compatible = "silabs,si5340" },
1635 { .compatible = "silabs,si5341" },
1636 { .compatible = "silabs,si5342" },
1637 { .compatible = "silabs,si5344" },
1638 { .compatible = "silabs,si5345" },
1641 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1643 static struct i2c_driver si5341_driver = {
1646 .of_match_table = clk_si5341_of_match,
1648 .probe = si5341_probe,
1649 .id_table = si5341_id,
1651 module_i2c_driver(si5341_driver);
1653 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1654 MODULE_DESCRIPTION("Si5341 driver");
1655 MODULE_LICENSE("GPL");