1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * clock driver for Freescale QorIQ SoCs.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/fsl/guts.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
20 #include <linux/slab.h>
27 #define PLATFORM_PLL 0
31 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
34 #define MAX_PLL_DIV 32
36 struct clockgen_pll_div {
42 struct clockgen_pll_div div[MAX_PLL_DIV];
45 #define CLKSEL_VALID 1
46 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
48 struct clockgen_sourceinfo {
49 u32 flags; /* CLKSEL_xxx */
50 int pll; /* CGx_PLLn */
51 int div; /* PLL_DIVn */
54 #define NUM_MUX_PARENTS 16
56 struct clockgen_muxinfo {
57 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
66 * cmux freq must be >= platform pll.
67 * If not set, cmux freq must be >= platform pll/2
69 #define CG_CMUX_GE_PLAT 1
71 #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */
72 #define CG_VER3 4 /* version 3 cg: reg layout different */
73 #define CG_LITTLE_ENDIAN 8
75 struct clockgen_chipinfo {
76 const char *compat, *guts_compat;
77 const struct clockgen_muxinfo *cmux_groups[2];
78 const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
79 void (*init_periph)(struct clockgen *cg);
80 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
81 u32 pll_mask; /* 1 << n bit set if PLL n is valid */
82 u32 flags; /* CG_xxx */
86 struct device_node *node;
88 struct clockgen_chipinfo info; /* mutable copy */
89 struct clk *sysclk, *coreclk;
90 struct clockgen_pll pll[6];
91 struct clk *cmux[NUM_CMUX];
92 struct clk *hwaccel[NUM_HWACCEL];
94 struct ccsr_guts __iomem *guts;
97 static struct clockgen clockgen;
98 static bool add_cpufreq_dev __initdata;
100 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
102 if (cg->info.flags & CG_LITTLE_ENDIAN)
105 iowrite32be(val, reg);
108 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
112 if (cg->info.flags & CG_LITTLE_ENDIAN)
115 val = ioread32be(reg);
120 static const struct clockgen_muxinfo p2041_cmux_grp1 = {
122 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
123 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
124 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
128 static const struct clockgen_muxinfo p2041_cmux_grp2 = {
130 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
131 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
132 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
136 static const struct clockgen_muxinfo p5020_cmux_grp1 = {
138 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
139 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
140 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
144 static const struct clockgen_muxinfo p5020_cmux_grp2 = {
146 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
147 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
148 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
152 static const struct clockgen_muxinfo p5040_cmux_grp1 = {
154 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
155 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
156 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
157 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
161 static const struct clockgen_muxinfo p5040_cmux_grp2 = {
163 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
164 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
165 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
166 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
170 static const struct clockgen_muxinfo p4080_cmux_grp1 = {
172 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
173 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
174 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
175 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
176 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
180 static const struct clockgen_muxinfo p4080_cmux_grp2 = {
182 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
183 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
184 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
185 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
186 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
190 static const struct clockgen_muxinfo t1023_cmux = {
192 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
193 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
197 static const struct clockgen_muxinfo t1040_cmux = {
199 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
200 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
201 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
202 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
207 static const struct clockgen_muxinfo clockgen2_cmux_cga = {
209 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
213 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
217 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
218 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
223 static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
225 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
229 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
235 static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
237 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
238 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
241 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
242 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
247 static const struct clockgen_muxinfo ls1021a_cmux = {
249 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
250 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
255 static const struct clockgen_muxinfo ls1028a_hwa1 = {
257 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
258 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
259 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
260 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
261 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
263 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
264 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
268 static const struct clockgen_muxinfo ls1028a_hwa2 = {
270 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
271 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
272 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
273 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
274 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
276 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
277 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
281 static const struct clockgen_muxinfo ls1028a_hwa3 = {
283 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
284 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
285 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
286 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
287 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
289 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
290 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
294 static const struct clockgen_muxinfo ls1028a_hwa4 = {
296 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
297 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
298 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
299 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
300 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
302 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
303 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
307 static const struct clockgen_muxinfo ls1043a_hwa1 = {
311 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
312 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
315 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
316 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
320 static const struct clockgen_muxinfo ls1043a_hwa2 = {
323 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
325 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
329 static const struct clockgen_muxinfo ls1046a_hwa1 = {
333 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
334 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
335 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
336 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
337 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
338 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
342 static const struct clockgen_muxinfo ls1046a_hwa2 = {
345 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
346 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
347 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
350 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
354 static const struct clockgen_muxinfo ls1088a_hwa1 = {
357 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
358 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
359 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
362 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
363 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
367 static const struct clockgen_muxinfo ls1088a_hwa2 = {
370 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
371 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
372 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
373 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
375 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
376 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
380 static const struct clockgen_muxinfo ls1012a_cmux = {
382 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
384 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
388 static const struct clockgen_muxinfo t1023_hwa1 = {
391 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
392 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
393 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
397 static const struct clockgen_muxinfo t1023_hwa2 = {
399 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
403 static const struct clockgen_muxinfo t2080_hwa1 = {
406 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
407 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
408 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
409 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
410 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
411 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
412 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
416 static const struct clockgen_muxinfo t2080_hwa2 = {
419 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
420 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
421 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
422 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
423 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
424 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
425 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
429 static const struct clockgen_muxinfo t4240_hwa1 = {
431 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
432 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
433 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
434 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
435 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
437 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
438 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
442 static const struct clockgen_muxinfo t4240_hwa4 = {
444 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
445 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
446 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
447 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
448 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
452 static const struct clockgen_muxinfo t4240_hwa5 = {
454 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
455 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
456 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
457 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
458 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
459 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
463 #define RCWSR7_FM1_CLK_SEL 0x40000000
464 #define RCWSR7_FM2_CLK_SEL 0x20000000
465 #define RCWSR7_HWA_ASYNC_DIV 0x04000000
467 static void __init p2041_init_periph(struct clockgen *cg)
471 reg = ioread32be(&cg->guts->rcwsr[7]);
473 if (reg & RCWSR7_FM1_CLK_SEL)
474 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
476 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
479 static void __init p4080_init_periph(struct clockgen *cg)
483 reg = ioread32be(&cg->guts->rcwsr[7]);
485 if (reg & RCWSR7_FM1_CLK_SEL)
486 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
488 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
490 if (reg & RCWSR7_FM2_CLK_SEL)
491 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
493 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
496 static void __init p5020_init_periph(struct clockgen *cg)
501 reg = ioread32be(&cg->guts->rcwsr[7]);
502 if (reg & RCWSR7_HWA_ASYNC_DIV)
505 if (reg & RCWSR7_FM1_CLK_SEL)
506 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
508 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
511 static void __init p5040_init_periph(struct clockgen *cg)
516 reg = ioread32be(&cg->guts->rcwsr[7]);
517 if (reg & RCWSR7_HWA_ASYNC_DIV)
520 if (reg & RCWSR7_FM1_CLK_SEL)
521 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
523 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
525 if (reg & RCWSR7_FM2_CLK_SEL)
526 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
528 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
531 static void __init t1023_init_periph(struct clockgen *cg)
533 cg->fman[0] = cg->hwaccel[1];
536 static void __init t1040_init_periph(struct clockgen *cg)
538 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
541 static void __init t2080_init_periph(struct clockgen *cg)
543 cg->fman[0] = cg->hwaccel[0];
546 static void __init t4240_init_periph(struct clockgen *cg)
548 cg->fman[0] = cg->hwaccel[3];
549 cg->fman[1] = cg->hwaccel[4];
552 static const struct clockgen_chipinfo chipinfo[] = {
554 .compat = "fsl,b4420-clockgen",
555 .guts_compat = "fsl,b4860-device-config",
556 .init_periph = t2080_init_periph,
558 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
567 .flags = CG_PLL_8BIT,
570 .compat = "fsl,b4860-clockgen",
571 .guts_compat = "fsl,b4860-device-config",
572 .init_periph = t2080_init_periph,
574 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
583 .flags = CG_PLL_8BIT,
586 .compat = "fsl,ls1021a-clockgen",
596 .compat = "fsl,ls1028a-clockgen",
598 &clockgen2_cmux_cga12
601 &ls1028a_hwa1, &ls1028a_hwa2,
602 &ls1028a_hwa3, &ls1028a_hwa4
608 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
611 .compat = "fsl,ls1043a-clockgen",
612 .init_periph = t2080_init_periph,
617 &ls1043a_hwa1, &ls1043a_hwa2
623 .flags = CG_PLL_8BIT,
626 .compat = "fsl,ls1046a-clockgen",
627 .init_periph = t2080_init_periph,
632 &ls1046a_hwa1, &ls1046a_hwa2
638 .flags = CG_PLL_8BIT,
641 .compat = "fsl,ls1088a-clockgen",
643 &clockgen2_cmux_cga12
646 &ls1088a_hwa1, &ls1088a_hwa2
652 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
655 .compat = "fsl,ls1012a-clockgen",
665 .compat = "fsl,ls2080a-clockgen",
667 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
673 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
676 .compat = "fsl,lx2160a-clockgen",
678 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
681 0, 0, 0, 0, 1, 1, 1, 1, -1
684 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
687 .compat = "fsl,p2041-clockgen",
688 .guts_compat = "fsl,qoriq-device-config-1.0",
689 .init_periph = p2041_init_periph,
691 &p2041_cmux_grp1, &p2041_cmux_grp2
699 .compat = "fsl,p3041-clockgen",
700 .guts_compat = "fsl,qoriq-device-config-1.0",
701 .init_periph = p2041_init_periph,
703 &p2041_cmux_grp1, &p2041_cmux_grp2
711 .compat = "fsl,p4080-clockgen",
712 .guts_compat = "fsl,qoriq-device-config-1.0",
713 .init_periph = p4080_init_periph,
715 &p4080_cmux_grp1, &p4080_cmux_grp2
718 0, 0, 0, 0, 1, 1, 1, 1, -1
723 .compat = "fsl,p5020-clockgen",
724 .guts_compat = "fsl,qoriq-device-config-1.0",
725 .init_periph = p5020_init_periph,
727 &p5020_cmux_grp1, &p5020_cmux_grp2
735 .compat = "fsl,p5040-clockgen",
736 .guts_compat = "fsl,p5040-device-config",
737 .init_periph = p5040_init_periph,
739 &p5040_cmux_grp1, &p5040_cmux_grp2
747 .compat = "fsl,t1023-clockgen",
748 .guts_compat = "fsl,t1023-device-config",
749 .init_periph = t1023_init_periph,
754 &t1023_hwa1, &t1023_hwa2
760 .flags = CG_PLL_8BIT,
763 .compat = "fsl,t1040-clockgen",
764 .guts_compat = "fsl,t1040-device-config",
765 .init_periph = t1040_init_periph,
773 .flags = CG_PLL_8BIT,
776 .compat = "fsl,t2080-clockgen",
777 .guts_compat = "fsl,t2080-device-config",
778 .init_periph = t2080_init_periph,
780 &clockgen2_cmux_cga12
783 &t2080_hwa1, &t2080_hwa2
789 .flags = CG_PLL_8BIT,
792 .compat = "fsl,t4240-clockgen",
793 .guts_compat = "fsl,t4240-device-config",
794 .init_periph = t4240_init_periph,
796 &clockgen2_cmux_cga, &clockgen2_cmux_cgb
799 &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
805 .flags = CG_PLL_8BIT,
813 const struct clockgen_muxinfo *info;
815 u8 parent_to_clksel[NUM_MUX_PARENTS];
816 s8 clksel_to_parent[NUM_MUX_PARENTS];
820 #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw)
821 #define CLKSEL_MASK 0x78000000
822 #define CLKSEL_SHIFT 27
824 static int mux_set_parent(struct clk_hw *hw, u8 idx)
826 struct mux_hwclock *hwc = to_mux_hwclock(hw);
829 if (idx >= hwc->num_parents)
832 clksel = hwc->parent_to_clksel[idx];
833 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
838 static u8 mux_get_parent(struct clk_hw *hw)
840 struct mux_hwclock *hwc = to_mux_hwclock(hw);
844 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
846 ret = hwc->clksel_to_parent[clksel];
848 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
855 static const struct clk_ops cmux_ops = {
856 .get_parent = mux_get_parent,
857 .set_parent = mux_set_parent,
861 * Don't allow setting for now, as the clock options haven't been
862 * sanitized for additional restrictions.
864 static const struct clk_ops hwaccel_ops = {
865 .get_parent = mux_get_parent,
868 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
869 struct mux_hwclock *hwc,
874 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
877 pll = hwc->info->clksel[idx].pll;
878 div = hwc->info->clksel[idx].div;
880 return &cg->pll[pll].div[div];
883 static struct clk * __init create_mux_common(struct clockgen *cg,
884 struct mux_hwclock *hwc,
885 const struct clk_ops *ops,
886 unsigned long min_rate,
887 unsigned long max_rate,
888 unsigned long pct80_rate,
889 const char *fmt, int idx)
891 struct clk_init_data init = {};
893 const struct clockgen_pll_div *div;
894 const char *parent_names[NUM_MUX_PARENTS];
898 snprintf(name, sizeof(name), fmt, idx);
900 for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
903 hwc->clksel_to_parent[i] = -1;
905 div = get_pll_div(cg, hwc, i);
909 rate = clk_get_rate(div->clk);
911 if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
919 parent_names[j] = div->name;
920 hwc->parent_to_clksel[j] = i;
921 hwc->clksel_to_parent[i] = j;
927 init.parent_names = parent_names;
928 init.num_parents = hwc->num_parents = j;
930 hwc->hw.init = &init;
933 clk = clk_register(NULL, &hwc->hw);
935 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
944 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
946 struct mux_hwclock *hwc;
947 const struct clockgen_pll_div *div;
948 unsigned long plat_rate, min_rate;
949 u64 max_rate, pct80_rate;
952 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
956 if (cg->info.flags & CG_VER3)
957 hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
959 hwc->reg = cg->regs + 0x20 * idx;
961 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
964 * Find the rate for the default clksel, and treat it as the
965 * maximum rated core frequency. If this is an incorrect
966 * assumption, certain clock options (possibly including the
967 * default clksel) may be inappropriately excluded on certain
970 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
971 div = get_pll_div(cg, hwc, clksel);
977 max_rate = clk_get_rate(div->clk);
978 pct80_rate = max_rate * 8;
979 do_div(pct80_rate, 10);
981 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
983 if (cg->info.flags & CG_CMUX_GE_PLAT)
984 min_rate = plat_rate;
986 min_rate = plat_rate / 2;
988 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
989 pct80_rate, "cg-cmux%d", idx);
992 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
994 struct mux_hwclock *hwc;
996 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
1000 hwc->reg = cg->regs + 0x20 * idx + 0x10;
1001 hwc->info = cg->info.hwaccel[idx];
1003 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
1004 "cg-hwaccel%d", idx);
1007 static void __init create_muxes(struct clockgen *cg)
1011 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
1012 if (cg->info.cmux_to_group[i] < 0)
1014 if (cg->info.cmux_to_group[i] >=
1015 ARRAY_SIZE(cg->info.cmux_groups)) {
1020 cg->cmux[i] = create_one_cmux(cg, i);
1023 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
1024 if (!cg->info.hwaccel[i])
1027 cg->hwaccel[i] = create_one_hwaccel(cg, i);
1031 static void __init _clockgen_init(struct device_node *np, bool legacy);
1034 * Legacy nodes may get probed before the parent clockgen node.
1035 * It is assumed that device trees with legacy nodes will not
1036 * contain a "clocks" property -- otherwise the input clocks may
1037 * not be initialized at this point.
1039 static void __init legacy_init_clockgen(struct device_node *np)
1041 if (!clockgen.node) {
1042 struct device_node *parent_np;
1044 parent_np = of_get_parent(np);
1045 _clockgen_init(parent_np, true);
1046 of_node_put(parent_np);
1051 static void __init core_mux_init(struct device_node *np)
1054 struct resource res;
1057 legacy_init_clockgen(np);
1059 if (of_address_to_resource(np, 0, &res))
1062 idx = (res.start & 0xf0) >> 5;
1063 clk = clockgen.cmux[idx];
1065 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
1067 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1073 static struct clk __init
1074 *sysclk_from_fixed(struct device_node *node, const char *name)
1078 if (of_property_read_u32(node, "clock-frequency", &rate))
1079 return ERR_PTR(-ENODEV);
1081 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
1084 static struct clk __init *input_clock(const char *name, struct clk *clk)
1086 const char *input_name;
1088 /* Register the input clock under the desired name. */
1089 input_name = __clk_get_name(clk);
1090 clk = clk_register_fixed_factor(NULL, name, input_name,
1093 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
1099 static struct clk __init *input_clock_by_name(const char *name,
1104 clk = of_clk_get_by_name(clockgen.node, dtname);
1108 return input_clock(name, clk);
1111 static struct clk __init *input_clock_by_index(const char *name, int idx)
1115 clk = of_clk_get(clockgen.node, 0);
1119 return input_clock(name, clk);
1122 static struct clk * __init create_sysclk(const char *name)
1124 struct device_node *sysclk;
1127 clk = sysclk_from_fixed(clockgen.node, name);
1131 clk = input_clock_by_name(name, "sysclk");
1135 clk = input_clock_by_index(name, 0);
1139 sysclk = of_get_child_by_name(clockgen.node, "sysclk");
1141 clk = sysclk_from_fixed(sysclk, name);
1142 of_node_put(sysclk);
1147 pr_err("%s: No input sysclk\n", __func__);
1151 static struct clk * __init create_coreclk(const char *name)
1155 clk = input_clock_by_name(name, "coreclk");
1160 * This indicates a mix of legacy nodes with the new coreclk
1161 * mechanism, which should never happen. If this error occurs,
1162 * don't use the wrong input clock just because coreclk isn't
1165 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
1172 static void __init sysclk_init(struct device_node *node)
1176 legacy_init_clockgen(node);
1178 clk = clockgen.sysclk;
1180 of_clk_add_provider(node, of_clk_src_simple_get, clk);
1183 #define PLL_KILL BIT(31)
1185 static void __init create_one_pll(struct clockgen *cg, int idx)
1189 struct clockgen_pll *pll = &cg->pll[idx];
1190 const char *input = "cg-sysclk";
1193 if (!(cg->info.pll_mask & (1 << idx)))
1196 if (cg->coreclk && idx != PLATFORM_PLL) {
1197 if (IS_ERR(cg->coreclk))
1200 input = "cg-coreclk";
1203 if (cg->info.flags & CG_VER3) {
1206 reg = cg->regs + 0x60080;
1209 reg = cg->regs + 0x80;
1212 reg = cg->regs + 0xa0;
1215 reg = cg->regs + 0x10080;
1218 reg = cg->regs + 0x100a0;
1221 WARN_ONCE(1, "index %d\n", idx);
1225 if (idx == PLATFORM_PLL)
1226 reg = cg->regs + 0xc00;
1228 reg = cg->regs + 0x800 + 0x20 * (idx - 1);
1231 /* Get the multiple of PLL */
1232 mult = cg_in(cg, reg);
1234 /* Check if this PLL is disabled */
1235 if (mult & PLL_KILL) {
1236 pr_debug("%s(): pll %p disabled\n", __func__, reg);
1240 if ((cg->info.flags & CG_VER3) ||
1241 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1242 mult = (mult & GENMASK(8, 1)) >> 1;
1244 mult = (mult & GENMASK(6, 1)) >> 1;
1246 for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
1251 * For platform PLL, there are MAX_PLL_DIV divider clocks.
1252 * For core PLL, there are 4 divider clocks at most.
1254 if (idx != PLATFORM_PLL && i >= 4)
1257 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
1258 "cg-pll%d-div%d", idx, i + 1);
1260 clk = clk_register_fixed_factor(NULL,
1261 pll->div[i].name, input, 0, mult, i + 1);
1263 pr_err("%s: %s: register failed %ld\n",
1264 __func__, pll->div[i].name, PTR_ERR(clk));
1268 pll->div[i].clk = clk;
1269 ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
1271 pr_err("%s: %s: register to lookup table failed %d\n",
1272 __func__, pll->div[i].name, ret);
1277 static void __init create_plls(struct clockgen *cg)
1281 for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
1282 create_one_pll(cg, i);
1285 static void __init legacy_pll_init(struct device_node *np, int idx)
1287 struct clockgen_pll *pll;
1288 struct clk_onecell_data *onecell_data;
1289 struct clk **subclks;
1292 legacy_init_clockgen(np);
1294 pll = &clockgen.pll[idx];
1295 count = of_property_count_strings(np, "clock-output-names");
1297 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
1298 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
1302 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
1307 subclks[0] = pll->div[0].clk;
1308 subclks[1] = pll->div[1].clk;
1309 subclks[2] = pll->div[3].clk;
1311 subclks[0] = pll->div[0].clk;
1312 subclks[1] = pll->div[1].clk;
1313 subclks[2] = pll->div[2].clk;
1314 subclks[3] = pll->div[3].clk;
1317 onecell_data->clks = subclks;
1318 onecell_data->clk_num = count;
1320 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
1322 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1329 kfree(onecell_data);
1335 static void __init pltfrm_pll_init(struct device_node *np)
1337 legacy_pll_init(np, PLATFORM_PLL);
1341 static void __init core_pll_init(struct device_node *np)
1343 struct resource res;
1346 if (of_address_to_resource(np, 0, &res))
1349 if ((res.start & 0xfff) == 0xc00) {
1351 * ls1021a devtree labels the platform PLL
1352 * with the core PLL compatible
1354 pltfrm_pll_init(np);
1356 idx = (res.start & 0xf0) >> 5;
1357 legacy_pll_init(np, CGA_PLL1 + idx);
1361 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
1363 struct clockgen *cg = data;
1365 struct clockgen_pll *pll;
1368 if (clkspec->args_count < 2) {
1369 pr_err("%s: insufficient phandle args\n", __func__);
1370 return ERR_PTR(-EINVAL);
1373 type = clkspec->args[0];
1374 idx = clkspec->args[1];
1383 if (idx >= ARRAY_SIZE(cg->cmux))
1385 clk = cg->cmux[idx];
1388 if (idx >= ARRAY_SIZE(cg->hwaccel))
1390 clk = cg->hwaccel[idx];
1393 if (idx >= ARRAY_SIZE(cg->fman))
1395 clk = cg->fman[idx];
1398 pll = &cg->pll[PLATFORM_PLL];
1399 if (idx >= ARRAY_SIZE(pll->div))
1401 clk = pll->div[idx].clk;
1415 return ERR_PTR(-ENOENT);
1419 pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
1420 return ERR_PTR(-EINVAL);
1424 #include <asm/mpc85xx.h>
1426 static const u32 a4510_svrs[] __initconst = {
1427 (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */
1428 (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */
1429 (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */
1430 (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */
1431 (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */
1432 (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */
1433 (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */
1434 (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */
1435 (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */
1436 (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */
1437 (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */
1438 (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */
1439 (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */
1442 #define SVR_SECURITY 0x80000 /* The Security (E) bit */
1444 static bool __init has_erratum_a4510(void)
1446 u32 svr = mfspr(SPRN_SVR);
1449 svr &= ~SVR_SECURITY;
1451 for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
1452 if (svr == a4510_svrs[i])
1459 static bool __init has_erratum_a4510(void)
1465 static void __init _clockgen_init(struct device_node *np, bool legacy)
1468 bool is_old_ls1021a = false;
1470 /* May have already been called by a legacy probe */
1475 clockgen.regs = of_iomap(np, 0);
1476 if (!clockgen.regs &&
1477 of_device_is_compatible(of_root, "fsl,ls1021a")) {
1478 /* Compatibility hack for old, broken device trees */
1479 clockgen.regs = ioremap(0x1ee1000, 0x1000);
1480 is_old_ls1021a = true;
1482 if (!clockgen.regs) {
1483 pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
1487 for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
1488 if (of_device_is_compatible(np, chipinfo[i].compat))
1490 if (is_old_ls1021a &&
1491 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
1495 if (i == ARRAY_SIZE(chipinfo)) {
1496 pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
1499 clockgen.info = chipinfo[i];
1501 if (clockgen.info.guts_compat) {
1502 struct device_node *guts;
1504 guts = of_find_compatible_node(NULL, NULL,
1505 clockgen.info.guts_compat);
1507 clockgen.guts = of_iomap(guts, 0);
1508 if (!clockgen.guts) {
1509 pr_err("%s: Couldn't map %pOF regs\n", __func__,
1517 if (has_erratum_a4510())
1518 clockgen.info.flags |= CG_CMUX_GE_PLAT;
1520 clockgen.sysclk = create_sysclk("cg-sysclk");
1521 clockgen.coreclk = create_coreclk("cg-coreclk");
1522 create_plls(&clockgen);
1523 create_muxes(&clockgen);
1525 if (clockgen.info.init_periph)
1526 clockgen.info.init_periph(&clockgen);
1528 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
1530 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1534 /* Don't create cpufreq device for legacy clockgen blocks */
1535 add_cpufreq_dev = !legacy;
1539 iounmap(clockgen.regs);
1540 clockgen.regs = NULL;
1543 static void __init clockgen_init(struct device_node *np)
1545 _clockgen_init(np, false);
1548 static int __init clockgen_cpufreq_init(void)
1550 struct platform_device *pdev;
1552 if (add_cpufreq_dev) {
1553 pdev = platform_device_register_simple("qoriq-cpufreq", -1,
1556 pr_err("Couldn't register qoriq-cpufreq err=%ld\n",
1561 device_initcall(clockgen_cpufreq_init);
1563 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1564 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1565 CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
1566 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
1567 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1568 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1569 CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
1570 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1571 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1572 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1573 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1574 CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
1575 CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
1576 CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
1577 CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
1578 CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
1579 CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
1580 CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
1581 CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
1582 CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
1583 CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
1586 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1587 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1588 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1589 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1590 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1591 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1592 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1593 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);