1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
6 #include <linux/clk-provider.h>
8 #include <linux/slab.h>
10 static u8 clk_composite_get_parent(struct clk_hw *hw)
12 struct clk_composite *composite = to_clk_composite(hw);
13 const struct clk_ops *mux_ops = composite->mux_ops;
14 struct clk_hw *mux_hw = composite->mux_hw;
16 __clk_hw_set_clk(mux_hw, hw);
18 return mux_ops->get_parent(mux_hw);
21 static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
23 struct clk_composite *composite = to_clk_composite(hw);
24 const struct clk_ops *mux_ops = composite->mux_ops;
25 struct clk_hw *mux_hw = composite->mux_hw;
27 __clk_hw_set_clk(mux_hw, hw);
29 return mux_ops->set_parent(mux_hw, index);
32 static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
33 unsigned long parent_rate)
35 struct clk_composite *composite = to_clk_composite(hw);
36 const struct clk_ops *rate_ops = composite->rate_ops;
37 struct clk_hw *rate_hw = composite->rate_hw;
39 __clk_hw_set_clk(rate_hw, hw);
41 return rate_ops->recalc_rate(rate_hw, parent_rate);
44 static int clk_composite_determine_rate(struct clk_hw *hw,
45 struct clk_rate_request *req)
47 struct clk_composite *composite = to_clk_composite(hw);
48 const struct clk_ops *rate_ops = composite->rate_ops;
49 const struct clk_ops *mux_ops = composite->mux_ops;
50 struct clk_hw *rate_hw = composite->rate_hw;
51 struct clk_hw *mux_hw = composite->mux_hw;
52 struct clk_hw *parent;
53 unsigned long parent_rate;
54 long tmp_rate, best_rate = 0;
55 unsigned long rate_diff;
56 unsigned long best_rate_diff = ULONG_MAX;
60 if (rate_hw && rate_ops && rate_ops->determine_rate) {
61 __clk_hw_set_clk(rate_hw, hw);
62 return rate_ops->determine_rate(rate_hw, req);
63 } else if (rate_hw && rate_ops && rate_ops->round_rate &&
64 mux_hw && mux_ops && mux_ops->set_parent) {
65 req->best_parent_hw = NULL;
67 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
68 parent = clk_hw_get_parent(mux_hw);
69 req->best_parent_hw = parent;
70 req->best_parent_rate = clk_hw_get_rate(parent);
72 rate = rate_ops->round_rate(rate_hw, req->rate,
73 &req->best_parent_rate);
81 for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
82 parent = clk_hw_get_parent_by_index(mux_hw, i);
86 parent_rate = clk_hw_get_rate(parent);
88 tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
93 rate_diff = abs(req->rate - tmp_rate);
95 if (!rate_diff || !req->best_parent_hw
96 || best_rate_diff > rate_diff) {
97 req->best_parent_hw = parent;
98 req->best_parent_rate = parent_rate;
99 best_rate_diff = rate_diff;
100 best_rate = tmp_rate;
107 req->rate = best_rate;
109 } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
110 __clk_hw_set_clk(mux_hw, hw);
111 return mux_ops->determine_rate(mux_hw, req);
113 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
118 static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
119 unsigned long *prate)
121 struct clk_composite *composite = to_clk_composite(hw);
122 const struct clk_ops *rate_ops = composite->rate_ops;
123 struct clk_hw *rate_hw = composite->rate_hw;
125 __clk_hw_set_clk(rate_hw, hw);
127 return rate_ops->round_rate(rate_hw, rate, prate);
130 static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
131 unsigned long parent_rate)
133 struct clk_composite *composite = to_clk_composite(hw);
134 const struct clk_ops *rate_ops = composite->rate_ops;
135 struct clk_hw *rate_hw = composite->rate_hw;
137 __clk_hw_set_clk(rate_hw, hw);
139 return rate_ops->set_rate(rate_hw, rate, parent_rate);
142 static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
144 unsigned long parent_rate,
147 struct clk_composite *composite = to_clk_composite(hw);
148 const struct clk_ops *rate_ops = composite->rate_ops;
149 const struct clk_ops *mux_ops = composite->mux_ops;
150 struct clk_hw *rate_hw = composite->rate_hw;
151 struct clk_hw *mux_hw = composite->mux_hw;
152 unsigned long temp_rate;
154 __clk_hw_set_clk(rate_hw, hw);
155 __clk_hw_set_clk(mux_hw, hw);
157 temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
158 if (temp_rate > rate) {
159 rate_ops->set_rate(rate_hw, rate, parent_rate);
160 mux_ops->set_parent(mux_hw, index);
162 mux_ops->set_parent(mux_hw, index);
163 rate_ops->set_rate(rate_hw, rate, parent_rate);
169 static int clk_composite_is_enabled(struct clk_hw *hw)
171 struct clk_composite *composite = to_clk_composite(hw);
172 const struct clk_ops *gate_ops = composite->gate_ops;
173 struct clk_hw *gate_hw = composite->gate_hw;
175 __clk_hw_set_clk(gate_hw, hw);
177 return gate_ops->is_enabled(gate_hw);
180 static int clk_composite_enable(struct clk_hw *hw)
182 struct clk_composite *composite = to_clk_composite(hw);
183 const struct clk_ops *gate_ops = composite->gate_ops;
184 struct clk_hw *gate_hw = composite->gate_hw;
186 __clk_hw_set_clk(gate_hw, hw);
188 return gate_ops->enable(gate_hw);
191 static void clk_composite_disable(struct clk_hw *hw)
193 struct clk_composite *composite = to_clk_composite(hw);
194 const struct clk_ops *gate_ops = composite->gate_ops;
195 struct clk_hw *gate_hw = composite->gate_hw;
197 __clk_hw_set_clk(gate_hw, hw);
199 gate_ops->disable(gate_hw);
202 static struct clk_hw *__clk_hw_register_composite(struct device *dev,
203 const char *name, const char * const *parent_names,
204 const struct clk_parent_data *pdata, int num_parents,
205 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
206 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
207 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
211 struct clk_init_data init = {};
212 struct clk_composite *composite;
213 struct clk_ops *clk_composite_ops;
216 composite = kzalloc(sizeof(*composite), GFP_KERNEL);
218 return ERR_PTR(-ENOMEM);
223 init.parent_names = parent_names;
225 init.parent_data = pdata;
226 init.num_parents = num_parents;
229 clk_composite_ops = &composite->ops;
231 if (mux_hw && mux_ops) {
232 if (!mux_ops->get_parent) {
233 hw = ERR_PTR(-EINVAL);
237 composite->mux_hw = mux_hw;
238 composite->mux_ops = mux_ops;
239 clk_composite_ops->get_parent = clk_composite_get_parent;
240 if (mux_ops->set_parent)
241 clk_composite_ops->set_parent = clk_composite_set_parent;
242 if (mux_ops->determine_rate)
243 clk_composite_ops->determine_rate = clk_composite_determine_rate;
246 if (rate_hw && rate_ops) {
247 if (!rate_ops->recalc_rate) {
248 hw = ERR_PTR(-EINVAL);
251 clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
253 if (rate_ops->determine_rate)
254 clk_composite_ops->determine_rate =
255 clk_composite_determine_rate;
256 else if (rate_ops->round_rate)
257 clk_composite_ops->round_rate =
258 clk_composite_round_rate;
260 /* .set_rate requires either .round_rate or .determine_rate */
261 if (rate_ops->set_rate) {
262 if (rate_ops->determine_rate || rate_ops->round_rate)
263 clk_composite_ops->set_rate =
264 clk_composite_set_rate;
266 WARN(1, "%s: missing round_rate op is required\n",
270 composite->rate_hw = rate_hw;
271 composite->rate_ops = rate_ops;
274 if (mux_hw && mux_ops && rate_hw && rate_ops) {
275 if (mux_ops->set_parent && rate_ops->set_rate)
276 clk_composite_ops->set_rate_and_parent =
277 clk_composite_set_rate_and_parent;
280 if (gate_hw && gate_ops) {
281 if (!gate_ops->is_enabled || !gate_ops->enable ||
282 !gate_ops->disable) {
283 hw = ERR_PTR(-EINVAL);
287 composite->gate_hw = gate_hw;
288 composite->gate_ops = gate_ops;
289 clk_composite_ops->is_enabled = clk_composite_is_enabled;
290 clk_composite_ops->enable = clk_composite_enable;
291 clk_composite_ops->disable = clk_composite_disable;
294 init.ops = clk_composite_ops;
295 composite->hw.init = &init;
297 ret = clk_hw_register(dev, hw);
303 if (composite->mux_hw)
304 composite->mux_hw->clk = hw->clk;
306 if (composite->rate_hw)
307 composite->rate_hw->clk = hw->clk;
309 if (composite->gate_hw)
310 composite->gate_hw->clk = hw->clk;
319 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
320 const char * const *parent_names, int num_parents,
321 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
322 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
323 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
326 return __clk_hw_register_composite(dev, name, parent_names, NULL,
327 num_parents, mux_hw, mux_ops,
328 rate_hw, rate_ops, gate_hw,
331 EXPORT_SYMBOL_GPL(clk_hw_register_composite);
333 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
335 const struct clk_parent_data *parent_data,
337 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
338 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
339 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
342 return __clk_hw_register_composite(dev, name, NULL, parent_data,
343 num_parents, mux_hw, mux_ops,
344 rate_hw, rate_ops, gate_hw,
348 struct clk *clk_register_composite(struct device *dev, const char *name,
349 const char * const *parent_names, int num_parents,
350 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
351 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
352 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
357 hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
358 mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
365 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
366 const struct clk_parent_data *parent_data,
368 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
369 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
370 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
375 hw = clk_hw_register_composite_pdata(dev, name, parent_data,
376 num_parents, mux_hw, mux_ops, rate_hw, rate_ops,
377 gate_hw, gate_ops, flags);
383 void clk_unregister_composite(struct clk *clk)
385 struct clk_composite *composite;
388 hw = __clk_get_hw(clk);
392 composite = to_clk_composite(hw);
398 void clk_hw_unregister_composite(struct clk_hw *hw)
400 struct clk_composite *composite;
402 composite = to_clk_composite(hw);
404 clk_hw_unregister(hw);
407 EXPORT_SYMBOL_GPL(clk_hw_unregister_composite);