2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
28 #include <asm/byteorder.h>
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
62 size_t *, struct otp_info *);
63 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
64 size_t *, struct otp_info *);
65 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
66 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
68 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
70 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
72 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
74 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
75 size_t *retlen, const u_char *buf);
77 static void cfi_amdstd_destroy(struct mtd_info *);
79 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
80 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
82 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
83 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
86 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
87 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
89 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
90 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
91 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
93 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
94 .probe = NULL, /* Not usable directly */
95 .destroy = cfi_amdstd_destroy,
96 .name = "cfi_cmdset_0002",
101 /* #define DEBUG_CFI_FEATURES */
104 #ifdef DEBUG_CFI_FEATURES
105 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
107 const char* erase_suspend[3] = {
108 "Not supported", "Read only", "Read/write"
110 const char* top_bottom[6] = {
111 "No WP", "8x8KiB sectors at top & bottom, no WP",
112 "Bottom boot", "Top boot",
113 "Uniform, Bottom WP", "Uniform, Top WP"
116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
117 printk(" Address sensitive unlock: %s\n",
118 (extp->SiliconRevision & 1) ? "Not required" : "Required");
120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
125 if (extp->BlkProt == 0)
126 printk(" Block protection: Not supported\n");
128 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
131 printk(" Temporary block unprotect: %s\n",
132 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
135 printk(" Burst mode: %s\n",
136 extp->BurstMode ? "Supported" : "Not supported");
137 if (extp->PageMode == 0)
138 printk(" Page mode: Not supported\n");
140 printk(" Page mode: %d word page\n", extp->PageMode << 2);
142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
143 extp->VppMin >> 4, extp->VppMin & 0xf);
144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
145 extp->VppMax >> 4, extp->VppMax & 0xf);
147 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
154 #ifdef AMD_BOOTLOC_BUG
155 /* Wheee. Bring me the head of someone at AMD. */
156 static void fixup_amd_bootblock(struct mtd_info *mtd)
158 struct map_info *map = mtd->priv;
159 struct cfi_private *cfi = map->fldrv_priv;
160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
161 __u8 major = extp->MajorVersion;
162 __u8 minor = extp->MinorVersion;
164 if (((major << 8) | minor) < 0x3131) {
165 /* CFI version 1.0 => don't trust bootloc */
167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
168 map->name, cfi->mfr, cfi->id);
170 /* AFAICS all 29LV400 with a bottom boot block have a device ID
171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
172 * These were badly detected as they have the 0x80 bit set
173 * so treat them as a special case.
175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
177 /* Macronix added CFI to their 2nd generation
178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
179 * Fujitsu, Spansion, EON, ESI and older Macronix)
182 * Therefore also check the manufacturer.
183 * This reduces the risk of false detection due to
184 * the 8-bit device ID.
186 (cfi->mfr == CFI_MFR_MACRONIX)) {
187 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
188 " detected\n", map->name);
189 extp->TopBottom = 2; /* bottom boot */
191 if (cfi->id & 0x80) {
192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
193 extp->TopBottom = 3; /* top boot */
195 extp->TopBottom = 2; /* bottom boot */
198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
199 " deduced %s from Device ID\n", map->name, major, minor,
200 extp->TopBottom == 2 ? "bottom" : "top");
205 static void fixup_use_write_buffers(struct mtd_info *mtd)
207 struct map_info *map = mtd->priv;
208 struct cfi_private *cfi = map->fldrv_priv;
209 if (cfi->cfiq->BufWriteTimeoutTyp) {
210 pr_debug("Using buffer write method\n" );
211 mtd->_write = cfi_amdstd_write_buffers;
215 /* Atmel chips don't use the same PRI format as AMD chips */
216 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
218 struct map_info *map = mtd->priv;
219 struct cfi_private *cfi = map->fldrv_priv;
220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
221 struct cfi_pri_atmel atmel_pri;
223 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
224 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
226 if (atmel_pri.Features & 0x02)
227 extp->EraseSuspend = 2;
229 /* Some chips got it backwards... */
230 if (cfi->id == AT49BV6416) {
231 if (atmel_pri.BottomBoot)
236 if (atmel_pri.BottomBoot)
242 /* burst write mode not supported */
243 cfi->cfiq->BufWriteTimeoutTyp = 0;
244 cfi->cfiq->BufWriteTimeoutMax = 0;
247 static void fixup_use_secsi(struct mtd_info *mtd)
249 /* Setup for chips with a secsi area */
250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
254 static void fixup_use_erase_chip(struct mtd_info *mtd)
256 struct map_info *map = mtd->priv;
257 struct cfi_private *cfi = map->fldrv_priv;
258 if ((cfi->cfiq->NumEraseRegions == 1) &&
259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
260 mtd->_erase = cfi_amdstd_erase_chip;
266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
269 static void fixup_use_atmel_lock(struct mtd_info *mtd)
271 mtd->_lock = cfi_atmel_lock;
272 mtd->_unlock = cfi_atmel_unlock;
273 mtd->flags |= MTD_POWERUP_LOCK;
276 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
278 struct map_info *map = mtd->priv;
279 struct cfi_private *cfi = map->fldrv_priv;
282 * These flashes report two separate eraseblock regions based on the
283 * sector_erase-size and block_erase-size, although they both operate on the
284 * same memory. This is not allowed according to CFI, so we just pick the
287 cfi->cfiq->NumEraseRegions = 1;
290 static void fixup_sst39vf(struct mtd_info *mtd)
292 struct map_info *map = mtd->priv;
293 struct cfi_private *cfi = map->fldrv_priv;
295 fixup_old_sst_eraseregion(mtd);
297 cfi->addr_unlock1 = 0x5555;
298 cfi->addr_unlock2 = 0x2AAA;
301 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
303 struct map_info *map = mtd->priv;
304 struct cfi_private *cfi = map->fldrv_priv;
306 fixup_old_sst_eraseregion(mtd);
308 cfi->addr_unlock1 = 0x555;
309 cfi->addr_unlock2 = 0x2AA;
311 cfi->sector_erase_cmd = CMD(0x50);
314 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
316 struct map_info *map = mtd->priv;
317 struct cfi_private *cfi = map->fldrv_priv;
319 fixup_sst39vf_rev_b(mtd);
322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
323 * it should report a size of 8KBytes (0x0020*256).
325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
326 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n",
330 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
332 struct map_info *map = mtd->priv;
333 struct cfi_private *cfi = map->fldrv_priv;
335 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
336 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
337 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n",
342 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
344 struct map_info *map = mtd->priv;
345 struct cfi_private *cfi = map->fldrv_priv;
347 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
348 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
349 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n",
354 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
356 struct map_info *map = mtd->priv;
357 struct cfi_private *cfi = map->fldrv_priv;
360 * S29NS512P flash uses more than 8bits to report number of sectors,
361 * which is not permitted by CFI.
363 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
364 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n",
368 /* Used to fix CFI-Tables of chips without Extended Query Tables */
369 static struct cfi_fixup cfi_nopri_fixup_table[] = {
370 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
371 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
372 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
373 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
374 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
375 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
376 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
377 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
381 static struct cfi_fixup cfi_fixup_table[] = {
382 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
383 #ifdef AMD_BOOTLOC_BUG
384 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
385 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
386 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
388 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
389 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
390 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
391 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
392 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
393 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
394 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
395 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
396 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
397 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
398 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
399 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
400 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
401 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
402 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
403 #if !FORCE_WORD_WRITE
404 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
408 static struct cfi_fixup jedec_fixup_table[] = {
409 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
410 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
411 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
415 static struct cfi_fixup fixup_table[] = {
416 /* The CFI vendor ids and the JEDEC vendor IDs appear
417 * to be common. It is like the devices id's are as
418 * well. This table is to pick all cases where
419 * we know that is the case.
421 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
422 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
427 static void cfi_fixup_major_minor(struct cfi_private *cfi,
428 struct cfi_pri_amdstd *extp)
430 if (cfi->mfr == CFI_MFR_SAMSUNG) {
431 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
432 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
434 * Samsung K8P2815UQB and K8D6x16UxM chips
435 * report major=0 / minor=0.
436 * K8D3x16UxC chips report major=3 / minor=3.
438 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
439 " Extended Query version to 1.%c\n",
441 extp->MajorVersion = '1';
446 * SST 38VF640x chips report major=0xFF / minor=0xFF.
448 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
449 extp->MajorVersion = '1';
450 extp->MinorVersion = '0';
454 static int is_m29ew(struct cfi_private *cfi)
456 if (cfi->mfr == CFI_MFR_INTEL &&
457 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
458 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
464 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
465 * Some revisions of the M29EW suffer from erase suspend hang ups. In
466 * particular, it can occur when the sequence
467 * Erase Confirm -> Suspend -> Program -> Resume
468 * causes a lockup due to internal timing issues. The consequence is that the
469 * erase cannot be resumed without inserting a dummy command after programming
470 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
471 * that writes an F0 command code before the RESUME command.
473 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
476 struct cfi_private *cfi = map->fldrv_priv;
477 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
479 map_write(map, CMD(0xF0), adr);
483 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
485 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
486 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
487 * command is issued after an ERASE RESUME operation without waiting for a
488 * minimum delay. The result is that once the ERASE seems to be completed
489 * (no bits are toggling), the contents of the Flash memory block on which
490 * the erase was ongoing could be inconsistent with the expected values
491 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
492 * values), causing a consequent failure of the ERASE operation.
493 * The occurrence of this issue could be high, especially when file system
494 * operations on the Flash are intensive. As a result, it is recommended
495 * that a patch be applied. Intensive file system operations can cause many
496 * calls to the garbage routine to free Flash space (also by erasing physical
497 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
498 * commands can occur. The problem disappears when a delay is inserted after
499 * the RESUME command by using the udelay() function available in Linux.
500 * The DELAY value must be tuned based on the customer's platform.
501 * The maximum value that fixes the problem in all cases is 500us.
502 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
504 * We have chosen 500µs because this latency is acceptable.
506 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
509 * Resolving the Delay After Resume Issue see Micron TN-13-07
510 * Worst case delay must be 500µs but 30-50µs should be ok as well
516 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
518 struct cfi_private *cfi = map->fldrv_priv;
519 struct device_node __maybe_unused *np = map->device_node;
520 struct mtd_info *mtd;
523 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
527 mtd->type = MTD_NORFLASH;
529 /* Fill in the default mtd operations */
530 mtd->_erase = cfi_amdstd_erase_varsize;
531 mtd->_write = cfi_amdstd_write_words;
532 mtd->_read = cfi_amdstd_read;
533 mtd->_sync = cfi_amdstd_sync;
534 mtd->_suspend = cfi_amdstd_suspend;
535 mtd->_resume = cfi_amdstd_resume;
536 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
537 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
538 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
539 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
540 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
541 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
542 mtd->flags = MTD_CAP_NORFLASH;
543 mtd->name = map->name;
545 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
547 pr_debug("MTD %s(): write buffer size %d\n", __func__,
550 mtd->_panic_write = cfi_amdstd_panic_write;
551 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
553 if (cfi->cfi_mode==CFI_MODE_CFI){
554 unsigned char bootloc;
555 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
556 struct cfi_pri_amdstd *extp;
558 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
561 * It's a real CFI chip, not one for which the probe
562 * routine faked a CFI structure.
564 cfi_fixup_major_minor(cfi, extp);
567 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
568 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
569 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
570 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
571 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
573 if (extp->MajorVersion != '1' ||
574 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
575 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
576 "version %c.%c (%#02x/%#02x).\n",
577 extp->MajorVersion, extp->MinorVersion,
578 extp->MajorVersion, extp->MinorVersion);
584 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
585 extp->MajorVersion, extp->MinorVersion);
587 /* Install our own private info structure */
588 cfi->cmdset_priv = extp;
590 /* Apply cfi device specific fixups */
591 cfi_fixup(mtd, cfi_fixup_table);
593 #ifdef DEBUG_CFI_FEATURES
594 /* Tell the user about it in lots of lovely detail */
595 cfi_tell_features(extp);
599 if (np && of_property_read_bool(
600 np, "use-advanced-sector-protection")
601 && extp->BlkProtUnprot == 8) {
602 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
603 mtd->_lock = cfi_ppb_lock;
604 mtd->_unlock = cfi_ppb_unlock;
605 mtd->_is_locked = cfi_ppb_is_locked;
609 bootloc = extp->TopBottom;
610 if ((bootloc < 2) || (bootloc > 5)) {
611 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
612 "bank location (%d). Assuming bottom.\n",
617 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
618 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
620 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
621 int j = (cfi->cfiq->NumEraseRegions-1)-i;
623 swap(cfi->cfiq->EraseRegionInfo[i],
624 cfi->cfiq->EraseRegionInfo[j]);
627 /* Set the default CFI lock/unlock addresses */
628 cfi->addr_unlock1 = 0x555;
629 cfi->addr_unlock2 = 0x2aa;
631 cfi_fixup(mtd, cfi_nopri_fixup_table);
633 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
639 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
640 /* Apply jedec specific fixups */
641 cfi_fixup(mtd, jedec_fixup_table);
643 /* Apply generic fixups */
644 cfi_fixup(mtd, fixup_table);
646 for (i=0; i< cfi->numchips; i++) {
647 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
648 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
649 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
651 * First calculate the timeout max according to timeout field
652 * of struct cfi_ident that probed from chip's CFI aera, if
653 * available. Specify a minimum of 2000us, in case the CFI data
656 if (cfi->cfiq->BufWriteTimeoutTyp &&
657 cfi->cfiq->BufWriteTimeoutMax)
658 cfi->chips[i].buffer_write_time_max =
659 1 << (cfi->cfiq->BufWriteTimeoutTyp +
660 cfi->cfiq->BufWriteTimeoutMax);
662 cfi->chips[i].buffer_write_time_max = 0;
664 cfi->chips[i].buffer_write_time_max =
665 max(cfi->chips[i].buffer_write_time_max, 2000);
667 cfi->chips[i].ref_point_counter = 0;
668 init_waitqueue_head(&(cfi->chips[i].wq));
671 map->fldrv = &cfi_amdstd_chipdrv;
673 return cfi_amdstd_setup(mtd);
675 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
676 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
677 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
678 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
679 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
681 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
683 struct map_info *map = mtd->priv;
684 struct cfi_private *cfi = map->fldrv_priv;
685 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
686 unsigned long offset = 0;
689 printk(KERN_NOTICE "number of %s chips: %d\n",
690 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
691 /* Select the correct geometry setup */
692 mtd->size = devsize * cfi->numchips;
694 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
695 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
696 * mtd->numeraseregions, GFP_KERNEL);
697 if (!mtd->eraseregions)
700 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
701 unsigned long ernum, ersize;
702 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
703 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
705 if (mtd->erasesize < ersize) {
706 mtd->erasesize = ersize;
708 for (j=0; j<cfi->numchips; j++) {
709 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
710 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
711 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
713 offset += (ersize * ernum);
715 if (offset != devsize) {
717 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
721 __module_get(THIS_MODULE);
722 register_reboot_notifier(&mtd->reboot_notifier);
726 kfree(mtd->eraseregions);
728 kfree(cfi->cmdset_priv);
733 * Return true if the chip is ready.
735 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
736 * non-suspended sector) and is indicated by no toggle bits toggling.
738 * Note that anything more complicated than checking if no bits are toggling
739 * (including checking DQ5 for an error status) is tricky to get working
740 * correctly and is therefore not done (particularly with interleaved chips
741 * as each chip must be checked independently of the others).
743 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
747 d = map_read(map, addr);
748 t = map_read(map, addr);
750 return map_word_equal(map, d, t);
754 * Return true if the chip is ready and has the correct value.
756 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
757 * non-suspended sector) and it is indicated by no bits toggling.
759 * Error are indicated by toggling bits or bits held with the wrong value,
760 * or with bits toggling.
762 * Note that anything more complicated than checking if no bits are toggling
763 * (including checking DQ5 for an error status) is tricky to get working
764 * correctly and is therefore not done (particularly with interleaved chips
765 * as each chip must be checked independently of the others).
768 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
772 oldd = map_read(map, addr);
773 curd = map_read(map, addr);
775 return map_word_equal(map, oldd, curd) &&
776 map_word_equal(map, curd, expected);
779 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
781 DECLARE_WAITQUEUE(wait, current);
782 struct cfi_private *cfi = map->fldrv_priv;
784 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
787 timeo = jiffies + HZ;
789 switch (chip->state) {
793 if (chip_ready(map, adr))
796 if (time_after(jiffies, timeo)) {
797 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
800 mutex_unlock(&chip->mutex);
802 mutex_lock(&chip->mutex);
803 /* Someone else might have been playing with it. */
813 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
814 !(mode == FL_READY || mode == FL_POINT ||
815 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
818 /* Do not allow suspend iff read/write to EB address */
819 if ((adr & chip->in_progress_block_mask) ==
820 chip->in_progress_block_addr)
824 /* It's harmless to issue the Erase-Suspend and Erase-Resume
825 * commands when the erase algorithm isn't in progress. */
826 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
827 chip->oldstate = FL_ERASING;
828 chip->state = FL_ERASE_SUSPENDING;
829 chip->erase_suspended = 1;
831 if (chip_ready(map, adr))
834 if (time_after(jiffies, timeo)) {
835 /* Should have suspended the erase by now.
836 * Send an Erase-Resume command as either
837 * there was an error (so leave the erase
838 * routine to recover from it) or we trying to
839 * use the erase-in-progress sector. */
840 put_chip(map, chip, adr);
841 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
845 mutex_unlock(&chip->mutex);
847 mutex_lock(&chip->mutex);
848 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
849 So we can just loop here. */
851 chip->state = FL_READY;
854 case FL_XIP_WHILE_ERASING:
855 if (mode != FL_READY && mode != FL_POINT &&
856 (!cfip || !(cfip->EraseSuspend&2)))
858 chip->oldstate = chip->state;
859 chip->state = FL_READY;
863 /* The machine is rebooting */
867 /* Only if there's no operation suspended... */
868 if (mode == FL_READY && chip->oldstate == FL_READY)
873 set_current_state(TASK_UNINTERRUPTIBLE);
874 add_wait_queue(&chip->wq, &wait);
875 mutex_unlock(&chip->mutex);
877 remove_wait_queue(&chip->wq, &wait);
878 mutex_lock(&chip->mutex);
884 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
886 struct cfi_private *cfi = map->fldrv_priv;
888 switch(chip->oldstate) {
890 cfi_fixup_m29ew_erase_suspend(map,
891 chip->in_progress_block_addr);
892 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
893 cfi_fixup_m29ew_delay_after_resume(cfi);
894 chip->oldstate = FL_READY;
895 chip->state = FL_ERASING;
898 case FL_XIP_WHILE_ERASING:
899 chip->state = chip->oldstate;
900 chip->oldstate = FL_READY;
907 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
912 #ifdef CONFIG_MTD_XIP
915 * No interrupt what so ever can be serviced while the flash isn't in array
916 * mode. This is ensured by the xip_disable() and xip_enable() functions
917 * enclosing any code path where the flash is known not to be in array mode.
918 * And within a XIP disabled code path, only functions marked with __xipram
919 * may be called and nothing else (it's a good thing to inspect generated
920 * assembly to make sure inline functions were actually inlined and that gcc
921 * didn't emit calls to its own support functions). Also configuring MTD CFI
922 * support to a single buswidth and a single interleave is also recommended.
925 static void xip_disable(struct map_info *map, struct flchip *chip,
928 /* TODO: chips with no XIP use should ignore and return */
929 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
933 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
936 struct cfi_private *cfi = map->fldrv_priv;
938 if (chip->state != FL_POINT && chip->state != FL_READY) {
939 map_write(map, CMD(0xf0), adr);
940 chip->state = FL_READY;
942 (void) map_read(map, adr);
948 * When a delay is required for the flash operation to complete, the
949 * xip_udelay() function is polling for both the given timeout and pending
950 * (but still masked) hardware interrupts. Whenever there is an interrupt
951 * pending then the flash erase operation is suspended, array mode restored
952 * and interrupts unmasked. Task scheduling might also happen at that
953 * point. The CPU eventually returns from the interrupt or the call to
954 * schedule() and the suspended flash operation is resumed for the remaining
955 * of the delay period.
957 * Warning: this function _will_ fool interrupt latency tracing tools.
960 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
961 unsigned long adr, int usec)
963 struct cfi_private *cfi = map->fldrv_priv;
964 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
965 map_word status, OK = CMD(0x80);
966 unsigned long suspended, start = xip_currtime();
971 if (xip_irqpending() && extp &&
972 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
973 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
975 * Let's suspend the erase operation when supported.
976 * Note that we currently don't try to suspend
977 * interleaved chips if there is already another
978 * operation suspended (imagine what happens
979 * when one chip was already done with the current
980 * operation while another chip suspended it, then
981 * we resume the whole thing at once). Yes, it
984 map_write(map, CMD(0xb0), adr);
985 usec -= xip_elapsed_since(start);
986 suspended = xip_currtime();
988 if (xip_elapsed_since(suspended) > 100000) {
990 * The chip doesn't want to suspend
991 * after waiting for 100 msecs.
992 * This is a critical error but there
993 * is not much we can do here.
997 status = map_read(map, adr);
998 } while (!map_word_andequal(map, status, OK, OK));
1000 /* Suspend succeeded */
1001 oldstate = chip->state;
1002 if (!map_word_bitsset(map, status, CMD(0x40)))
1004 chip->state = FL_XIP_WHILE_ERASING;
1005 chip->erase_suspended = 1;
1006 map_write(map, CMD(0xf0), adr);
1007 (void) map_read(map, adr);
1010 mutex_unlock(&chip->mutex);
1015 * We're back. However someone else might have
1016 * decided to go write to the chip if we are in
1017 * a suspended erase state. If so let's wait
1020 mutex_lock(&chip->mutex);
1021 while (chip->state != FL_XIP_WHILE_ERASING) {
1022 DECLARE_WAITQUEUE(wait, current);
1023 set_current_state(TASK_UNINTERRUPTIBLE);
1024 add_wait_queue(&chip->wq, &wait);
1025 mutex_unlock(&chip->mutex);
1027 remove_wait_queue(&chip->wq, &wait);
1028 mutex_lock(&chip->mutex);
1030 /* Disallow XIP again */
1031 local_irq_disable();
1033 /* Correct Erase Suspend Hangups for M29EW */
1034 cfi_fixup_m29ew_erase_suspend(map, adr);
1035 /* Resume the write or erase operation */
1036 map_write(map, cfi->sector_erase_cmd, adr);
1037 chip->state = oldstate;
1038 start = xip_currtime();
1039 } else if (usec >= 1000000/HZ) {
1041 * Try to save on CPU power when waiting delay
1042 * is at least a system timer tick period.
1043 * No need to be extremely accurate here.
1047 status = map_read(map, adr);
1048 } while (!map_word_andequal(map, status, OK, OK)
1049 && xip_elapsed_since(start) < usec);
1052 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1055 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1056 * the flash is actively programming or erasing since we have to poll for
1057 * the operation to complete anyway. We can't do that in a generic way with
1058 * a XIP setup so do it before the actual flash operation in this case
1059 * and stub it out from INVALIDATE_CACHE_UDELAY.
1061 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1062 INVALIDATE_CACHED_RANGE(map, from, size)
1064 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1065 UDELAY(map, chip, adr, usec)
1070 * Activating this XIP support changes the way the code works a bit. For
1071 * example the code to suspend the current process when concurrent access
1072 * happens is never executed because xip_udelay() will always return with the
1073 * same chip state as it was entered with. This is why there is no care for
1074 * the presence of add_wait_queue() or schedule() calls from within a couple
1075 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1076 * The queueing and scheduling are always happening within xip_udelay().
1078 * Similarly, get_chip() and put_chip() just happen to always be executed
1079 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1080 * is in array mode, therefore never executing many cases therein and not
1081 * causing any problem with XIP.
1086 #define xip_disable(map, chip, adr)
1087 #define xip_enable(map, chip, adr)
1088 #define XIP_INVAL_CACHED_RANGE(x...)
1090 #define UDELAY(map, chip, adr, usec) \
1092 mutex_unlock(&chip->mutex); \
1094 mutex_lock(&chip->mutex); \
1097 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1099 mutex_unlock(&chip->mutex); \
1100 INVALIDATE_CACHED_RANGE(map, adr, len); \
1102 mutex_lock(&chip->mutex); \
1107 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1109 unsigned long cmd_addr;
1110 struct cfi_private *cfi = map->fldrv_priv;
1115 /* Ensure cmd read/writes are aligned. */
1116 cmd_addr = adr & ~(map_bankwidth(map)-1);
1118 mutex_lock(&chip->mutex);
1119 ret = get_chip(map, chip, cmd_addr, FL_READY);
1121 mutex_unlock(&chip->mutex);
1125 if (chip->state != FL_POINT && chip->state != FL_READY) {
1126 map_write(map, CMD(0xf0), cmd_addr);
1127 chip->state = FL_READY;
1130 map_copy_from(map, buf, adr, len);
1132 put_chip(map, chip, cmd_addr);
1134 mutex_unlock(&chip->mutex);
1139 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1141 struct map_info *map = mtd->priv;
1142 struct cfi_private *cfi = map->fldrv_priv;
1147 /* ofs: offset within the first chip that the first read should start */
1148 chipnum = (from >> cfi->chipshift);
1149 ofs = from - (chipnum << cfi->chipshift);
1152 unsigned long thislen;
1154 if (chipnum >= cfi->numchips)
1157 if ((len + ofs -1) >> cfi->chipshift)
1158 thislen = (1<<cfi->chipshift) - ofs;
1162 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1176 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1177 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1179 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1180 loff_t adr, size_t len)
1182 struct cfi_private *cfi = map->fldrv_priv;
1184 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1185 cfi->device_type, NULL);
1186 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1187 cfi->device_type, NULL);
1188 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1189 cfi->device_type, NULL);
1191 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1194 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1195 loff_t adr, size_t len)
1197 struct cfi_private *cfi = map->fldrv_priv;
1199 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1200 cfi->device_type, NULL);
1201 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1202 cfi->device_type, NULL);
1203 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1204 cfi->device_type, NULL);
1205 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1206 cfi->device_type, NULL);
1208 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1211 static inline int do_read_secsi_onechip(struct map_info *map,
1212 struct flchip *chip, loff_t adr,
1213 size_t len, u_char *buf,
1216 DECLARE_WAITQUEUE(wait, current);
1217 unsigned long timeo = jiffies + HZ;
1220 mutex_lock(&chip->mutex);
1222 if (chip->state != FL_READY){
1223 set_current_state(TASK_UNINTERRUPTIBLE);
1224 add_wait_queue(&chip->wq, &wait);
1226 mutex_unlock(&chip->mutex);
1229 remove_wait_queue(&chip->wq, &wait);
1230 timeo = jiffies + HZ;
1237 chip->state = FL_READY;
1239 otp_enter(map, chip, adr, len);
1240 map_copy_from(map, buf, adr, len);
1241 otp_exit(map, chip, adr, len);
1244 mutex_unlock(&chip->mutex);
1249 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1251 struct map_info *map = mtd->priv;
1252 struct cfi_private *cfi = map->fldrv_priv;
1257 /* ofs: offset within the first chip that the first read should start */
1258 /* 8 secsi bytes per chip */
1263 unsigned long thislen;
1265 if (chipnum >= cfi->numchips)
1268 if ((len + ofs -1) >> 3)
1269 thislen = (1<<3) - ofs;
1273 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1288 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1289 unsigned long adr, map_word datum,
1292 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1293 size_t len, u_char *buf, size_t grouplen)
1297 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1298 int gap = adr - bus_ofs;
1299 int n = min_t(int, len, map_bankwidth(map) - gap);
1300 map_word datum = map_word_ff(map);
1302 if (n != map_bankwidth(map)) {
1303 /* partial write of a word, load old contents */
1304 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1305 datum = map_read(map, bus_ofs);
1306 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1309 datum = map_word_load_partial(map, datum, buf, gap, n);
1310 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1322 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1323 size_t len, u_char *buf, size_t grouplen)
1325 struct cfi_private *cfi = map->fldrv_priv;
1327 unsigned long timeo;
1330 /* make sure area matches group boundaries */
1331 if ((adr != 0) || (len != grouplen))
1334 mutex_lock(&chip->mutex);
1335 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1337 mutex_unlock(&chip->mutex);
1340 chip->state = FL_LOCKING;
1342 /* Enter lock register command */
1343 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1344 cfi->device_type, NULL);
1345 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1346 cfi->device_type, NULL);
1347 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1348 cfi->device_type, NULL);
1350 /* read lock register */
1351 lockreg = cfi_read_query(map, 0);
1353 /* set bit 0 to protect extended memory block */
1356 /* set bit 0 to protect extended memory block */
1357 /* write lock register */
1358 map_write(map, CMD(0xA0), chip->start);
1359 map_write(map, CMD(lockreg), chip->start);
1361 /* wait for chip to become ready */
1362 timeo = jiffies + msecs_to_jiffies(2);
1364 if (chip_ready(map, adr))
1367 if (time_after(jiffies, timeo)) {
1368 pr_err("Waiting for chip to be ready timed out.\n");
1372 UDELAY(map, chip, 0, 1);
1375 /* exit protection commands */
1376 map_write(map, CMD(0x90), chip->start);
1377 map_write(map, CMD(0x00), chip->start);
1379 chip->state = FL_READY;
1380 put_chip(map, chip, chip->start);
1381 mutex_unlock(&chip->mutex);
1386 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1387 size_t *retlen, u_char *buf,
1388 otp_op_t action, int user_regs)
1390 struct map_info *map = mtd->priv;
1391 struct cfi_private *cfi = map->fldrv_priv;
1392 int ofs_factor = cfi->interleave * cfi->device_type;
1395 struct flchip *chip;
1396 uint8_t otp, lockreg;
1399 size_t user_size, factory_size, otpsize;
1400 loff_t user_offset, factory_offset, otpoffset;
1401 int user_locked = 0, otplocked;
1405 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1406 chip = &cfi->chips[chipnum];
1410 /* Micron M29EW family */
1411 if (is_m29ew(cfi)) {
1414 /* check whether secsi area is factory locked
1416 mutex_lock(&chip->mutex);
1417 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1419 mutex_unlock(&chip->mutex);
1422 cfi_qry_mode_on(base, map, cfi);
1423 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1424 cfi_qry_mode_off(base, map, cfi);
1425 put_chip(map, chip, base);
1426 mutex_unlock(&chip->mutex);
1429 /* factory locked */
1431 factory_size = 0x100;
1433 /* customer lockable */
1437 mutex_lock(&chip->mutex);
1438 ret = get_chip(map, chip, base, FL_LOCKING);
1440 mutex_unlock(&chip->mutex);
1444 /* Enter lock register command */
1445 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1446 chip->start, map, cfi,
1447 cfi->device_type, NULL);
1448 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1449 chip->start, map, cfi,
1450 cfi->device_type, NULL);
1451 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1452 chip->start, map, cfi,
1453 cfi->device_type, NULL);
1454 /* read lock register */
1455 lockreg = cfi_read_query(map, 0);
1456 /* exit protection commands */
1457 map_write(map, CMD(0x90), chip->start);
1458 map_write(map, CMD(0x00), chip->start);
1459 put_chip(map, chip, chip->start);
1460 mutex_unlock(&chip->mutex);
1462 user_locked = ((lockreg & 0x01) == 0x00);
1466 otpsize = user_regs ? user_size : factory_size;
1469 otpoffset = user_regs ? user_offset : factory_offset;
1470 otplocked = user_regs ? user_locked : 1;
1473 /* return otpinfo */
1474 struct otp_info *otpinfo;
1475 len -= sizeof(*otpinfo);
1478 otpinfo = (struct otp_info *)buf;
1479 otpinfo->start = from;
1480 otpinfo->length = otpsize;
1481 otpinfo->locked = otplocked;
1482 buf += sizeof(*otpinfo);
1483 *retlen += sizeof(*otpinfo);
1485 } else if ((from < otpsize) && (len > 0)) {
1487 size = (len < otpsize - from) ? len : otpsize - from;
1488 ret = action(map, chip, otpoffset + from, size, buf,
1504 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1505 size_t *retlen, struct otp_info *buf)
1507 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1511 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1512 size_t *retlen, struct otp_info *buf)
1514 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1518 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1519 size_t len, size_t *retlen,
1522 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1523 buf, do_read_secsi_onechip, 0);
1526 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1527 size_t len, size_t *retlen,
1530 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1531 buf, do_read_secsi_onechip, 1);
1534 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1535 size_t len, size_t *retlen,
1538 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1542 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1546 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1550 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1551 unsigned long adr, map_word datum,
1554 struct cfi_private *cfi = map->fldrv_priv;
1555 unsigned long timeo = jiffies + HZ;
1557 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1558 * have a max write time of a few hundreds usec). However, we should
1559 * use the maximum timeout value given by the chip at probe time
1560 * instead. Unfortunately, struct flchip does have a field for
1561 * maximum timeout, only for typical which can be far too short
1562 * depending of the conditions. The ' + 1' is to avoid having a
1563 * timeout of 0 jiffies if HZ is smaller than 1000.
1565 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1572 mutex_lock(&chip->mutex);
1573 ret = get_chip(map, chip, adr, mode);
1575 mutex_unlock(&chip->mutex);
1579 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1580 __func__, adr, datum.x[0] );
1582 if (mode == FL_OTP_WRITE)
1583 otp_enter(map, chip, adr, map_bankwidth(map));
1586 * Check for a NOP for the case when the datum to write is already
1587 * present - it saves time and works around buggy chips that corrupt
1588 * data at other locations when 0xff is written to a location that
1589 * already contains 0xff.
1591 oldd = map_read(map, adr);
1592 if (map_word_equal(map, oldd, datum)) {
1593 pr_debug("MTD %s(): NOP\n",
1598 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1600 xip_disable(map, chip, adr);
1603 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1604 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1605 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1606 map_write(map, datum, adr);
1609 INVALIDATE_CACHE_UDELAY(map, chip,
1610 adr, map_bankwidth(map),
1611 chip->word_write_time);
1613 /* See comment above for timeout value. */
1614 timeo = jiffies + uWriteTimeout;
1616 if (chip->state != mode) {
1617 /* Someone's suspended the write. Sleep */
1618 DECLARE_WAITQUEUE(wait, current);
1620 set_current_state(TASK_UNINTERRUPTIBLE);
1621 add_wait_queue(&chip->wq, &wait);
1622 mutex_unlock(&chip->mutex);
1624 remove_wait_queue(&chip->wq, &wait);
1625 timeo = jiffies + (HZ / 2); /* FIXME */
1626 mutex_lock(&chip->mutex);
1631 * We check "time_after" and "!chip_good" before checking
1632 * "chip_good" to avoid the failure due to scheduling.
1634 if (time_after(jiffies, timeo) && !chip_good(map, adr, datum)) {
1635 xip_enable(map, chip, adr);
1636 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1637 xip_disable(map, chip, adr);
1642 if (chip_good(map, adr, datum))
1645 /* Latency issues. Drop the lock, wait a while and retry */
1646 UDELAY(map, chip, adr, 1);
1649 /* Did we succeed? */
1651 /* reset on all failures. */
1652 map_write( map, CMD(0xF0), chip->start );
1653 /* FIXME - should have reset delay before continuing */
1655 if (++retry_cnt <= MAX_RETRIES) {
1660 xip_enable(map, chip, adr);
1662 if (mode == FL_OTP_WRITE)
1663 otp_exit(map, chip, adr, map_bankwidth(map));
1664 chip->state = FL_READY;
1666 put_chip(map, chip, adr);
1667 mutex_unlock(&chip->mutex);
1673 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1674 size_t *retlen, const u_char *buf)
1676 struct map_info *map = mtd->priv;
1677 struct cfi_private *cfi = map->fldrv_priv;
1680 unsigned long ofs, chipstart;
1681 DECLARE_WAITQUEUE(wait, current);
1683 chipnum = to >> cfi->chipshift;
1684 ofs = to - (chipnum << cfi->chipshift);
1685 chipstart = cfi->chips[chipnum].start;
1687 /* If it's not bus-aligned, do the first byte write */
1688 if (ofs & (map_bankwidth(map)-1)) {
1689 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1690 int i = ofs - bus_ofs;
1695 mutex_lock(&cfi->chips[chipnum].mutex);
1697 if (cfi->chips[chipnum].state != FL_READY) {
1698 set_current_state(TASK_UNINTERRUPTIBLE);
1699 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1701 mutex_unlock(&cfi->chips[chipnum].mutex);
1704 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1708 /* Load 'tmp_buf' with old contents of flash */
1709 tmp_buf = map_read(map, bus_ofs+chipstart);
1711 mutex_unlock(&cfi->chips[chipnum].mutex);
1713 /* Number of bytes to copy from buffer */
1714 n = min_t(int, len, map_bankwidth(map)-i);
1716 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1718 ret = do_write_oneword(map, &cfi->chips[chipnum],
1719 bus_ofs, tmp_buf, FL_WRITING);
1728 if (ofs >> cfi->chipshift) {
1731 if (chipnum == cfi->numchips)
1736 /* We are now aligned, write as much as possible */
1737 while(len >= map_bankwidth(map)) {
1740 datum = map_word_load(map, buf);
1742 ret = do_write_oneword(map, &cfi->chips[chipnum],
1743 ofs, datum, FL_WRITING);
1747 ofs += map_bankwidth(map);
1748 buf += map_bankwidth(map);
1749 (*retlen) += map_bankwidth(map);
1750 len -= map_bankwidth(map);
1752 if (ofs >> cfi->chipshift) {
1755 if (chipnum == cfi->numchips)
1757 chipstart = cfi->chips[chipnum].start;
1761 /* Write the trailing bytes if any */
1762 if (len & (map_bankwidth(map)-1)) {
1766 mutex_lock(&cfi->chips[chipnum].mutex);
1768 if (cfi->chips[chipnum].state != FL_READY) {
1769 set_current_state(TASK_UNINTERRUPTIBLE);
1770 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1772 mutex_unlock(&cfi->chips[chipnum].mutex);
1775 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1779 tmp_buf = map_read(map, ofs + chipstart);
1781 mutex_unlock(&cfi->chips[chipnum].mutex);
1783 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1785 ret = do_write_oneword(map, &cfi->chips[chipnum],
1786 ofs, tmp_buf, FL_WRITING);
1798 * FIXME: interleaved mode not tested, and probably not supported!
1800 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1801 unsigned long adr, const u_char *buf,
1804 struct cfi_private *cfi = map->fldrv_priv;
1805 unsigned long timeo = jiffies + HZ;
1807 * Timeout is calculated according to CFI data, if available.
1808 * See more comments in cfi_cmdset_0002().
1810 unsigned long uWriteTimeout =
1811 usecs_to_jiffies(chip->buffer_write_time_max);
1813 unsigned long cmd_adr;
1820 mutex_lock(&chip->mutex);
1821 ret = get_chip(map, chip, adr, FL_WRITING);
1823 mutex_unlock(&chip->mutex);
1827 datum = map_word_load(map, buf);
1829 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1830 __func__, adr, datum.x[0] );
1832 XIP_INVAL_CACHED_RANGE(map, adr, len);
1834 xip_disable(map, chip, cmd_adr);
1836 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1837 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1839 /* Write Buffer Load */
1840 map_write(map, CMD(0x25), cmd_adr);
1842 chip->state = FL_WRITING_TO_BUFFER;
1844 /* Write length of data to come */
1845 words = len / map_bankwidth(map);
1846 map_write(map, CMD(words - 1), cmd_adr);
1849 while(z < words * map_bankwidth(map)) {
1850 datum = map_word_load(map, buf);
1851 map_write(map, datum, adr + z);
1853 z += map_bankwidth(map);
1854 buf += map_bankwidth(map);
1856 z -= map_bankwidth(map);
1860 /* Write Buffer Program Confirm: GO GO GO */
1861 map_write(map, CMD(0x29), cmd_adr);
1862 chip->state = FL_WRITING;
1864 INVALIDATE_CACHE_UDELAY(map, chip,
1865 adr, map_bankwidth(map),
1866 chip->word_write_time);
1868 timeo = jiffies + uWriteTimeout;
1871 if (chip->state != FL_WRITING) {
1872 /* Someone's suspended the write. Sleep */
1873 DECLARE_WAITQUEUE(wait, current);
1875 set_current_state(TASK_UNINTERRUPTIBLE);
1876 add_wait_queue(&chip->wq, &wait);
1877 mutex_unlock(&chip->mutex);
1879 remove_wait_queue(&chip->wq, &wait);
1880 timeo = jiffies + (HZ / 2); /* FIXME */
1881 mutex_lock(&chip->mutex);
1886 * We check "time_after" and "!chip_good" before checking "chip_good" to avoid
1887 * the failure due to scheduling.
1889 if (time_after(jiffies, timeo) && !chip_good(map, adr, datum))
1892 if (chip_good(map, adr, datum)) {
1893 xip_enable(map, chip, adr);
1897 /* Latency issues. Drop the lock, wait a while and retry */
1898 UDELAY(map, chip, adr, 1);
1902 * Recovery from write-buffer programming failures requires
1903 * the write-to-buffer-reset sequence. Since the last part
1904 * of the sequence also works as a normal reset, we can run
1905 * the same commands regardless of why we are here.
1907 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
1909 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1910 cfi->device_type, NULL);
1911 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1912 cfi->device_type, NULL);
1913 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
1914 cfi->device_type, NULL);
1915 xip_enable(map, chip, adr);
1916 /* FIXME - should have reset delay before continuing */
1918 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n",
1923 chip->state = FL_READY;
1925 put_chip(map, chip, adr);
1926 mutex_unlock(&chip->mutex);
1932 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1933 size_t *retlen, const u_char *buf)
1935 struct map_info *map = mtd->priv;
1936 struct cfi_private *cfi = map->fldrv_priv;
1937 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1942 chipnum = to >> cfi->chipshift;
1943 ofs = to - (chipnum << cfi->chipshift);
1945 /* If it's not bus-aligned, do the first word write */
1946 if (ofs & (map_bankwidth(map)-1)) {
1947 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1948 if (local_len > len)
1950 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1951 local_len, retlen, buf);
1958 if (ofs >> cfi->chipshift) {
1961 if (chipnum == cfi->numchips)
1966 /* Write buffer is worth it only if more than one word to write... */
1967 while (len >= map_bankwidth(map) * 2) {
1968 /* We must not cross write block boundaries */
1969 int size = wbufsize - (ofs & (wbufsize-1));
1973 if (size % map_bankwidth(map))
1974 size -= size % map_bankwidth(map);
1976 ret = do_write_buffer(map, &cfi->chips[chipnum],
1986 if (ofs >> cfi->chipshift) {
1989 if (chipnum == cfi->numchips)
1995 size_t retlen_dregs = 0;
1997 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1998 len, &retlen_dregs, buf);
2000 *retlen += retlen_dregs;
2008 * Wait for the flash chip to become ready to write data
2010 * This is only called during the panic_write() path. When panic_write()
2011 * is called, the kernel is in the process of a panic, and will soon be
2012 * dead. Therefore we don't take any locks, and attempt to get access
2013 * to the chip as soon as possible.
2015 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2018 struct cfi_private *cfi = map->fldrv_priv;
2023 * If the driver thinks the chip is idle, and no toggle bits
2024 * are changing, then the chip is actually idle for sure.
2026 if (chip->state == FL_READY && chip_ready(map, adr))
2030 * Try several times to reset the chip and then wait for it
2031 * to become idle. The upper limit of a few milliseconds of
2032 * delay isn't a big problem: the kernel is dying anyway. It
2033 * is more important to save the messages.
2035 while (retries > 0) {
2036 const unsigned long timeo = (HZ / 1000) + 1;
2038 /* send the reset command */
2039 map_write(map, CMD(0xF0), chip->start);
2041 /* wait for the chip to become ready */
2042 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2043 if (chip_ready(map, adr))
2052 /* the chip never became ready */
2057 * Write out one word of data to a single flash chip during a kernel panic
2059 * This is only called during the panic_write() path. When panic_write()
2060 * is called, the kernel is in the process of a panic, and will soon be
2061 * dead. Therefore we don't take any locks, and attempt to get access
2062 * to the chip as soon as possible.
2064 * The implementation of this routine is intentionally similar to
2065 * do_write_oneword(), in order to ease code maintenance.
2067 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2068 unsigned long adr, map_word datum)
2070 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2071 struct cfi_private *cfi = map->fldrv_priv;
2079 ret = cfi_amdstd_panic_wait(map, chip, adr);
2083 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2084 __func__, adr, datum.x[0]);
2087 * Check for a NOP for the case when the datum to write is already
2088 * present - it saves time and works around buggy chips that corrupt
2089 * data at other locations when 0xff is written to a location that
2090 * already contains 0xff.
2092 oldd = map_read(map, adr);
2093 if (map_word_equal(map, oldd, datum)) {
2094 pr_debug("MTD %s(): NOP\n", __func__);
2101 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2102 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2103 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2104 map_write(map, datum, adr);
2106 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2107 if (chip_ready(map, adr))
2113 if (!chip_good(map, adr, datum)) {
2114 /* reset on all failures. */
2115 map_write(map, CMD(0xF0), chip->start);
2116 /* FIXME - should have reset delay before continuing */
2118 if (++retry_cnt <= MAX_RETRIES)
2130 * Write out some data during a kernel panic
2132 * This is used by the mtdoops driver to save the dying messages from a
2133 * kernel which has panic'd.
2135 * This routine ignores all of the locking used throughout the rest of the
2136 * driver, in order to ensure that the data gets written out no matter what
2137 * state this driver (and the flash chip itself) was in when the kernel crashed.
2139 * The implementation of this routine is intentionally similar to
2140 * cfi_amdstd_write_words(), in order to ease code maintenance.
2142 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2143 size_t *retlen, const u_char *buf)
2145 struct map_info *map = mtd->priv;
2146 struct cfi_private *cfi = map->fldrv_priv;
2147 unsigned long ofs, chipstart;
2151 chipnum = to >> cfi->chipshift;
2152 ofs = to - (chipnum << cfi->chipshift);
2153 chipstart = cfi->chips[chipnum].start;
2155 /* If it's not bus aligned, do the first byte write */
2156 if (ofs & (map_bankwidth(map) - 1)) {
2157 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2158 int i = ofs - bus_ofs;
2162 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2166 /* Load 'tmp_buf' with old contents of flash */
2167 tmp_buf = map_read(map, bus_ofs + chipstart);
2169 /* Number of bytes to copy from buffer */
2170 n = min_t(int, len, map_bankwidth(map) - i);
2172 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2174 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2184 if (ofs >> cfi->chipshift) {
2187 if (chipnum == cfi->numchips)
2192 /* We are now aligned, write as much as possible */
2193 while (len >= map_bankwidth(map)) {
2196 datum = map_word_load(map, buf);
2198 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2203 ofs += map_bankwidth(map);
2204 buf += map_bankwidth(map);
2205 (*retlen) += map_bankwidth(map);
2206 len -= map_bankwidth(map);
2208 if (ofs >> cfi->chipshift) {
2211 if (chipnum == cfi->numchips)
2214 chipstart = cfi->chips[chipnum].start;
2218 /* Write the trailing bytes if any */
2219 if (len & (map_bankwidth(map) - 1)) {
2222 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2226 tmp_buf = map_read(map, ofs + chipstart);
2228 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2230 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2243 * Handle devices with one erase region, that only implement
2244 * the chip erase command.
2246 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2248 struct cfi_private *cfi = map->fldrv_priv;
2249 unsigned long timeo = jiffies + HZ;
2250 unsigned long int adr;
2251 DECLARE_WAITQUEUE(wait, current);
2255 adr = cfi->addr_unlock1;
2257 mutex_lock(&chip->mutex);
2258 ret = get_chip(map, chip, adr, FL_WRITING);
2260 mutex_unlock(&chip->mutex);
2264 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2265 __func__, chip->start );
2267 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2269 xip_disable(map, chip, adr);
2272 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2273 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2274 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2275 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2276 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2277 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2279 chip->state = FL_ERASING;
2280 chip->erase_suspended = 0;
2281 chip->in_progress_block_addr = adr;
2282 chip->in_progress_block_mask = ~(map->size - 1);
2284 INVALIDATE_CACHE_UDELAY(map, chip,
2286 chip->erase_time*500);
2288 timeo = jiffies + (HZ*20);
2291 if (chip->state != FL_ERASING) {
2292 /* Someone's suspended the erase. Sleep */
2293 set_current_state(TASK_UNINTERRUPTIBLE);
2294 add_wait_queue(&chip->wq, &wait);
2295 mutex_unlock(&chip->mutex);
2297 remove_wait_queue(&chip->wq, &wait);
2298 mutex_lock(&chip->mutex);
2301 if (chip->erase_suspended) {
2302 /* This erase was suspended and resumed.
2303 Adjust the timeout */
2304 timeo = jiffies + (HZ*20); /* FIXME */
2305 chip->erase_suspended = 0;
2308 if (chip_good(map, adr, map_word_ff(map)))
2311 if (time_after(jiffies, timeo)) {
2312 printk(KERN_WARNING "MTD %s(): software timeout\n",
2318 /* Latency issues. Drop the lock, wait a while and retry */
2319 UDELAY(map, chip, adr, 1000000/HZ);
2321 /* Did we succeed? */
2323 /* reset on all failures. */
2324 map_write( map, CMD(0xF0), chip->start );
2325 /* FIXME - should have reset delay before continuing */
2327 if (++retry_cnt <= MAX_RETRIES) {
2333 chip->state = FL_READY;
2334 xip_enable(map, chip, adr);
2336 put_chip(map, chip, adr);
2337 mutex_unlock(&chip->mutex);
2343 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2345 struct cfi_private *cfi = map->fldrv_priv;
2346 unsigned long timeo = jiffies + HZ;
2347 DECLARE_WAITQUEUE(wait, current);
2353 mutex_lock(&chip->mutex);
2354 ret = get_chip(map, chip, adr, FL_ERASING);
2356 mutex_unlock(&chip->mutex);
2360 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2363 XIP_INVAL_CACHED_RANGE(map, adr, len);
2365 xip_disable(map, chip, adr);
2368 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2369 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2370 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2371 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2372 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2373 map_write(map, cfi->sector_erase_cmd, adr);
2375 chip->state = FL_ERASING;
2376 chip->erase_suspended = 0;
2377 chip->in_progress_block_addr = adr;
2378 chip->in_progress_block_mask = ~(len - 1);
2380 INVALIDATE_CACHE_UDELAY(map, chip,
2382 chip->erase_time*500);
2384 timeo = jiffies + (HZ*20);
2387 if (chip->state != FL_ERASING) {
2388 /* Someone's suspended the erase. Sleep */
2389 set_current_state(TASK_UNINTERRUPTIBLE);
2390 add_wait_queue(&chip->wq, &wait);
2391 mutex_unlock(&chip->mutex);
2393 remove_wait_queue(&chip->wq, &wait);
2394 mutex_lock(&chip->mutex);
2397 if (chip->erase_suspended) {
2398 /* This erase was suspended and resumed.
2399 Adjust the timeout */
2400 timeo = jiffies + (HZ*20); /* FIXME */
2401 chip->erase_suspended = 0;
2404 if (chip_good(map, adr, map_word_ff(map))) {
2405 xip_enable(map, chip, adr);
2409 if (time_after(jiffies, timeo)) {
2410 xip_enable(map, chip, adr);
2411 printk(KERN_WARNING "MTD %s(): software timeout\n",
2417 /* Latency issues. Drop the lock, wait a while and retry */
2418 UDELAY(map, chip, adr, 1000000/HZ);
2420 /* Did we succeed? */
2422 /* reset on all failures. */
2423 map_write( map, CMD(0xF0), chip->start );
2424 /* FIXME - should have reset delay before continuing */
2426 if (++retry_cnt <= MAX_RETRIES) {
2432 chip->state = FL_READY;
2434 put_chip(map, chip, adr);
2435 mutex_unlock(&chip->mutex);
2440 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2442 unsigned long ofs, len;
2448 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
2452 instr->state = MTD_ERASE_DONE;
2453 mtd_erase_callback(instr);
2459 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2461 struct map_info *map = mtd->priv;
2462 struct cfi_private *cfi = map->fldrv_priv;
2465 if (instr->addr != 0)
2468 if (instr->len != mtd->size)
2471 ret = do_erase_chip(map, &cfi->chips[0]);
2475 instr->state = MTD_ERASE_DONE;
2476 mtd_erase_callback(instr);
2481 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2482 unsigned long adr, int len, void *thunk)
2484 struct cfi_private *cfi = map->fldrv_priv;
2487 mutex_lock(&chip->mutex);
2488 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2491 chip->state = FL_LOCKING;
2493 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2495 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2496 cfi->device_type, NULL);
2497 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2498 cfi->device_type, NULL);
2499 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2500 cfi->device_type, NULL);
2501 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2502 cfi->device_type, NULL);
2503 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2504 cfi->device_type, NULL);
2505 map_write(map, CMD(0x40), chip->start + adr);
2507 chip->state = FL_READY;
2508 put_chip(map, chip, adr + chip->start);
2512 mutex_unlock(&chip->mutex);
2516 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2517 unsigned long adr, int len, void *thunk)
2519 struct cfi_private *cfi = map->fldrv_priv;
2522 mutex_lock(&chip->mutex);
2523 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2526 chip->state = FL_UNLOCKING;
2528 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2530 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2531 cfi->device_type, NULL);
2532 map_write(map, CMD(0x70), adr);
2534 chip->state = FL_READY;
2535 put_chip(map, chip, adr + chip->start);
2539 mutex_unlock(&chip->mutex);
2543 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2545 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2548 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2550 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2554 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2558 struct flchip *chip;
2563 #define MAX_SECTORS 512
2565 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2566 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2567 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2569 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2570 struct flchip *chip,
2571 unsigned long adr, int len, void *thunk)
2573 struct cfi_private *cfi = map->fldrv_priv;
2574 unsigned long timeo;
2578 mutex_lock(&chip->mutex);
2579 ret = get_chip(map, chip, adr, FL_LOCKING);
2581 mutex_unlock(&chip->mutex);
2585 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2587 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2588 cfi->device_type, NULL);
2589 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2590 cfi->device_type, NULL);
2591 /* PPB entry command */
2592 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2593 cfi->device_type, NULL);
2595 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2596 chip->state = FL_LOCKING;
2597 map_write(map, CMD(0xA0), adr);
2598 map_write(map, CMD(0x00), adr);
2599 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2601 * Unlocking of one specific sector is not supported, so we
2602 * have to unlock all sectors of this device instead
2604 chip->state = FL_UNLOCKING;
2605 map_write(map, CMD(0x80), chip->start);
2606 map_write(map, CMD(0x30), chip->start);
2607 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2608 chip->state = FL_JEDEC_QUERY;
2609 /* Return locked status: 0->locked, 1->unlocked */
2610 ret = !cfi_read_query(map, adr);
2615 * Wait for some time as unlocking of all sectors takes quite long
2617 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2619 if (chip_ready(map, adr))
2622 if (time_after(jiffies, timeo)) {
2623 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2628 UDELAY(map, chip, adr, 1);
2631 /* Exit BC commands */
2632 map_write(map, CMD(0x90), chip->start);
2633 map_write(map, CMD(0x00), chip->start);
2635 chip->state = FL_READY;
2636 put_chip(map, chip, adr);
2637 mutex_unlock(&chip->mutex);
2642 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2645 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2646 DO_XXLOCK_ONEBLOCK_LOCK);
2649 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2652 struct mtd_erase_region_info *regions = mtd->eraseregions;
2653 struct map_info *map = mtd->priv;
2654 struct cfi_private *cfi = map->fldrv_priv;
2655 struct ppb_lock *sect;
2665 * PPB unlocking always unlocks all sectors of the flash chip.
2666 * We need to re-lock all previously locked sectors. So lets
2667 * first check the locking status of all sectors and save
2668 * it for future use.
2670 sect = kzalloc(MAX_SECTORS * sizeof(struct ppb_lock), GFP_KERNEL);
2675 * This code to walk all sectors is a slightly modified version
2676 * of the cfi_varsize_frob() code.
2686 int size = regions[i].erasesize;
2689 * Only test sectors that shall not be unlocked. The other
2690 * sectors shall be unlocked, so lets keep their locking
2691 * status at "unlocked" (locked=0) for the final re-locking.
2693 if ((offset < ofs) || (offset >= (ofs + len))) {
2694 sect[sectors].chip = &cfi->chips[chipnum];
2695 sect[sectors].adr = adr;
2696 sect[sectors].locked = do_ppb_xxlock(
2697 map, &cfi->chips[chipnum], adr, 0,
2698 DO_XXLOCK_ONEBLOCK_GETLOCK);
2705 if (offset == regions[i].offset + size * regions[i].numblocks)
2708 if (adr >> cfi->chipshift) {
2709 if (offset >= (ofs + len))
2714 if (chipnum >= cfi->numchips)
2719 if (sectors >= MAX_SECTORS) {
2720 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2727 /* Now unlock the whole chip */
2728 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2729 DO_XXLOCK_ONEBLOCK_UNLOCK);
2736 * PPB unlocking always unlocks all sectors of the flash chip.
2737 * We need to re-lock all previously locked sectors.
2739 for (i = 0; i < sectors; i++) {
2741 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
2742 DO_XXLOCK_ONEBLOCK_LOCK);
2749 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2752 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2753 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2756 static void cfi_amdstd_sync (struct mtd_info *mtd)
2758 struct map_info *map = mtd->priv;
2759 struct cfi_private *cfi = map->fldrv_priv;
2761 struct flchip *chip;
2763 DECLARE_WAITQUEUE(wait, current);
2765 for (i=0; !ret && i<cfi->numchips; i++) {
2766 chip = &cfi->chips[i];
2769 mutex_lock(&chip->mutex);
2771 switch(chip->state) {
2775 case FL_JEDEC_QUERY:
2776 chip->oldstate = chip->state;
2777 chip->state = FL_SYNCING;
2778 /* No need to wake_up() on this state change -
2779 * as the whole point is that nobody can do anything
2780 * with the chip now anyway.
2783 mutex_unlock(&chip->mutex);
2787 /* Not an idle state */
2788 set_current_state(TASK_UNINTERRUPTIBLE);
2789 add_wait_queue(&chip->wq, &wait);
2791 mutex_unlock(&chip->mutex);
2795 remove_wait_queue(&chip->wq, &wait);
2801 /* Unlock the chips again */
2803 for (i--; i >=0; i--) {
2804 chip = &cfi->chips[i];
2806 mutex_lock(&chip->mutex);
2808 if (chip->state == FL_SYNCING) {
2809 chip->state = chip->oldstate;
2812 mutex_unlock(&chip->mutex);
2817 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2819 struct map_info *map = mtd->priv;
2820 struct cfi_private *cfi = map->fldrv_priv;
2822 struct flchip *chip;
2825 for (i=0; !ret && i<cfi->numchips; i++) {
2826 chip = &cfi->chips[i];
2828 mutex_lock(&chip->mutex);
2830 switch(chip->state) {
2834 case FL_JEDEC_QUERY:
2835 chip->oldstate = chip->state;
2836 chip->state = FL_PM_SUSPENDED;
2837 /* No need to wake_up() on this state change -
2838 * as the whole point is that nobody can do anything
2839 * with the chip now anyway.
2841 case FL_PM_SUSPENDED:
2848 mutex_unlock(&chip->mutex);
2851 /* Unlock the chips again */
2854 for (i--; i >=0; i--) {
2855 chip = &cfi->chips[i];
2857 mutex_lock(&chip->mutex);
2859 if (chip->state == FL_PM_SUSPENDED) {
2860 chip->state = chip->oldstate;
2863 mutex_unlock(&chip->mutex);
2871 static void cfi_amdstd_resume(struct mtd_info *mtd)
2873 struct map_info *map = mtd->priv;
2874 struct cfi_private *cfi = map->fldrv_priv;
2876 struct flchip *chip;
2878 for (i=0; i<cfi->numchips; i++) {
2880 chip = &cfi->chips[i];
2882 mutex_lock(&chip->mutex);
2884 if (chip->state == FL_PM_SUSPENDED) {
2885 chip->state = FL_READY;
2886 map_write(map, CMD(0xF0), chip->start);
2890 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
2892 mutex_unlock(&chip->mutex);
2898 * Ensure that the flash device is put back into read array mode before
2899 * unloading the driver or rebooting. On some systems, rebooting while
2900 * the flash is in query/program/erase mode will prevent the CPU from
2901 * fetching the bootloader code, requiring a hard reset or power cycle.
2903 static int cfi_amdstd_reset(struct mtd_info *mtd)
2905 struct map_info *map = mtd->priv;
2906 struct cfi_private *cfi = map->fldrv_priv;
2908 struct flchip *chip;
2910 for (i = 0; i < cfi->numchips; i++) {
2912 chip = &cfi->chips[i];
2914 mutex_lock(&chip->mutex);
2916 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2918 map_write(map, CMD(0xF0), chip->start);
2919 chip->state = FL_SHUTDOWN;
2920 put_chip(map, chip, chip->start);
2923 mutex_unlock(&chip->mutex);
2930 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2933 struct mtd_info *mtd;
2935 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2936 cfi_amdstd_reset(mtd);
2941 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2943 struct map_info *map = mtd->priv;
2944 struct cfi_private *cfi = map->fldrv_priv;
2946 cfi_amdstd_reset(mtd);
2947 unregister_reboot_notifier(&mtd->reboot_notifier);
2948 kfree(cfi->cmdset_priv);
2951 kfree(mtd->eraseregions);
2954 MODULE_LICENSE("GPL");
2955 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2956 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2957 MODULE_ALIAS("cfi_cmdset_0006");
2958 MODULE_ALIAS("cfi_cmdset_0701");