2 * Copyright(c) 2015 - 2020 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
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13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
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21 * modification, are permitted provided that the following conditions
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44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 * This file contains all of the code that is specific to the HFI chip
52 #include <linux/pci.h>
53 #include <linux/delay.h>
54 #include <linux/interrupt.h>
55 #include <linux/module.h>
71 uint num_vls = HFI1_MAX_VLS_SUPPORTED;
72 module_param(num_vls, uint, S_IRUGO);
73 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
76 * Default time to aggregate two 10K packets from the idle state
77 * (timer not running). The timer starts at the end of the first packet,
78 * so only the time for one 10K packet and header plus a bit extra is needed.
79 * 10 * 1024 + 64 header byte = 10304 byte
80 * 10304 byte / 12.5 GB/s = 824.32ns
82 uint rcv_intr_timeout = (824 + 16); /* 16 is for coalescing interrupt */
83 module_param(rcv_intr_timeout, uint, S_IRUGO);
84 MODULE_PARM_DESC(rcv_intr_timeout, "Receive interrupt mitigation timeout in ns");
86 uint rcv_intr_count = 16; /* same as qib */
87 module_param(rcv_intr_count, uint, S_IRUGO);
88 MODULE_PARM_DESC(rcv_intr_count, "Receive interrupt mitigation count");
90 ushort link_crc_mask = SUPPORTED_CRCS;
91 module_param(link_crc_mask, ushort, S_IRUGO);
92 MODULE_PARM_DESC(link_crc_mask, "CRCs to use on the link");
95 module_param_named(loopback, loopback, uint, S_IRUGO);
96 MODULE_PARM_DESC(loopback, "Put into loopback mode (1 = serdes, 3 = external cable");
98 /* Other driver tunables */
99 uint rcv_intr_dynamic = 1; /* enable dynamic mode for rcv int mitigation*/
100 static ushort crc_14b_sideband = 1;
101 static uint use_flr = 1;
102 uint quick_linkup; /* skip LNI */
105 u64 flag; /* the flag */
106 char *str; /* description string */
107 u16 extra; /* extra information */
112 /* str must be a string constant */
113 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
114 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
116 /* Send Error Consequences */
117 #define SEC_WRITE_DROPPED 0x1
118 #define SEC_PACKET_DROPPED 0x2
119 #define SEC_SC_HALTED 0x4 /* per-context only */
120 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */
122 #define DEFAULT_KRCVQS 2
123 #define MIN_KERNEL_KCTXTS 2
124 #define FIRST_KERNEL_KCTXT 1
127 * RSM instance allocation
128 * 0 - User Fecn Handling
133 #define RSM_INS_FECN 0
134 #define RSM_INS_VNIC 1
135 #define RSM_INS_AIP 2
136 #define RSM_INS_VERBS 3
138 /* Bit offset into the GUID which carries HFI id information */
139 #define GUID_HFI_INDEX_SHIFT 39
141 /* extract the emulation revision */
142 #define emulator_rev(dd) ((dd)->irev >> 8)
143 /* parallel and serial emulation versions are 3 and 4 respectively */
144 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
145 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
147 /* RSM fields for Verbs */
149 #define IB_PACKET_TYPE 2ull
150 #define QW_SHIFT 6ull
152 #define QPN_WIDTH 7ull
154 /* LRH.BTH: QW 0, OFFSET 48 - for match */
155 #define LRH_BTH_QW 0ull
156 #define LRH_BTH_BIT_OFFSET 48ull
157 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
158 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
159 #define LRH_BTH_SELECT
160 #define LRH_BTH_MASK 3ull
161 #define LRH_BTH_VALUE 2ull
163 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
164 #define LRH_SC_QW 0ull
165 #define LRH_SC_BIT_OFFSET 56ull
166 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
167 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
168 #define LRH_SC_MASK 128ull
169 #define LRH_SC_VALUE 0ull
171 /* SC[n..0] QW 0, OFFSET 60 - for select */
172 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
174 /* QPN[m+n:1] QW 1, OFFSET 1 */
175 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
177 /* RSM fields for AIP */
178 /* LRH.BTH above is reused for this rule */
180 /* BTH.DESTQP: QW 1, OFFSET 16 for match */
181 #define BTH_DESTQP_QW 1ull
182 #define BTH_DESTQP_BIT_OFFSET 16ull
183 #define BTH_DESTQP_OFFSET(off) ((BTH_DESTQP_QW << QW_SHIFT) | (off))
184 #define BTH_DESTQP_MATCH_OFFSET BTH_DESTQP_OFFSET(BTH_DESTQP_BIT_OFFSET)
185 #define BTH_DESTQP_MASK 0xFFull
186 #define BTH_DESTQP_VALUE 0x81ull
188 /* DETH.SQPN: QW 1 Offset 56 for select */
189 /* We use 8 most significant Soure QPN bits as entropy fpr AIP */
190 #define DETH_AIP_SQPN_QW 3ull
191 #define DETH_AIP_SQPN_BIT_OFFSET 56ull
192 #define DETH_AIP_SQPN_OFFSET(off) ((DETH_AIP_SQPN_QW << QW_SHIFT) | (off))
193 #define DETH_AIP_SQPN_SELECT_OFFSET \
194 DETH_AIP_SQPN_OFFSET(DETH_AIP_SQPN_BIT_OFFSET)
196 /* RSM fields for Vnic */
197 /* L2_TYPE: QW 0, OFFSET 61 - for match */
198 #define L2_TYPE_QW 0ull
199 #define L2_TYPE_BIT_OFFSET 61ull
200 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off))
201 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET)
202 #define L2_TYPE_MASK 3ull
203 #define L2_16B_VALUE 2ull
205 /* L4_TYPE QW 1, OFFSET 0 - for match */
206 #define L4_TYPE_QW 1ull
207 #define L4_TYPE_BIT_OFFSET 0ull
208 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off))
209 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET)
210 #define L4_16B_TYPE_MASK 0xFFull
211 #define L4_16B_ETH_VALUE 0x78ull
213 /* 16B VESWID - for select */
214 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull))
215 /* 16B ENTROPY - for select */
216 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull))
218 /* defines to build power on SC2VL table */
230 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
231 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
232 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
233 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
234 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
235 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
236 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
237 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
240 #define DC_SC_VL_VAL( \
259 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
260 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
261 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
262 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
263 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
264 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
265 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
266 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
267 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
268 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
269 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
270 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
271 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
272 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
273 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
274 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
277 /* all CceStatus sub-block freeze bits */
278 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
279 | CCE_STATUS_RXE_FROZE_SMASK \
280 | CCE_STATUS_TXE_FROZE_SMASK \
281 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
282 /* all CceStatus sub-block TXE pause bits */
283 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
284 | CCE_STATUS_TXE_PAUSED_SMASK \
285 | CCE_STATUS_SDMA_PAUSED_SMASK)
286 /* all CceStatus sub-block RXE pause bits */
287 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
289 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
290 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
295 static struct flag_table cce_err_status_flags[] = {
296 /* 0*/ FLAG_ENTRY0("CceCsrParityErr",
297 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK),
298 /* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr",
299 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK),
300 /* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr",
301 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK),
302 /* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
303 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK),
304 /* 4*/ FLAG_ENTRY0("CceTrgtAccessErr",
305 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK),
306 /* 5*/ FLAG_ENTRY0("CceRspdDataParityErr",
307 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK),
308 /* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
309 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK),
310 /* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr",
311 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK),
312 /* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
313 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK),
314 /* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
315 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK),
316 /*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
317 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK),
318 /*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
319 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK),
320 /*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
321 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK),
322 /*13*/ FLAG_ENTRY0("PcicRetryMemCorErr",
323 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK),
324 /*14*/ FLAG_ENTRY0("PcicRetryMemCorErr",
325 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK),
326 /*15*/ FLAG_ENTRY0("PcicPostHdQCorErr",
327 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK),
328 /*16*/ FLAG_ENTRY0("PcicPostHdQCorErr",
329 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK),
330 /*17*/ FLAG_ENTRY0("PcicPostHdQCorErr",
331 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK),
332 /*18*/ FLAG_ENTRY0("PcicCplDatQCorErr",
333 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK),
334 /*19*/ FLAG_ENTRY0("PcicNPostHQParityErr",
335 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK),
336 /*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr",
337 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK),
338 /*21*/ FLAG_ENTRY0("PcicRetryMemUncErr",
339 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK),
340 /*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr",
341 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK),
342 /*23*/ FLAG_ENTRY0("PcicPostHdQUncErr",
343 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK),
344 /*24*/ FLAG_ENTRY0("PcicPostDatQUncErr",
345 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK),
346 /*25*/ FLAG_ENTRY0("PcicCplHdQUncErr",
347 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK),
348 /*26*/ FLAG_ENTRY0("PcicCplDatQUncErr",
349 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK),
350 /*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr",
351 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK),
352 /*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr",
353 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK),
354 /*29*/ FLAG_ENTRY0("PcicReceiveParityErr",
355 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK),
356 /*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr",
357 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK),
358 /*31*/ FLAG_ENTRY0("LATriggered",
359 CCE_ERR_STATUS_LA_TRIGGERED_SMASK),
360 /*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr",
361 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK),
362 /*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr",
363 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK),
364 /*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
365 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK),
366 /*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
367 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK),
368 /*36*/ FLAG_ENTRY0("CceMsixTableCorErr",
369 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK),
370 /*37*/ FLAG_ENTRY0("CceMsixTableUncErr",
371 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK),
372 /*38*/ FLAG_ENTRY0("CceIntMapCorErr",
373 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK),
374 /*39*/ FLAG_ENTRY0("CceIntMapUncErr",
375 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK),
376 /*40*/ FLAG_ENTRY0("CceMsixCsrParityErr",
377 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK),
384 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
385 static struct flag_table misc_err_status_flags[] = {
386 /* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
387 /* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
388 /* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
389 /* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
390 /* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
391 /* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
392 /* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
393 /* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
394 /* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
395 /* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY)),
396 /*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD)),
397 /*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL)),
398 /*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL))
402 * TXE PIO Error flags and consequences
404 static struct flag_table pio_err_status_flags[] = {
405 /* 0*/ FLAG_ENTRY("PioWriteBadCtxt",
407 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK),
408 /* 1*/ FLAG_ENTRY("PioWriteAddrParity",
410 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK),
411 /* 2*/ FLAG_ENTRY("PioCsrParity",
413 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK),
414 /* 3*/ FLAG_ENTRY("PioSbMemFifo0",
416 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK),
417 /* 4*/ FLAG_ENTRY("PioSbMemFifo1",
419 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK),
420 /* 5*/ FLAG_ENTRY("PioPccFifoParity",
422 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK),
423 /* 6*/ FLAG_ENTRY("PioPecFifoParity",
425 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK),
426 /* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity",
428 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK),
429 /* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
431 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK),
432 /* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr",
434 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK),
435 /*10*/ FLAG_ENTRY("PioSmPktResetParity",
437 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK),
438 /*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc",
440 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK),
441 /*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc",
443 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK),
444 /*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor",
446 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK),
447 /*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor",
449 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK),
450 /*15*/ FLAG_ENTRY("PioCreditRetFifoParity",
452 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK),
453 /*16*/ FLAG_ENTRY("PioPpmcPblFifo",
455 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK),
456 /*17*/ FLAG_ENTRY("PioInitSmIn",
458 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK),
459 /*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm",
461 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK),
462 /*19*/ FLAG_ENTRY("PioHostAddrMemUnc",
464 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK),
465 /*20*/ FLAG_ENTRY("PioHostAddrMemCor",
467 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK),
468 /*21*/ FLAG_ENTRY("PioWriteDataParity",
470 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK),
471 /*22*/ FLAG_ENTRY("PioStateMachine",
473 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK),
474 /*23*/ FLAG_ENTRY("PioWriteQwValidParity",
475 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
476 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK),
477 /*24*/ FLAG_ENTRY("PioBlockQwCountParity",
478 SEC_WRITE_DROPPED | SEC_SPC_FREEZE,
479 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK),
480 /*25*/ FLAG_ENTRY("PioVlfVlLenParity",
482 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK),
483 /*26*/ FLAG_ENTRY("PioVlfSopParity",
485 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK),
486 /*27*/ FLAG_ENTRY("PioVlFifoParity",
488 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK),
489 /*28*/ FLAG_ENTRY("PioPpmcBqcMemParity",
491 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK),
492 /*29*/ FLAG_ENTRY("PioPpmcSopLen",
494 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK),
496 /*32*/ FLAG_ENTRY("PioCurrentFreeCntParity",
498 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK),
499 /*33*/ FLAG_ENTRY("PioLastReturnedCntParity",
501 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK),
502 /*34*/ FLAG_ENTRY("PioPccSopHeadParity",
504 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK),
505 /*35*/ FLAG_ENTRY("PioPecSopHeadParityErr",
507 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK),
511 /* TXE PIO errors that cause an SPC freeze */
512 #define ALL_PIO_FREEZE_ERR \
513 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
514 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
515 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
516 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
517 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
518 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
519 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
520 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
521 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
522 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
523 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
524 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
525 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
526 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
527 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
528 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
529 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
530 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
531 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
532 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
533 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
534 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
535 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
536 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
537 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
538 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
539 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
540 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
541 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
544 * TXE SDMA Error flags
546 static struct flag_table sdma_err_status_flags[] = {
547 /* 0*/ FLAG_ENTRY0("SDmaRpyTagErr",
548 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK),
549 /* 1*/ FLAG_ENTRY0("SDmaCsrParityErr",
550 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK),
551 /* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
552 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK),
553 /* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
554 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK),
558 /* TXE SDMA errors that cause an SPC freeze */
559 #define ALL_SDMA_FREEZE_ERR \
560 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
561 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
562 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
564 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
565 #define PORT_DISCARD_EGRESS_ERRS \
566 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
567 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
568 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
571 * TXE Egress Error flags
573 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
574 static struct flag_table egress_err_status_flags[] = {
575 /* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR)),
576 /* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC)),
578 /* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
579 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY)),
580 /* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN)),
581 /* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE)),
583 /* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr",
584 SEES(TX_PIO_LAUNCH_INTF_PARITY)),
585 /* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
586 SEES(TX_SDMA_LAUNCH_INTF_PARITY)),
588 /*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
589 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY)),
590 /*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL)),
591 /*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY)),
592 /*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY)),
593 /*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY)),
594 /*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
595 SEES(TX_SDMA0_DISALLOWED_PACKET)),
596 /*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
597 SEES(TX_SDMA1_DISALLOWED_PACKET)),
598 /*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
599 SEES(TX_SDMA2_DISALLOWED_PACKET)),
600 /*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
601 SEES(TX_SDMA3_DISALLOWED_PACKET)),
602 /*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
603 SEES(TX_SDMA4_DISALLOWED_PACKET)),
604 /*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
605 SEES(TX_SDMA5_DISALLOWED_PACKET)),
606 /*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
607 SEES(TX_SDMA6_DISALLOWED_PACKET)),
608 /*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
609 SEES(TX_SDMA7_DISALLOWED_PACKET)),
610 /*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
611 SEES(TX_SDMA8_DISALLOWED_PACKET)),
612 /*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
613 SEES(TX_SDMA9_DISALLOWED_PACKET)),
614 /*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
615 SEES(TX_SDMA10_DISALLOWED_PACKET)),
616 /*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
617 SEES(TX_SDMA11_DISALLOWED_PACKET)),
618 /*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
619 SEES(TX_SDMA12_DISALLOWED_PACKET)),
620 /*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
621 SEES(TX_SDMA13_DISALLOWED_PACKET)),
622 /*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
623 SEES(TX_SDMA14_DISALLOWED_PACKET)),
624 /*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
625 SEES(TX_SDMA15_DISALLOWED_PACKET)),
626 /*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
627 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY)),
628 /*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
629 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY)),
630 /*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
631 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY)),
632 /*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
633 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY)),
634 /*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
635 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY)),
636 /*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
637 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY)),
638 /*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
639 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY)),
640 /*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
641 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY)),
642 /*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
643 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY)),
644 /*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY)),
645 /*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC)),
646 /*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC)),
647 /*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC)),
648 /*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC)),
649 /*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION)),
650 /*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL)),
651 /*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR)),
652 /*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR)),
653 /*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR)),
654 /*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR)),
655 /*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR)),
656 /*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR)),
657 /*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR)),
658 /*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR)),
659 /*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR)),
660 /*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN)),
661 /*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR)),
662 /*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR)),
663 /*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR)),
664 /*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR)),
665 /*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
666 SEES(TX_READ_SDMA_MEMORY_CSR_UNC)),
667 /*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
668 SEES(TX_READ_PIO_MEMORY_CSR_UNC)),
672 * TXE Egress Error Info flags
674 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
675 static struct flag_table egress_err_info_flags[] = {
676 /* 0*/ FLAG_ENTRY0("Reserved", 0ull),
677 /* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL)),
678 /* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
679 /* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY)),
680 /* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY)),
681 /* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID)),
682 /* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE)),
683 /* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING)),
684 /* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW)),
685 /* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6)),
686 /*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH)),
687 /*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS)),
688 /*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS)),
689 /*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS)),
690 /*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS)),
691 /*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS)),
692 /*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST)),
693 /*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN)),
694 /*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET)),
695 /*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS)),
696 /*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL)),
697 /*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN)),
700 /* TXE Egress errors that cause an SPC freeze */
701 #define ALL_TXE_EGRESS_FREEZE_ERR \
702 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
703 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
704 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
705 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
706 | SEES(TX_LAUNCH_CSR_PARITY) \
707 | SEES(TX_SBRD_CTL_CSR_PARITY) \
708 | SEES(TX_CONFIG_PARITY) \
709 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
710 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
711 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
712 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
713 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
714 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
715 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
716 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
717 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
718 | SEES(TX_CREDIT_RETURN_PARITY))
721 * TXE Send error flags
723 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
724 static struct flag_table send_err_status_flags[] = {
725 /* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY)),
726 /* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR)),
727 /* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR))
731 * TXE Send Context Error flags and consequences
733 static struct flag_table sc_err_status_flags[] = {
734 /* 0*/ FLAG_ENTRY("InconsistentSop",
735 SEC_PACKET_DROPPED | SEC_SC_HALTED,
736 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK),
737 /* 1*/ FLAG_ENTRY("DisallowedPacket",
738 SEC_PACKET_DROPPED | SEC_SC_HALTED,
739 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK),
740 /* 2*/ FLAG_ENTRY("WriteCrossesBoundary",
741 SEC_WRITE_DROPPED | SEC_SC_HALTED,
742 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK),
743 /* 3*/ FLAG_ENTRY("WriteOverflow",
744 SEC_WRITE_DROPPED | SEC_SC_HALTED,
745 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK),
746 /* 4*/ FLAG_ENTRY("WriteOutOfBounds",
747 SEC_WRITE_DROPPED | SEC_SC_HALTED,
748 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK),
753 * RXE Receive Error flags
755 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
756 static struct flag_table rxe_err_status_flags[] = {
757 /* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR)),
758 /* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY)),
759 /* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC)),
760 /* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR)),
761 /* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC)),
762 /* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR)),
763 /* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC)),
764 /* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR)),
765 /* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY)),
766 /* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY)),
767 /*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC)),
768 /*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR)),
769 /*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING)),
770 /*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC)),
771 /*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR)),
772 /*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC)),
773 /*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
774 RXES(RBUF_LOOKUP_DES_REG_UNC_COR)),
775 /*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC)),
776 /*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR)),
777 /*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr",
778 RXES(RBUF_BLOCK_LIST_READ_UNC)),
779 /*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr",
780 RXES(RBUF_BLOCK_LIST_READ_COR)),
781 /*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
782 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY)),
783 /*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
784 RXES(RBUF_CSR_QENT_CNT_PARITY)),
785 /*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
786 RXES(RBUF_CSR_QNEXT_BUF_PARITY)),
787 /*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
788 RXES(RBUF_CSR_QVLD_BIT_PARITY)),
789 /*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY)),
790 /*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY)),
791 /*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
792 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY)),
793 /*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY)),
794 /*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY)),
795 /*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP)),
796 /*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL)),
797 /*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY)),
798 /*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY)),
799 /*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY)),
800 /*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
801 RXES(RBUF_FL_INITDONE_PARITY)),
802 /*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
803 RXES(RBUF_FL_INIT_WR_ADDR_PARITY)),
804 /*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC)),
805 /*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR)),
806 /*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC)),
807 /*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
808 RXES(LOOKUP_DES_PART1_UNC_COR)),
809 /*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr",
810 RXES(LOOKUP_DES_PART2_PARITY)),
811 /*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC)),
812 /*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR)),
813 /*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY)),
814 /*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY)),
815 /*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM)),
816 /*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC)),
817 /*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR)),
818 /*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC)),
819 /*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR)),
820 /*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC)),
821 /*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR)),
822 /*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC)),
823 /*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR)),
824 /*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC)),
825 /*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR)),
826 /*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY)),
827 /*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING)),
828 /*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING)),
829 /*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC)),
830 /*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR)),
831 /*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR)),
832 /*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY))
835 /* RXE errors that will trigger an SPC freeze */
836 #define ALL_RXE_FREEZE_ERR \
837 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
838 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
839 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
840 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
841 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
842 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
843 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
844 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
845 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
846 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
847 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
848 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
849 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
850 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
851 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
852 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
853 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
854 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
855 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
856 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
857 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
858 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
859 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
860 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
861 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
862 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
863 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
864 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
865 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
866 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
867 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
868 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
869 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
870 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
871 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
872 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
873 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
874 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
875 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
876 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
877 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
878 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
879 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
880 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
882 #define RXE_FREEZE_ABORT_MASK \
883 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
884 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
885 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
890 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
891 static struct flag_table dcc_err_flags[] = {
892 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR)),
893 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR)),
894 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR)),
895 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR)),
896 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR)),
897 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR)),
898 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR)),
899 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR)),
900 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR)),
901 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR)),
902 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR)),
903 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE)),
904 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR)),
905 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR)),
906 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR)),
907 FLAG_ENTRY0("link_err", DCCE(LINK_ERR)),
908 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR)),
909 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR)),
910 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR)),
911 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR)),
912 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR)),
913 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR)),
914 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR)),
915 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR)),
916 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR)),
917 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR)),
918 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR)),
919 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR)),
920 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR)),
921 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR)),
922 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR)),
923 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR)),
924 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR)),
925 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR)),
926 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST)),
927 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC)),
928 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR)),
929 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR)),
930 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR)),
931 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR)),
932 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR)),
933 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR)),
934 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR)),
935 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR)),
936 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR)),
937 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR)),
943 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
944 static struct flag_table lcb_err_flags[] = {
945 /* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR)),
946 /* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR)),
947 /* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW)),
948 /* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
949 LCBE(ALL_LNS_FAILED_REINIT_TEST)),
950 /* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS)),
951 /* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS)),
952 /* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS)),
953 /* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR)),
954 /* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER)),
955 /* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE)),
956 /*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT)),
957 /*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED)),
958 /*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER)),
959 /*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
960 LCBE(UNEXPECTED_ROUND_TRIP_MARKER)),
961 /*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP)),
962 /*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING)),
963 /*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW)),
964 /*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW)),
965 /*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR)),
966 /*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
967 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE)),
968 /*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE)),
969 /*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE)),
970 /*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE)),
971 /*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE)),
972 /*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE)),
973 /*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT)),
974 /*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
975 LCBE(RST_FOR_INCOMPLT_RND_TRIP)),
976 /*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT)),
977 /*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
978 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE)),
979 /*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
980 LCBE(REDUNDANT_FLIT_PARITY_ERR))
986 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
987 static struct flag_table dc8051_err_flags[] = {
988 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051)),
989 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT)),
990 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE)),
991 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE)),
992 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE)),
993 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE)),
994 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE)),
995 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE)),
996 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
997 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES)),
998 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR)),
1002 * DC8051 Information Error flags
1004 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
1006 static struct flag_table dc8051_info_err_flags[] = {
1007 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED),
1008 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME),
1009 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET),
1010 FLAG_ENTRY0("Serdes internal loopback failure",
1011 FAILED_SERDES_INTERNAL_LOOPBACK),
1012 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT),
1013 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING),
1014 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE),
1015 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM),
1016 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ),
1017 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1),
1018 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2),
1019 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT),
1020 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT),
1021 FLAG_ENTRY0("External Device Request Timeout",
1022 EXTERNAL_DEVICE_REQ_TIMEOUT),
1026 * DC8051 Information Host Information flags
1028 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
1030 static struct flag_table dc8051_info_host_msg_flags[] = {
1031 FLAG_ENTRY0("Host request done", 0x0001),
1032 FLAG_ENTRY0("BC PWR_MGM message", 0x0002),
1033 FLAG_ENTRY0("BC SMA message", 0x0004),
1034 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
1035 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
1036 FLAG_ENTRY0("External device config request", 0x0020),
1037 FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
1038 FLAG_ENTRY0("LinkUp achieved", 0x0080),
1039 FLAG_ENTRY0("Link going down", 0x0100),
1040 FLAG_ENTRY0("Link width downgraded", 0x0200),
1043 static u32 encoded_size(u32 size);
1044 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate);
1045 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state);
1046 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
1048 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
1049 u8 *vcu, u16 *vl15buf, u8 *crc_sizes);
1050 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
1051 u8 *remote_tx_rate, u16 *link_widths);
1052 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits,
1053 u8 *flag_bits, u16 *link_widths);
1054 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
1056 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx);
1057 static int read_tx_settings(struct hfi1_devdata *dd, u8 *enable_lane_tx,
1058 u8 *tx_polarity_inversion,
1059 u8 *rx_polarity_inversion, u8 *max_rate);
1060 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
1061 unsigned int context, u64 err_status);
1062 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg);
1063 static void handle_dcc_err(struct hfi1_devdata *dd,
1064 unsigned int context, u64 err_status);
1065 static void handle_lcb_err(struct hfi1_devdata *dd,
1066 unsigned int context, u64 err_status);
1067 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg);
1068 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1069 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1070 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1071 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1072 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1073 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1074 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg);
1075 static void set_partition_keys(struct hfi1_pportdata *ppd);
1076 static const char *link_state_name(u32 state);
1077 static const char *link_state_reason_name(struct hfi1_pportdata *ppd,
1079 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
1081 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data);
1082 static int thermal_init(struct hfi1_devdata *dd);
1084 static void update_statusp(struct hfi1_pportdata *ppd, u32 state);
1085 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd,
1087 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1089 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state);
1090 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state);
1091 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state,
1093 static int wait_phys_link_out_of_offline(struct hfi1_pportdata *ppd,
1095 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc);
1096 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr);
1097 static void handle_temp_err(struct hfi1_devdata *dd);
1098 static void dc_shutdown(struct hfi1_devdata *dd);
1099 static void dc_start(struct hfi1_devdata *dd);
1100 static int qos_rmt_entries(unsigned int n_krcv_queues, unsigned int *mp,
1102 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd);
1103 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms);
1104 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index);
1105 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width);
1108 * Error interrupt table entry. This is used as input to the interrupt
1109 * "clear down" routine used for all second tier error interrupt register.
1110 * Second tier interrupt registers have a single bit representing them
1111 * in the top-level CceIntStatus.
1113 struct err_reg_info {
1114 u32 status; /* status CSR offset */
1115 u32 clear; /* clear CSR offset */
1116 u32 mask; /* mask CSR offset */
1117 void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg);
1121 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END + 1 - IS_GENERAL_ERR_START)
1122 #define NUM_DC_ERRS (IS_DC_END + 1 - IS_DC_START)
1123 #define NUM_VARIOUS (IS_VARIOUS_END + 1 - IS_VARIOUS_START)
1126 * Helpers for building HFI and DC error interrupt table entries. Different
1127 * helpers are needed because of inconsistent register names.
1129 #define EE(reg, handler, desc) \
1130 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1132 #define DC_EE1(reg, handler, desc) \
1133 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1134 #define DC_EE2(reg, handler, desc) \
1135 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1138 * Table of the "misc" grouping of error interrupts. Each entry refers to
1139 * another register containing more information.
1141 static const struct err_reg_info misc_errs[NUM_MISC_ERRS] = {
1142 /* 0*/ EE(CCE_ERR, handle_cce_err, "CceErr"),
1143 /* 1*/ EE(RCV_ERR, handle_rxe_err, "RxeErr"),
1144 /* 2*/ EE(MISC_ERR, handle_misc_err, "MiscErr"),
1145 /* 3*/ { 0, 0, 0, NULL }, /* reserved */
1146 /* 4*/ EE(SEND_PIO_ERR, handle_pio_err, "PioErr"),
1147 /* 5*/ EE(SEND_DMA_ERR, handle_sdma_err, "SDmaErr"),
1148 /* 6*/ EE(SEND_EGRESS_ERR, handle_egress_err, "EgressErr"),
1149 /* 7*/ EE(SEND_ERR, handle_txe_err, "TxeErr")
1150 /* the rest are reserved */
1154 * Index into the Various section of the interrupt sources
1155 * corresponding to the Critical Temperature interrupt.
1157 #define TCRIT_INT_SOURCE 4
1160 * SDMA error interrupt entry - refers to another register containing more
1163 static const struct err_reg_info sdma_eng_err =
1164 EE(SEND_DMA_ENG_ERR, handle_sdma_eng_err, "SDmaEngErr");
1166 static const struct err_reg_info various_err[NUM_VARIOUS] = {
1167 /* 0*/ { 0, 0, 0, NULL }, /* PbcInt */
1168 /* 1*/ { 0, 0, 0, NULL }, /* GpioAssertInt */
1169 /* 2*/ EE(ASIC_QSFP1, handle_qsfp_int, "QSFP1"),
1170 /* 3*/ EE(ASIC_QSFP2, handle_qsfp_int, "QSFP2"),
1171 /* 4*/ { 0, 0, 0, NULL }, /* TCritInt */
1172 /* rest are reserved */
1176 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1177 * register can not be derived from the MTU value because 10K is not
1178 * a power of 2. Therefore, we need a constant. Everything else can
1181 #define DCC_CFG_PORT_MTU_CAP_10240 7
1184 * Table of the DC grouping of error interrupts. Each entry refers to
1185 * another register containing more information.
1187 static const struct err_reg_info dc_errs[NUM_DC_ERRS] = {
1188 /* 0*/ DC_EE1(DCC_ERR, handle_dcc_err, "DCC Err"),
1189 /* 1*/ DC_EE2(DC_LCB_ERR, handle_lcb_err, "LCB Err"),
1190 /* 2*/ DC_EE2(DC_DC8051_ERR, handle_8051_interrupt, "DC8051 Interrupt"),
1191 /* 3*/ /* dc_lbm_int - special, see is_dc_int() */
1192 /* the rest are reserved */
1202 * csr to read for name (if applicable)
1207 * offset into dd or ppd to store the counter's value
1217 * accessor for stat element, context either dd or ppd
1219 u64 (*rw_cntr)(const struct cntr_entry *, void *context, int vl,
1220 int mode, u64 data);
1223 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1224 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1226 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1236 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1238 (counter * 8 + RCV_COUNTER_ARRAY32), \
1239 0, flags | CNTR_32BIT, \
1240 port_access_u32_csr)
1242 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1244 (counter * 8 + RCV_COUNTER_ARRAY32), \
1245 0, flags | CNTR_32BIT, \
1249 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1251 (counter * 8 + RCV_COUNTER_ARRAY64), \
1253 port_access_u64_csr)
1255 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1257 (counter * 8 + RCV_COUNTER_ARRAY64), \
1261 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1262 #define OVR_ELM(ctx) \
1263 CNTR_ELEM("RcvHdrOvr" #ctx, \
1264 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1265 0, CNTR_NORMAL, port_access_u64_csr)
1268 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1270 (counter * 8 + SEND_COUNTER_ARRAY32), \
1271 0, flags | CNTR_32BIT, \
1272 port_access_u32_csr)
1275 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1277 (counter * 8 + SEND_COUNTER_ARRAY64), \
1279 port_access_u64_csr)
1281 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1283 counter * 8 + SEND_COUNTER_ARRAY64, \
1289 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1291 (counter * 8 + CCE_COUNTER_ARRAY32), \
1292 0, flags | CNTR_32BIT, \
1295 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1297 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1298 0, flags | CNTR_32BIT, \
1302 #define DC_PERF_CNTR(name, counter, flags) \
1309 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1317 #define SW_IBP_CNTR(name, cntr) \
1325 * hfi_addr_from_offset - return addr for readq/writeq
1326 * @dd - the dd device
1327 * @offset - the offset of the CSR within bar0
1329 * This routine selects the appropriate base address
1330 * based on the indicated offset.
1332 static inline void __iomem *hfi1_addr_from_offset(
1333 const struct hfi1_devdata *dd,
1336 if (offset >= dd->base2_start)
1337 return dd->kregbase2 + (offset - dd->base2_start);
1338 return dd->kregbase1 + offset;
1342 * read_csr - read CSR at the indicated offset
1343 * @dd - the dd device
1344 * @offset - the offset of the CSR within bar0
1346 * Return: the value read or all FF's if there
1349 u64 read_csr(const struct hfi1_devdata *dd, u32 offset)
1351 if (dd->flags & HFI1_PRESENT)
1352 return readq(hfi1_addr_from_offset(dd, offset));
1357 * write_csr - write CSR at the indicated offset
1358 * @dd - the dd device
1359 * @offset - the offset of the CSR within bar0
1360 * @value - value to write
1362 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value)
1364 if (dd->flags & HFI1_PRESENT) {
1365 void __iomem *base = hfi1_addr_from_offset(dd, offset);
1367 /* avoid write to RcvArray */
1368 if (WARN_ON(offset >= RCV_ARRAY && offset < dd->base2_start))
1370 writeq(value, base);
1375 * get_csr_addr - return te iomem address for offset
1376 * @dd - the dd device
1377 * @offset - the offset of the CSR within bar0
1379 * Return: The iomem address to use in subsequent
1380 * writeq/readq operations.
1382 void __iomem *get_csr_addr(
1383 const struct hfi1_devdata *dd,
1386 if (dd->flags & HFI1_PRESENT)
1387 return hfi1_addr_from_offset(dd, offset);
1391 static inline u64 read_write_csr(const struct hfi1_devdata *dd, u32 csr,
1392 int mode, u64 value)
1396 if (mode == CNTR_MODE_R) {
1397 ret = read_csr(dd, csr);
1398 } else if (mode == CNTR_MODE_W) {
1399 write_csr(dd, csr, value);
1402 dd_dev_err(dd, "Invalid cntr register access mode");
1406 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
1411 static u64 dev_access_u32_csr(const struct cntr_entry *entry,
1412 void *context, int vl, int mode, u64 data)
1414 struct hfi1_devdata *dd = context;
1415 u64 csr = entry->csr;
1417 if (entry->flags & CNTR_SDMA) {
1418 if (vl == CNTR_INVALID_VL)
1422 if (vl != CNTR_INVALID_VL)
1425 return read_write_csr(dd, csr, mode, data);
1428 static u64 access_sde_err_cnt(const struct cntr_entry *entry,
1429 void *context, int idx, int mode, u64 data)
1431 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1433 if (dd->per_sdma && idx < dd->num_sdma)
1434 return dd->per_sdma[idx].err_cnt;
1438 static u64 access_sde_int_cnt(const struct cntr_entry *entry,
1439 void *context, int idx, int mode, u64 data)
1441 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1443 if (dd->per_sdma && idx < dd->num_sdma)
1444 return dd->per_sdma[idx].sdma_int_cnt;
1448 static u64 access_sde_idle_int_cnt(const struct cntr_entry *entry,
1449 void *context, int idx, int mode, u64 data)
1451 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1453 if (dd->per_sdma && idx < dd->num_sdma)
1454 return dd->per_sdma[idx].idle_int_cnt;
1458 static u64 access_sde_progress_int_cnt(const struct cntr_entry *entry,
1459 void *context, int idx, int mode,
1462 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1464 if (dd->per_sdma && idx < dd->num_sdma)
1465 return dd->per_sdma[idx].progress_int_cnt;
1469 static u64 dev_access_u64_csr(const struct cntr_entry *entry, void *context,
1470 int vl, int mode, u64 data)
1472 struct hfi1_devdata *dd = context;
1475 u64 csr = entry->csr;
1477 if (entry->flags & CNTR_VL) {
1478 if (vl == CNTR_INVALID_VL)
1482 if (vl != CNTR_INVALID_VL)
1486 val = read_write_csr(dd, csr, mode, data);
1490 static u64 dc_access_lcb_cntr(const struct cntr_entry *entry, void *context,
1491 int vl, int mode, u64 data)
1493 struct hfi1_devdata *dd = context;
1494 u32 csr = entry->csr;
1497 if (vl != CNTR_INVALID_VL)
1499 if (mode == CNTR_MODE_R)
1500 ret = read_lcb_csr(dd, csr, &data);
1501 else if (mode == CNTR_MODE_W)
1502 ret = write_lcb_csr(dd, csr, data);
1505 dd_dev_err(dd, "Could not acquire LCB for counter 0x%x", csr);
1509 hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
1514 static u64 port_access_u32_csr(const struct cntr_entry *entry, void *context,
1515 int vl, int mode, u64 data)
1517 struct hfi1_pportdata *ppd = context;
1519 if (vl != CNTR_INVALID_VL)
1521 return read_write_csr(ppd->dd, entry->csr, mode, data);
1524 static u64 port_access_u64_csr(const struct cntr_entry *entry,
1525 void *context, int vl, int mode, u64 data)
1527 struct hfi1_pportdata *ppd = context;
1529 u64 csr = entry->csr;
1531 if (entry->flags & CNTR_VL) {
1532 if (vl == CNTR_INVALID_VL)
1536 if (vl != CNTR_INVALID_VL)
1539 val = read_write_csr(ppd->dd, csr, mode, data);
1543 /* Software defined */
1544 static inline u64 read_write_sw(struct hfi1_devdata *dd, u64 *cntr, int mode,
1549 if (mode == CNTR_MODE_R) {
1551 } else if (mode == CNTR_MODE_W) {
1555 dd_dev_err(dd, "Invalid cntr sw access mode");
1559 hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
1564 static u64 access_sw_link_dn_cnt(const struct cntr_entry *entry, void *context,
1565 int vl, int mode, u64 data)
1567 struct hfi1_pportdata *ppd = context;
1569 if (vl != CNTR_INVALID_VL)
1571 return read_write_sw(ppd->dd, &ppd->link_downed, mode, data);
1574 static u64 access_sw_link_up_cnt(const struct cntr_entry *entry, void *context,
1575 int vl, int mode, u64 data)
1577 struct hfi1_pportdata *ppd = context;
1579 if (vl != CNTR_INVALID_VL)
1581 return read_write_sw(ppd->dd, &ppd->link_up, mode, data);
1584 static u64 access_sw_unknown_frame_cnt(const struct cntr_entry *entry,
1585 void *context, int vl, int mode,
1588 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1590 if (vl != CNTR_INVALID_VL)
1592 return read_write_sw(ppd->dd, &ppd->unknown_frame_count, mode, data);
1595 static u64 access_sw_xmit_discards(const struct cntr_entry *entry,
1596 void *context, int vl, int mode, u64 data)
1598 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context;
1602 if (vl == CNTR_INVALID_VL)
1603 counter = &ppd->port_xmit_discards;
1604 else if (vl >= 0 && vl < C_VL_COUNT)
1605 counter = &ppd->port_xmit_discards_vl[vl];
1609 return read_write_sw(ppd->dd, counter, mode, data);
1612 static u64 access_xmit_constraint_errs(const struct cntr_entry *entry,
1613 void *context, int vl, int mode,
1616 struct hfi1_pportdata *ppd = context;
1618 if (vl != CNTR_INVALID_VL)
1621 return read_write_sw(ppd->dd, &ppd->port_xmit_constraint_errors,
1625 static u64 access_rcv_constraint_errs(const struct cntr_entry *entry,
1626 void *context, int vl, int mode, u64 data)
1628 struct hfi1_pportdata *ppd = context;
1630 if (vl != CNTR_INVALID_VL)
1633 return read_write_sw(ppd->dd, &ppd->port_rcv_constraint_errors,
1637 u64 get_all_cpu_total(u64 __percpu *cntr)
1642 for_each_possible_cpu(cpu)
1643 counter += *per_cpu_ptr(cntr, cpu);
1647 static u64 read_write_cpu(struct hfi1_devdata *dd, u64 *z_val,
1649 int vl, int mode, u64 data)
1653 if (vl != CNTR_INVALID_VL)
1656 if (mode == CNTR_MODE_R) {
1657 ret = get_all_cpu_total(cntr) - *z_val;
1658 } else if (mode == CNTR_MODE_W) {
1659 /* A write can only zero the counter */
1661 *z_val = get_all_cpu_total(cntr);
1663 dd_dev_err(dd, "Per CPU cntrs can only be zeroed");
1665 dd_dev_err(dd, "Invalid cntr sw cpu access mode");
1672 static u64 access_sw_cpu_intr(const struct cntr_entry *entry,
1673 void *context, int vl, int mode, u64 data)
1675 struct hfi1_devdata *dd = context;
1677 return read_write_cpu(dd, &dd->z_int_counter, dd->int_counter, vl,
1681 static u64 access_sw_cpu_rcv_limit(const struct cntr_entry *entry,
1682 void *context, int vl, int mode, u64 data)
1684 struct hfi1_devdata *dd = context;
1686 return read_write_cpu(dd, &dd->z_rcv_limit, dd->rcv_limit, vl,
1690 static u64 access_sw_pio_wait(const struct cntr_entry *entry,
1691 void *context, int vl, int mode, u64 data)
1693 struct hfi1_devdata *dd = context;
1695 return dd->verbs_dev.n_piowait;
1698 static u64 access_sw_pio_drain(const struct cntr_entry *entry,
1699 void *context, int vl, int mode, u64 data)
1701 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1703 return dd->verbs_dev.n_piodrain;
1706 static u64 access_sw_ctx0_seq_drop(const struct cntr_entry *entry,
1707 void *context, int vl, int mode, u64 data)
1709 struct hfi1_devdata *dd = context;
1711 return dd->ctx0_seq_drop;
1714 static u64 access_sw_vtx_wait(const struct cntr_entry *entry,
1715 void *context, int vl, int mode, u64 data)
1717 struct hfi1_devdata *dd = context;
1719 return dd->verbs_dev.n_txwait;
1722 static u64 access_sw_kmem_wait(const struct cntr_entry *entry,
1723 void *context, int vl, int mode, u64 data)
1725 struct hfi1_devdata *dd = context;
1727 return dd->verbs_dev.n_kmem_wait;
1730 static u64 access_sw_send_schedule(const struct cntr_entry *entry,
1731 void *context, int vl, int mode, u64 data)
1733 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1735 return read_write_cpu(dd, &dd->z_send_schedule, dd->send_schedule, vl,
1739 /* Software counters for the error status bits within MISC_ERR_STATUS */
1740 static u64 access_misc_pll_lock_fail_err_cnt(const struct cntr_entry *entry,
1741 void *context, int vl, int mode,
1744 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1746 return dd->misc_err_status_cnt[12];
1749 static u64 access_misc_mbist_fail_err_cnt(const struct cntr_entry *entry,
1750 void *context, int vl, int mode,
1753 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1755 return dd->misc_err_status_cnt[11];
1758 static u64 access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry *entry,
1759 void *context, int vl, int mode,
1762 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1764 return dd->misc_err_status_cnt[10];
1767 static u64 access_misc_efuse_done_parity_err_cnt(const struct cntr_entry *entry,
1768 void *context, int vl,
1771 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1773 return dd->misc_err_status_cnt[9];
1776 static u64 access_misc_efuse_write_err_cnt(const struct cntr_entry *entry,
1777 void *context, int vl, int mode,
1780 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1782 return dd->misc_err_status_cnt[8];
1785 static u64 access_misc_efuse_read_bad_addr_err_cnt(
1786 const struct cntr_entry *entry,
1787 void *context, int vl, int mode, u64 data)
1789 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1791 return dd->misc_err_status_cnt[7];
1794 static u64 access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry *entry,
1795 void *context, int vl,
1798 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1800 return dd->misc_err_status_cnt[6];
1803 static u64 access_misc_fw_auth_failed_err_cnt(const struct cntr_entry *entry,
1804 void *context, int vl, int mode,
1807 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1809 return dd->misc_err_status_cnt[5];
1812 static u64 access_misc_key_mismatch_err_cnt(const struct cntr_entry *entry,
1813 void *context, int vl, int mode,
1816 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1818 return dd->misc_err_status_cnt[4];
1821 static u64 access_misc_sbus_write_failed_err_cnt(const struct cntr_entry *entry,
1822 void *context, int vl,
1825 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1827 return dd->misc_err_status_cnt[3];
1830 static u64 access_misc_csr_write_bad_addr_err_cnt(
1831 const struct cntr_entry *entry,
1832 void *context, int vl, int mode, u64 data)
1834 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1836 return dd->misc_err_status_cnt[2];
1839 static u64 access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1840 void *context, int vl,
1843 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1845 return dd->misc_err_status_cnt[1];
1848 static u64 access_misc_csr_parity_err_cnt(const struct cntr_entry *entry,
1849 void *context, int vl, int mode,
1852 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1854 return dd->misc_err_status_cnt[0];
1858 * Software counter for the aggregate of
1859 * individual CceErrStatus counters
1861 static u64 access_sw_cce_err_status_aggregated_cnt(
1862 const struct cntr_entry *entry,
1863 void *context, int vl, int mode, u64 data)
1865 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1867 return dd->sw_cce_err_status_aggregate;
1871 * Software counters corresponding to each of the
1872 * error status bits within CceErrStatus
1874 static u64 access_cce_msix_csr_parity_err_cnt(const struct cntr_entry *entry,
1875 void *context, int vl, int mode,
1878 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1880 return dd->cce_err_status_cnt[40];
1883 static u64 access_cce_int_map_unc_err_cnt(const struct cntr_entry *entry,
1884 void *context, int vl, int mode,
1887 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1889 return dd->cce_err_status_cnt[39];
1892 static u64 access_cce_int_map_cor_err_cnt(const struct cntr_entry *entry,
1893 void *context, int vl, int mode,
1896 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1898 return dd->cce_err_status_cnt[38];
1901 static u64 access_cce_msix_table_unc_err_cnt(const struct cntr_entry *entry,
1902 void *context, int vl, int mode,
1905 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1907 return dd->cce_err_status_cnt[37];
1910 static u64 access_cce_msix_table_cor_err_cnt(const struct cntr_entry *entry,
1911 void *context, int vl, int mode,
1914 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1916 return dd->cce_err_status_cnt[36];
1919 static u64 access_cce_rxdma_conv_fifo_parity_err_cnt(
1920 const struct cntr_entry *entry,
1921 void *context, int vl, int mode, u64 data)
1923 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1925 return dd->cce_err_status_cnt[35];
1928 static u64 access_cce_rcpl_async_fifo_parity_err_cnt(
1929 const struct cntr_entry *entry,
1930 void *context, int vl, int mode, u64 data)
1932 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1934 return dd->cce_err_status_cnt[34];
1937 static u64 access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry *entry,
1938 void *context, int vl,
1941 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1943 return dd->cce_err_status_cnt[33];
1946 static u64 access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry *entry,
1947 void *context, int vl, int mode,
1950 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1952 return dd->cce_err_status_cnt[32];
1955 static u64 access_la_triggered_cnt(const struct cntr_entry *entry,
1956 void *context, int vl, int mode, u64 data)
1958 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1960 return dd->cce_err_status_cnt[31];
1963 static u64 access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry *entry,
1964 void *context, int vl, int mode,
1967 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1969 return dd->cce_err_status_cnt[30];
1972 static u64 access_pcic_receive_parity_err_cnt(const struct cntr_entry *entry,
1973 void *context, int vl, int mode,
1976 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1978 return dd->cce_err_status_cnt[29];
1981 static u64 access_pcic_transmit_back_parity_err_cnt(
1982 const struct cntr_entry *entry,
1983 void *context, int vl, int mode, u64 data)
1985 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1987 return dd->cce_err_status_cnt[28];
1990 static u64 access_pcic_transmit_front_parity_err_cnt(
1991 const struct cntr_entry *entry,
1992 void *context, int vl, int mode, u64 data)
1994 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
1996 return dd->cce_err_status_cnt[27];
1999 static u64 access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry *entry,
2000 void *context, int vl, int mode,
2003 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2005 return dd->cce_err_status_cnt[26];
2008 static u64 access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry *entry,
2009 void *context, int vl, int mode,
2012 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2014 return dd->cce_err_status_cnt[25];
2017 static u64 access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry *entry,
2018 void *context, int vl, int mode,
2021 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2023 return dd->cce_err_status_cnt[24];
2026 static u64 access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry *entry,
2027 void *context, int vl, int mode,
2030 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2032 return dd->cce_err_status_cnt[23];
2035 static u64 access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry *entry,
2036 void *context, int vl,
2039 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2041 return dd->cce_err_status_cnt[22];
2044 static u64 access_pcic_retry_mem_unc_err(const struct cntr_entry *entry,
2045 void *context, int vl, int mode,
2048 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2050 return dd->cce_err_status_cnt[21];
2053 static u64 access_pcic_n_post_dat_q_parity_err_cnt(
2054 const struct cntr_entry *entry,
2055 void *context, int vl, int mode, u64 data)
2057 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2059 return dd->cce_err_status_cnt[20];
2062 static u64 access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry *entry,
2063 void *context, int vl,
2066 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2068 return dd->cce_err_status_cnt[19];
2071 static u64 access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry *entry,
2072 void *context, int vl, int mode,
2075 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2077 return dd->cce_err_status_cnt[18];
2080 static u64 access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry *entry,
2081 void *context, int vl, int mode,
2084 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2086 return dd->cce_err_status_cnt[17];
2089 static u64 access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry *entry,
2090 void *context, int vl, int mode,
2093 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2095 return dd->cce_err_status_cnt[16];
2098 static u64 access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry *entry,
2099 void *context, int vl, int mode,
2102 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2104 return dd->cce_err_status_cnt[15];
2107 static u64 access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry *entry,
2108 void *context, int vl,
2111 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2113 return dd->cce_err_status_cnt[14];
2116 static u64 access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry *entry,
2117 void *context, int vl, int mode,
2120 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2122 return dd->cce_err_status_cnt[13];
2125 static u64 access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2126 const struct cntr_entry *entry,
2127 void *context, int vl, int mode, u64 data)
2129 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2131 return dd->cce_err_status_cnt[12];
2134 static u64 access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2135 const struct cntr_entry *entry,
2136 void *context, int vl, int mode, u64 data)
2138 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2140 return dd->cce_err_status_cnt[11];
2143 static u64 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2144 const struct cntr_entry *entry,
2145 void *context, int vl, int mode, u64 data)
2147 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2149 return dd->cce_err_status_cnt[10];
2152 static u64 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2153 const struct cntr_entry *entry,
2154 void *context, int vl, int mode, u64 data)
2156 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2158 return dd->cce_err_status_cnt[9];
2161 static u64 access_cce_cli2_async_fifo_parity_err_cnt(
2162 const struct cntr_entry *entry,
2163 void *context, int vl, int mode, u64 data)
2165 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2167 return dd->cce_err_status_cnt[8];
2170 static u64 access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry *entry,
2171 void *context, int vl,
2174 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2176 return dd->cce_err_status_cnt[7];
2179 static u64 access_cce_cli0_async_fifo_parity_err_cnt(
2180 const struct cntr_entry *entry,
2181 void *context, int vl, int mode, u64 data)
2183 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2185 return dd->cce_err_status_cnt[6];
2188 static u64 access_cce_rspd_data_parity_err_cnt(const struct cntr_entry *entry,
2189 void *context, int vl, int mode,
2192 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2194 return dd->cce_err_status_cnt[5];
2197 static u64 access_cce_trgt_access_err_cnt(const struct cntr_entry *entry,
2198 void *context, int vl, int mode,
2201 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2203 return dd->cce_err_status_cnt[4];
2206 static u64 access_cce_trgt_async_fifo_parity_err_cnt(
2207 const struct cntr_entry *entry,
2208 void *context, int vl, int mode, u64 data)
2210 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2212 return dd->cce_err_status_cnt[3];
2215 static u64 access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2216 void *context, int vl,
2219 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2221 return dd->cce_err_status_cnt[2];
2224 static u64 access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2225 void *context, int vl,
2228 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2230 return dd->cce_err_status_cnt[1];
2233 static u64 access_ccs_csr_parity_err_cnt(const struct cntr_entry *entry,
2234 void *context, int vl, int mode,
2237 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2239 return dd->cce_err_status_cnt[0];
2243 * Software counters corresponding to each of the
2244 * error status bits within RcvErrStatus
2246 static u64 access_rx_csr_parity_err_cnt(const struct cntr_entry *entry,
2247 void *context, int vl, int mode,
2250 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2252 return dd->rcv_err_status_cnt[63];
2255 static u64 access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry *entry,
2256 void *context, int vl,
2259 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2261 return dd->rcv_err_status_cnt[62];
2264 static u64 access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
2265 void *context, int vl, int mode,
2268 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2270 return dd->rcv_err_status_cnt[61];
2273 static u64 access_rx_dma_csr_unc_err_cnt(const struct cntr_entry *entry,
2274 void *context, int vl, int mode,
2277 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2279 return dd->rcv_err_status_cnt[60];
2282 static u64 access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2283 void *context, int vl,
2286 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2288 return dd->rcv_err_status_cnt[59];
2291 static u64 access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2292 void *context, int vl,
2295 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2297 return dd->rcv_err_status_cnt[58];
2300 static u64 access_rx_dma_csr_parity_err_cnt(const struct cntr_entry *entry,
2301 void *context, int vl, int mode,
2304 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2306 return dd->rcv_err_status_cnt[57];
2309 static u64 access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry *entry,
2310 void *context, int vl, int mode,
2313 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2315 return dd->rcv_err_status_cnt[56];
2318 static u64 access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry *entry,
2319 void *context, int vl, int mode,
2322 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2324 return dd->rcv_err_status_cnt[55];
2327 static u64 access_rx_dma_data_fifo_rd_cor_err_cnt(
2328 const struct cntr_entry *entry,
2329 void *context, int vl, int mode, u64 data)
2331 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2333 return dd->rcv_err_status_cnt[54];
2336 static u64 access_rx_dma_data_fifo_rd_unc_err_cnt(
2337 const struct cntr_entry *entry,
2338 void *context, int vl, int mode, u64 data)
2340 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2342 return dd->rcv_err_status_cnt[53];
2345 static u64 access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry *entry,
2346 void *context, int vl,
2349 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2351 return dd->rcv_err_status_cnt[52];
2354 static u64 access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry *entry,
2355 void *context, int vl,
2358 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2360 return dd->rcv_err_status_cnt[51];
2363 static u64 access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry *entry,
2364 void *context, int vl,
2367 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2369 return dd->rcv_err_status_cnt[50];
2372 static u64 access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry *entry,
2373 void *context, int vl,
2376 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2378 return dd->rcv_err_status_cnt[49];
2381 static u64 access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry *entry,
2382 void *context, int vl,
2385 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2387 return dd->rcv_err_status_cnt[48];
2390 static u64 access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry *entry,
2391 void *context, int vl,
2394 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2396 return dd->rcv_err_status_cnt[47];
2399 static u64 access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry *entry,
2400 void *context, int vl, int mode,
2403 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2405 return dd->rcv_err_status_cnt[46];
2408 static u64 access_rx_hq_intr_csr_parity_err_cnt(
2409 const struct cntr_entry *entry,
2410 void *context, int vl, int mode, u64 data)
2412 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2414 return dd->rcv_err_status_cnt[45];
2417 static u64 access_rx_lookup_csr_parity_err_cnt(
2418 const struct cntr_entry *entry,
2419 void *context, int vl, int mode, u64 data)
2421 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2423 return dd->rcv_err_status_cnt[44];
2426 static u64 access_rx_lookup_rcv_array_cor_err_cnt(
2427 const struct cntr_entry *entry,
2428 void *context, int vl, int mode, u64 data)
2430 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2432 return dd->rcv_err_status_cnt[43];
2435 static u64 access_rx_lookup_rcv_array_unc_err_cnt(
2436 const struct cntr_entry *entry,
2437 void *context, int vl, int mode, u64 data)
2439 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2441 return dd->rcv_err_status_cnt[42];
2444 static u64 access_rx_lookup_des_part2_parity_err_cnt(
2445 const struct cntr_entry *entry,
2446 void *context, int vl, int mode, u64 data)
2448 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2450 return dd->rcv_err_status_cnt[41];
2453 static u64 access_rx_lookup_des_part1_unc_cor_err_cnt(
2454 const struct cntr_entry *entry,
2455 void *context, int vl, int mode, u64 data)
2457 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2459 return dd->rcv_err_status_cnt[40];
2462 static u64 access_rx_lookup_des_part1_unc_err_cnt(
2463 const struct cntr_entry *entry,
2464 void *context, int vl, int mode, u64 data)
2466 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2468 return dd->rcv_err_status_cnt[39];
2471 static u64 access_rx_rbuf_next_free_buf_cor_err_cnt(
2472 const struct cntr_entry *entry,
2473 void *context, int vl, int mode, u64 data)
2475 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2477 return dd->rcv_err_status_cnt[38];
2480 static u64 access_rx_rbuf_next_free_buf_unc_err_cnt(
2481 const struct cntr_entry *entry,
2482 void *context, int vl, int mode, u64 data)
2484 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2486 return dd->rcv_err_status_cnt[37];
2489 static u64 access_rbuf_fl_init_wr_addr_parity_err_cnt(
2490 const struct cntr_entry *entry,
2491 void *context, int vl, int mode, u64 data)
2493 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2495 return dd->rcv_err_status_cnt[36];
2498 static u64 access_rx_rbuf_fl_initdone_parity_err_cnt(
2499 const struct cntr_entry *entry,
2500 void *context, int vl, int mode, u64 data)
2502 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2504 return dd->rcv_err_status_cnt[35];
2507 static u64 access_rx_rbuf_fl_write_addr_parity_err_cnt(
2508 const struct cntr_entry *entry,
2509 void *context, int vl, int mode, u64 data)
2511 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2513 return dd->rcv_err_status_cnt[34];
2516 static u64 access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2517 const struct cntr_entry *entry,
2518 void *context, int vl, int mode, u64 data)
2520 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2522 return dd->rcv_err_status_cnt[33];
2525 static u64 access_rx_rbuf_empty_err_cnt(const struct cntr_entry *entry,
2526 void *context, int vl, int mode,
2529 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2531 return dd->rcv_err_status_cnt[32];
2534 static u64 access_rx_rbuf_full_err_cnt(const struct cntr_entry *entry,
2535 void *context, int vl, int mode,
2538 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2540 return dd->rcv_err_status_cnt[31];
2543 static u64 access_rbuf_bad_lookup_err_cnt(const struct cntr_entry *entry,
2544 void *context, int vl, int mode,
2547 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2549 return dd->rcv_err_status_cnt[30];
2552 static u64 access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry *entry,
2553 void *context, int vl, int mode,
2556 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2558 return dd->rcv_err_status_cnt[29];
2561 static u64 access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry *entry,
2562 void *context, int vl,
2565 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2567 return dd->rcv_err_status_cnt[28];
2570 static u64 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2571 const struct cntr_entry *entry,
2572 void *context, int vl, int mode, u64 data)
2574 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2576 return dd->rcv_err_status_cnt[27];
2579 static u64 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2580 const struct cntr_entry *entry,
2581 void *context, int vl, int mode, u64 data)
2583 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2585 return dd->rcv_err_status_cnt[26];
2588 static u64 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2589 const struct cntr_entry *entry,
2590 void *context, int vl, int mode, u64 data)
2592 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2594 return dd->rcv_err_status_cnt[25];
2597 static u64 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2598 const struct cntr_entry *entry,
2599 void *context, int vl, int mode, u64 data)
2601 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2603 return dd->rcv_err_status_cnt[24];
2606 static u64 access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2607 const struct cntr_entry *entry,
2608 void *context, int vl, int mode, u64 data)
2610 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2612 return dd->rcv_err_status_cnt[23];
2615 static u64 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2616 const struct cntr_entry *entry,
2617 void *context, int vl, int mode, u64 data)
2619 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2621 return dd->rcv_err_status_cnt[22];
2624 static u64 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2625 const struct cntr_entry *entry,
2626 void *context, int vl, int mode, u64 data)
2628 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2630 return dd->rcv_err_status_cnt[21];
2633 static u64 access_rx_rbuf_block_list_read_cor_err_cnt(
2634 const struct cntr_entry *entry,
2635 void *context, int vl, int mode, u64 data)
2637 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2639 return dd->rcv_err_status_cnt[20];
2642 static u64 access_rx_rbuf_block_list_read_unc_err_cnt(
2643 const struct cntr_entry *entry,
2644 void *context, int vl, int mode, u64 data)
2646 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2648 return dd->rcv_err_status_cnt[19];
2651 static u64 access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry *entry,
2652 void *context, int vl,
2655 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2657 return dd->rcv_err_status_cnt[18];
2660 static u64 access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry *entry,
2661 void *context, int vl,
2664 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2666 return dd->rcv_err_status_cnt[17];
2669 static u64 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2670 const struct cntr_entry *entry,
2671 void *context, int vl, int mode, u64 data)
2673 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2675 return dd->rcv_err_status_cnt[16];
2678 static u64 access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2679 const struct cntr_entry *entry,
2680 void *context, int vl, int mode, u64 data)
2682 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2684 return dd->rcv_err_status_cnt[15];
2687 static u64 access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry *entry,
2688 void *context, int vl,
2691 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2693 return dd->rcv_err_status_cnt[14];
2696 static u64 access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry *entry,
2697 void *context, int vl,
2700 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2702 return dd->rcv_err_status_cnt[13];
2705 static u64 access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry *entry,
2706 void *context, int vl, int mode,
2709 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2711 return dd->rcv_err_status_cnt[12];
2714 static u64 access_rx_dma_flag_cor_err_cnt(const struct cntr_entry *entry,
2715 void *context, int vl, int mode,
2718 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2720 return dd->rcv_err_status_cnt[11];
2723 static u64 access_rx_dma_flag_unc_err_cnt(const struct cntr_entry *entry,
2724 void *context, int vl, int mode,
2727 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2729 return dd->rcv_err_status_cnt[10];
2732 static u64 access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry *entry,
2733 void *context, int vl, int mode,
2736 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2738 return dd->rcv_err_status_cnt[9];
2741 static u64 access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry *entry,
2742 void *context, int vl, int mode,
2745 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2747 return dd->rcv_err_status_cnt[8];
2750 static u64 access_rx_rcv_qp_map_table_cor_err_cnt(
2751 const struct cntr_entry *entry,
2752 void *context, int vl, int mode, u64 data)
2754 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2756 return dd->rcv_err_status_cnt[7];
2759 static u64 access_rx_rcv_qp_map_table_unc_err_cnt(
2760 const struct cntr_entry *entry,
2761 void *context, int vl, int mode, u64 data)
2763 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2765 return dd->rcv_err_status_cnt[6];
2768 static u64 access_rx_rcv_data_cor_err_cnt(const struct cntr_entry *entry,
2769 void *context, int vl, int mode,
2772 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2774 return dd->rcv_err_status_cnt[5];
2777 static u64 access_rx_rcv_data_unc_err_cnt(const struct cntr_entry *entry,
2778 void *context, int vl, int mode,
2781 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2783 return dd->rcv_err_status_cnt[4];
2786 static u64 access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry *entry,
2787 void *context, int vl, int mode,
2790 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2792 return dd->rcv_err_status_cnt[3];
2795 static u64 access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry *entry,
2796 void *context, int vl, int mode,
2799 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2801 return dd->rcv_err_status_cnt[2];
2804 static u64 access_rx_dc_intf_parity_err_cnt(const struct cntr_entry *entry,
2805 void *context, int vl, int mode,
2808 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2810 return dd->rcv_err_status_cnt[1];
2813 static u64 access_rx_dma_csr_cor_err_cnt(const struct cntr_entry *entry,
2814 void *context, int vl, int mode,
2817 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2819 return dd->rcv_err_status_cnt[0];
2823 * Software counters corresponding to each of the
2824 * error status bits within SendPioErrStatus
2826 static u64 access_pio_pec_sop_head_parity_err_cnt(
2827 const struct cntr_entry *entry,
2828 void *context, int vl, int mode, u64 data)
2830 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2832 return dd->send_pio_err_status_cnt[35];
2835 static u64 access_pio_pcc_sop_head_parity_err_cnt(
2836 const struct cntr_entry *entry,
2837 void *context, int vl, int mode, u64 data)
2839 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2841 return dd->send_pio_err_status_cnt[34];
2844 static u64 access_pio_last_returned_cnt_parity_err_cnt(
2845 const struct cntr_entry *entry,
2846 void *context, int vl, int mode, u64 data)
2848 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2850 return dd->send_pio_err_status_cnt[33];
2853 static u64 access_pio_current_free_cnt_parity_err_cnt(
2854 const struct cntr_entry *entry,
2855 void *context, int vl, int mode, u64 data)
2857 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2859 return dd->send_pio_err_status_cnt[32];
2862 static u64 access_pio_reserved_31_err_cnt(const struct cntr_entry *entry,
2863 void *context, int vl, int mode,
2866 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2868 return dd->send_pio_err_status_cnt[31];
2871 static u64 access_pio_reserved_30_err_cnt(const struct cntr_entry *entry,
2872 void *context, int vl, int mode,
2875 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2877 return dd->send_pio_err_status_cnt[30];
2880 static u64 access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry *entry,
2881 void *context, int vl, int mode,
2884 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2886 return dd->send_pio_err_status_cnt[29];
2889 static u64 access_pio_ppmc_bqc_mem_parity_err_cnt(
2890 const struct cntr_entry *entry,
2891 void *context, int vl, int mode, u64 data)
2893 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2895 return dd->send_pio_err_status_cnt[28];
2898 static u64 access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry *entry,
2899 void *context, int vl, int mode,
2902 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2904 return dd->send_pio_err_status_cnt[27];
2907 static u64 access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry *entry,
2908 void *context, int vl, int mode,
2911 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2913 return dd->send_pio_err_status_cnt[26];
2916 static u64 access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry *entry,
2917 void *context, int vl,
2920 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2922 return dd->send_pio_err_status_cnt[25];
2925 static u64 access_pio_block_qw_count_parity_err_cnt(
2926 const struct cntr_entry *entry,
2927 void *context, int vl, int mode, u64 data)
2929 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2931 return dd->send_pio_err_status_cnt[24];
2934 static u64 access_pio_write_qw_valid_parity_err_cnt(
2935 const struct cntr_entry *entry,
2936 void *context, int vl, int mode, u64 data)
2938 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2940 return dd->send_pio_err_status_cnt[23];
2943 static u64 access_pio_state_machine_err_cnt(const struct cntr_entry *entry,
2944 void *context, int vl, int mode,
2947 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2949 return dd->send_pio_err_status_cnt[22];
2952 static u64 access_pio_write_data_parity_err_cnt(const struct cntr_entry *entry,
2953 void *context, int vl,
2956 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2958 return dd->send_pio_err_status_cnt[21];
2961 static u64 access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry *entry,
2962 void *context, int vl,
2965 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2967 return dd->send_pio_err_status_cnt[20];
2970 static u64 access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry *entry,
2971 void *context, int vl,
2974 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2976 return dd->send_pio_err_status_cnt[19];
2979 static u64 access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2980 const struct cntr_entry *entry,
2981 void *context, int vl, int mode, u64 data)
2983 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2985 return dd->send_pio_err_status_cnt[18];
2988 static u64 access_pio_init_sm_in_err_cnt(const struct cntr_entry *entry,
2989 void *context, int vl, int mode,
2992 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
2994 return dd->send_pio_err_status_cnt[17];
2997 static u64 access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry *entry,
2998 void *context, int vl, int mode,
3001 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3003 return dd->send_pio_err_status_cnt[16];
3006 static u64 access_pio_credit_ret_fifo_parity_err_cnt(
3007 const struct cntr_entry *entry,
3008 void *context, int vl, int mode, u64 data)
3010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3012 return dd->send_pio_err_status_cnt[15];
3015 static u64 access_pio_v1_len_mem_bank1_cor_err_cnt(
3016 const struct cntr_entry *entry,
3017 void *context, int vl, int mode, u64 data)
3019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3021 return dd->send_pio_err_status_cnt[14];
3024 static u64 access_pio_v1_len_mem_bank0_cor_err_cnt(
3025 const struct cntr_entry *entry,
3026 void *context, int vl, int mode, u64 data)
3028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3030 return dd->send_pio_err_status_cnt[13];
3033 static u64 access_pio_v1_len_mem_bank1_unc_err_cnt(
3034 const struct cntr_entry *entry,
3035 void *context, int vl, int mode, u64 data)
3037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3039 return dd->send_pio_err_status_cnt[12];
3042 static u64 access_pio_v1_len_mem_bank0_unc_err_cnt(
3043 const struct cntr_entry *entry,
3044 void *context, int vl, int mode, u64 data)
3046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3048 return dd->send_pio_err_status_cnt[11];
3051 static u64 access_pio_sm_pkt_reset_parity_err_cnt(
3052 const struct cntr_entry *entry,
3053 void *context, int vl, int mode, u64 data)
3055 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3057 return dd->send_pio_err_status_cnt[10];
3060 static u64 access_pio_pkt_evict_fifo_parity_err_cnt(
3061 const struct cntr_entry *entry,
3062 void *context, int vl, int mode, u64 data)
3064 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3066 return dd->send_pio_err_status_cnt[9];
3069 static u64 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
3070 const struct cntr_entry *entry,
3071 void *context, int vl, int mode, u64 data)
3073 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3075 return dd->send_pio_err_status_cnt[8];
3078 static u64 access_pio_sbrdctl_crrel_parity_err_cnt(
3079 const struct cntr_entry *entry,
3080 void *context, int vl, int mode, u64 data)
3082 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3084 return dd->send_pio_err_status_cnt[7];
3087 static u64 access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry *entry,
3088 void *context, int vl, int mode,
3091 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3093 return dd->send_pio_err_status_cnt[6];
3096 static u64 access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry *entry,
3097 void *context, int vl, int mode,
3100 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3102 return dd->send_pio_err_status_cnt[5];
3105 static u64 access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry *entry,
3106 void *context, int vl, int mode,
3109 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3111 return dd->send_pio_err_status_cnt[4];
3114 static u64 access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry *entry,
3115 void *context, int vl, int mode,
3118 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3120 return dd->send_pio_err_status_cnt[3];
3123 static u64 access_pio_csr_parity_err_cnt(const struct cntr_entry *entry,
3124 void *context, int vl, int mode,
3127 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3129 return dd->send_pio_err_status_cnt[2];
3132 static u64 access_pio_write_addr_parity_err_cnt(const struct cntr_entry *entry,
3133 void *context, int vl,
3136 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3138 return dd->send_pio_err_status_cnt[1];
3141 static u64 access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry *entry,
3142 void *context, int vl, int mode,
3145 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3147 return dd->send_pio_err_status_cnt[0];
3151 * Software counters corresponding to each of the
3152 * error status bits within SendDmaErrStatus
3154 static u64 access_sdma_pcie_req_tracking_cor_err_cnt(
3155 const struct cntr_entry *entry,
3156 void *context, int vl, int mode, u64 data)
3158 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3160 return dd->send_dma_err_status_cnt[3];
3163 static u64 access_sdma_pcie_req_tracking_unc_err_cnt(
3164 const struct cntr_entry *entry,
3165 void *context, int vl, int mode, u64 data)
3167 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3169 return dd->send_dma_err_status_cnt[2];
3172 static u64 access_sdma_csr_parity_err_cnt(const struct cntr_entry *entry,
3173 void *context, int vl, int mode,
3176 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3178 return dd->send_dma_err_status_cnt[1];
3181 static u64 access_sdma_rpy_tag_err_cnt(const struct cntr_entry *entry,
3182 void *context, int vl, int mode,
3185 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3187 return dd->send_dma_err_status_cnt[0];
3191 * Software counters corresponding to each of the
3192 * error status bits within SendEgressErrStatus
3194 static u64 access_tx_read_pio_memory_csr_unc_err_cnt(
3195 const struct cntr_entry *entry,
3196 void *context, int vl, int mode, u64 data)
3198 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3200 return dd->send_egress_err_status_cnt[63];
3203 static u64 access_tx_read_sdma_memory_csr_err_cnt(
3204 const struct cntr_entry *entry,
3205 void *context, int vl, int mode, u64 data)
3207 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3209 return dd->send_egress_err_status_cnt[62];
3212 static u64 access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry *entry,
3213 void *context, int vl, int mode,
3216 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3218 return dd->send_egress_err_status_cnt[61];
3221 static u64 access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry *entry,
3222 void *context, int vl,
3225 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3227 return dd->send_egress_err_status_cnt[60];
3230 static u64 access_tx_read_sdma_memory_cor_err_cnt(
3231 const struct cntr_entry *entry,
3232 void *context, int vl, int mode, u64 data)
3234 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3236 return dd->send_egress_err_status_cnt[59];
3239 static u64 access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry *entry,
3240 void *context, int vl, int mode,
3243 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3245 return dd->send_egress_err_status_cnt[58];
3248 static u64 access_tx_credit_overrun_err_cnt(const struct cntr_entry *entry,
3249 void *context, int vl, int mode,
3252 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3254 return dd->send_egress_err_status_cnt[57];
3257 static u64 access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry *entry,
3258 void *context, int vl, int mode,
3261 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3263 return dd->send_egress_err_status_cnt[56];
3266 static u64 access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry *entry,
3267 void *context, int vl, int mode,
3270 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3272 return dd->send_egress_err_status_cnt[55];
3275 static u64 access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry *entry,
3276 void *context, int vl, int mode,
3279 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3281 return dd->send_egress_err_status_cnt[54];
3284 static u64 access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry *entry,
3285 void *context, int vl, int mode,
3288 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3290 return dd->send_egress_err_status_cnt[53];
3293 static u64 access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry *entry,
3294 void *context, int vl, int mode,
3297 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3299 return dd->send_egress_err_status_cnt[52];
3302 static u64 access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry *entry,
3303 void *context, int vl, int mode,
3306 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3308 return dd->send_egress_err_status_cnt[51];
3311 static u64 access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry *entry,
3312 void *context, int vl, int mode,
3315 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3317 return dd->send_egress_err_status_cnt[50];
3320 static u64 access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry *entry,
3321 void *context, int vl, int mode,
3324 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3326 return dd->send_egress_err_status_cnt[49];
3329 static u64 access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry *entry,
3330 void *context, int vl, int mode,
3333 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3335 return dd->send_egress_err_status_cnt[48];
3338 static u64 access_tx_credit_return_vl_err_cnt(const struct cntr_entry *entry,
3339 void *context, int vl, int mode,
3342 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3344 return dd->send_egress_err_status_cnt[47];
3347 static u64 access_tx_hcrc_insertion_err_cnt(const struct cntr_entry *entry,
3348 void *context, int vl, int mode,
3351 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3353 return dd->send_egress_err_status_cnt[46];
3356 static u64 access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry *entry,
3357 void *context, int vl, int mode,
3360 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3362 return dd->send_egress_err_status_cnt[45];
3365 static u64 access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry *entry,
3366 void *context, int vl,
3369 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3371 return dd->send_egress_err_status_cnt[44];
3374 static u64 access_tx_read_sdma_memory_unc_err_cnt(
3375 const struct cntr_entry *entry,
3376 void *context, int vl, int mode, u64 data)
3378 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3380 return dd->send_egress_err_status_cnt[43];
3383 static u64 access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry *entry,
3384 void *context, int vl, int mode,
3387 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3389 return dd->send_egress_err_status_cnt[42];
3392 static u64 access_tx_credit_return_partiy_err_cnt(
3393 const struct cntr_entry *entry,
3394 void *context, int vl, int mode, u64 data)
3396 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3398 return dd->send_egress_err_status_cnt[41];
3401 static u64 access_tx_launch_fifo8_unc_or_parity_err_cnt(
3402 const struct cntr_entry *entry,
3403 void *context, int vl, int mode, u64 data)
3405 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3407 return dd->send_egress_err_status_cnt[40];
3410 static u64 access_tx_launch_fifo7_unc_or_parity_err_cnt(
3411 const struct cntr_entry *entry,
3412 void *context, int vl, int mode, u64 data)
3414 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3416 return dd->send_egress_err_status_cnt[39];
3419 static u64 access_tx_launch_fifo6_unc_or_parity_err_cnt(
3420 const struct cntr_entry *entry,
3421 void *context, int vl, int mode, u64 data)
3423 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3425 return dd->send_egress_err_status_cnt[38];
3428 static u64 access_tx_launch_fifo5_unc_or_parity_err_cnt(
3429 const struct cntr_entry *entry,
3430 void *context, int vl, int mode, u64 data)
3432 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3434 return dd->send_egress_err_status_cnt[37];
3437 static u64 access_tx_launch_fifo4_unc_or_parity_err_cnt(
3438 const struct cntr_entry *entry,
3439 void *context, int vl, int mode, u64 data)
3441 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3443 return dd->send_egress_err_status_cnt[36];
3446 static u64 access_tx_launch_fifo3_unc_or_parity_err_cnt(
3447 const struct cntr_entry *entry,
3448 void *context, int vl, int mode, u64 data)
3450 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3452 return dd->send_egress_err_status_cnt[35];
3455 static u64 access_tx_launch_fifo2_unc_or_parity_err_cnt(
3456 const struct cntr_entry *entry,
3457 void *context, int vl, int mode, u64 data)
3459 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3461 return dd->send_egress_err_status_cnt[34];
3464 static u64 access_tx_launch_fifo1_unc_or_parity_err_cnt(
3465 const struct cntr_entry *entry,
3466 void *context, int vl, int mode, u64 data)
3468 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3470 return dd->send_egress_err_status_cnt[33];
3473 static u64 access_tx_launch_fifo0_unc_or_parity_err_cnt(
3474 const struct cntr_entry *entry,
3475 void *context, int vl, int mode, u64 data)
3477 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3479 return dd->send_egress_err_status_cnt[32];
3482 static u64 access_tx_sdma15_disallowed_packet_err_cnt(
3483 const struct cntr_entry *entry,
3484 void *context, int vl, int mode, u64 data)
3486 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3488 return dd->send_egress_err_status_cnt[31];
3491 static u64 access_tx_sdma14_disallowed_packet_err_cnt(
3492 const struct cntr_entry *entry,
3493 void *context, int vl, int mode, u64 data)
3495 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3497 return dd->send_egress_err_status_cnt[30];
3500 static u64 access_tx_sdma13_disallowed_packet_err_cnt(
3501 const struct cntr_entry *entry,
3502 void *context, int vl, int mode, u64 data)
3504 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3506 return dd->send_egress_err_status_cnt[29];
3509 static u64 access_tx_sdma12_disallowed_packet_err_cnt(
3510 const struct cntr_entry *entry,
3511 void *context, int vl, int mode, u64 data)
3513 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3515 return dd->send_egress_err_status_cnt[28];
3518 static u64 access_tx_sdma11_disallowed_packet_err_cnt(
3519 const struct cntr_entry *entry,
3520 void *context, int vl, int mode, u64 data)
3522 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3524 return dd->send_egress_err_status_cnt[27];
3527 static u64 access_tx_sdma10_disallowed_packet_err_cnt(
3528 const struct cntr_entry *entry,
3529 void *context, int vl, int mode, u64 data)
3531 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3533 return dd->send_egress_err_status_cnt[26];
3536 static u64 access_tx_sdma9_disallowed_packet_err_cnt(
3537 const struct cntr_entry *entry,
3538 void *context, int vl, int mode, u64 data)
3540 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3542 return dd->send_egress_err_status_cnt[25];
3545 static u64 access_tx_sdma8_disallowed_packet_err_cnt(
3546 const struct cntr_entry *entry,
3547 void *context, int vl, int mode, u64 data)
3549 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3551 return dd->send_egress_err_status_cnt[24];
3554 static u64 access_tx_sdma7_disallowed_packet_err_cnt(
3555 const struct cntr_entry *entry,
3556 void *context, int vl, int mode, u64 data)
3558 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3560 return dd->send_egress_err_status_cnt[23];
3563 static u64 access_tx_sdma6_disallowed_packet_err_cnt(
3564 const struct cntr_entry *entry,
3565 void *context, int vl, int mode, u64 data)
3567 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3569 return dd->send_egress_err_status_cnt[22];
3572 static u64 access_tx_sdma5_disallowed_packet_err_cnt(
3573 const struct cntr_entry *entry,
3574 void *context, int vl, int mode, u64 data)
3576 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3578 return dd->send_egress_err_status_cnt[21];
3581 static u64 access_tx_sdma4_disallowed_packet_err_cnt(
3582 const struct cntr_entry *entry,
3583 void *context, int vl, int mode, u64 data)
3585 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3587 return dd->send_egress_err_status_cnt[20];
3590 static u64 access_tx_sdma3_disallowed_packet_err_cnt(
3591 const struct cntr_entry *entry,
3592 void *context, int vl, int mode, u64 data)
3594 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3596 return dd->send_egress_err_status_cnt[19];
3599 static u64 access_tx_sdma2_disallowed_packet_err_cnt(
3600 const struct cntr_entry *entry,
3601 void *context, int vl, int mode, u64 data)
3603 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3605 return dd->send_egress_err_status_cnt[18];
3608 static u64 access_tx_sdma1_disallowed_packet_err_cnt(
3609 const struct cntr_entry *entry,
3610 void *context, int vl, int mode, u64 data)
3612 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3614 return dd->send_egress_err_status_cnt[17];
3617 static u64 access_tx_sdma0_disallowed_packet_err_cnt(
3618 const struct cntr_entry *entry,
3619 void *context, int vl, int mode, u64 data)
3621 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3623 return dd->send_egress_err_status_cnt[16];
3626 static u64 access_tx_config_parity_err_cnt(const struct cntr_entry *entry,
3627 void *context, int vl, int mode,
3630 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3632 return dd->send_egress_err_status_cnt[15];
3635 static u64 access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry *entry,
3636 void *context, int vl,
3639 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3641 return dd->send_egress_err_status_cnt[14];
3644 static u64 access_tx_launch_csr_parity_err_cnt(const struct cntr_entry *entry,
3645 void *context, int vl, int mode,
3648 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3650 return dd->send_egress_err_status_cnt[13];
3653 static u64 access_tx_illegal_vl_err_cnt(const struct cntr_entry *entry,
3654 void *context, int vl, int mode,
3657 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3659 return dd->send_egress_err_status_cnt[12];
3662 static u64 access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3663 const struct cntr_entry *entry,
3664 void *context, int vl, int mode, u64 data)
3666 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3668 return dd->send_egress_err_status_cnt[11];
3671 static u64 access_egress_reserved_10_err_cnt(const struct cntr_entry *entry,
3672 void *context, int vl, int mode,
3675 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3677 return dd->send_egress_err_status_cnt[10];
3680 static u64 access_egress_reserved_9_err_cnt(const struct cntr_entry *entry,
3681 void *context, int vl, int mode,
3684 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3686 return dd->send_egress_err_status_cnt[9];
3689 static u64 access_tx_sdma_launch_intf_parity_err_cnt(
3690 const struct cntr_entry *entry,
3691 void *context, int vl, int mode, u64 data)
3693 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3695 return dd->send_egress_err_status_cnt[8];
3698 static u64 access_tx_pio_launch_intf_parity_err_cnt(
3699 const struct cntr_entry *entry,
3700 void *context, int vl, int mode, u64 data)
3702 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3704 return dd->send_egress_err_status_cnt[7];
3707 static u64 access_egress_reserved_6_err_cnt(const struct cntr_entry *entry,
3708 void *context, int vl, int mode,
3711 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3713 return dd->send_egress_err_status_cnt[6];
3716 static u64 access_tx_incorrect_link_state_err_cnt(
3717 const struct cntr_entry *entry,
3718 void *context, int vl, int mode, u64 data)
3720 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3722 return dd->send_egress_err_status_cnt[5];
3725 static u64 access_tx_linkdown_err_cnt(const struct cntr_entry *entry,
3726 void *context, int vl, int mode,
3729 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3731 return dd->send_egress_err_status_cnt[4];
3734 static u64 access_tx_egress_fifi_underrun_or_parity_err_cnt(
3735 const struct cntr_entry *entry,
3736 void *context, int vl, int mode, u64 data)
3738 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3740 return dd->send_egress_err_status_cnt[3];
3743 static u64 access_egress_reserved_2_err_cnt(const struct cntr_entry *entry,
3744 void *context, int vl, int mode,
3747 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3749 return dd->send_egress_err_status_cnt[2];
3752 static u64 access_tx_pkt_integrity_mem_unc_err_cnt(
3753 const struct cntr_entry *entry,
3754 void *context, int vl, int mode, u64 data)
3756 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3758 return dd->send_egress_err_status_cnt[1];
3761 static u64 access_tx_pkt_integrity_mem_cor_err_cnt(
3762 const struct cntr_entry *entry,
3763 void *context, int vl, int mode, u64 data)
3765 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3767 return dd->send_egress_err_status_cnt[0];
3771 * Software counters corresponding to each of the
3772 * error status bits within SendErrStatus
3774 static u64 access_send_csr_write_bad_addr_err_cnt(
3775 const struct cntr_entry *entry,
3776 void *context, int vl, int mode, u64 data)
3778 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3780 return dd->send_err_status_cnt[2];
3783 static u64 access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry *entry,
3784 void *context, int vl,
3787 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3789 return dd->send_err_status_cnt[1];
3792 static u64 access_send_csr_parity_cnt(const struct cntr_entry *entry,
3793 void *context, int vl, int mode,
3796 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3798 return dd->send_err_status_cnt[0];
3802 * Software counters corresponding to each of the
3803 * error status bits within SendCtxtErrStatus
3805 static u64 access_pio_write_out_of_bounds_err_cnt(
3806 const struct cntr_entry *entry,
3807 void *context, int vl, int mode, u64 data)
3809 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3811 return dd->sw_ctxt_err_status_cnt[4];
3814 static u64 access_pio_write_overflow_err_cnt(const struct cntr_entry *entry,
3815 void *context, int vl, int mode,
3818 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3820 return dd->sw_ctxt_err_status_cnt[3];
3823 static u64 access_pio_write_crosses_boundary_err_cnt(
3824 const struct cntr_entry *entry,
3825 void *context, int vl, int mode, u64 data)
3827 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3829 return dd->sw_ctxt_err_status_cnt[2];
3832 static u64 access_pio_disallowed_packet_err_cnt(const struct cntr_entry *entry,
3833 void *context, int vl,
3836 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3838 return dd->sw_ctxt_err_status_cnt[1];
3841 static u64 access_pio_inconsistent_sop_err_cnt(const struct cntr_entry *entry,
3842 void *context, int vl, int mode,
3845 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3847 return dd->sw_ctxt_err_status_cnt[0];
3851 * Software counters corresponding to each of the
3852 * error status bits within SendDmaEngErrStatus
3854 static u64 access_sdma_header_request_fifo_cor_err_cnt(
3855 const struct cntr_entry *entry,
3856 void *context, int vl, int mode, u64 data)
3858 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3860 return dd->sw_send_dma_eng_err_status_cnt[23];
3863 static u64 access_sdma_header_storage_cor_err_cnt(
3864 const struct cntr_entry *entry,
3865 void *context, int vl, int mode, u64 data)
3867 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3869 return dd->sw_send_dma_eng_err_status_cnt[22];
3872 static u64 access_sdma_packet_tracking_cor_err_cnt(
3873 const struct cntr_entry *entry,
3874 void *context, int vl, int mode, u64 data)
3876 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3878 return dd->sw_send_dma_eng_err_status_cnt[21];
3881 static u64 access_sdma_assembly_cor_err_cnt(const struct cntr_entry *entry,
3882 void *context, int vl, int mode,
3885 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3887 return dd->sw_send_dma_eng_err_status_cnt[20];
3890 static u64 access_sdma_desc_table_cor_err_cnt(const struct cntr_entry *entry,
3891 void *context, int vl, int mode,
3894 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3896 return dd->sw_send_dma_eng_err_status_cnt[19];
3899 static u64 access_sdma_header_request_fifo_unc_err_cnt(
3900 const struct cntr_entry *entry,
3901 void *context, int vl, int mode, u64 data)
3903 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3905 return dd->sw_send_dma_eng_err_status_cnt[18];
3908 static u64 access_sdma_header_storage_unc_err_cnt(
3909 const struct cntr_entry *entry,
3910 void *context, int vl, int mode, u64 data)
3912 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3914 return dd->sw_send_dma_eng_err_status_cnt[17];
3917 static u64 access_sdma_packet_tracking_unc_err_cnt(
3918 const struct cntr_entry *entry,
3919 void *context, int vl, int mode, u64 data)
3921 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3923 return dd->sw_send_dma_eng_err_status_cnt[16];
3926 static u64 access_sdma_assembly_unc_err_cnt(const struct cntr_entry *entry,
3927 void *context, int vl, int mode,
3930 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3932 return dd->sw_send_dma_eng_err_status_cnt[15];
3935 static u64 access_sdma_desc_table_unc_err_cnt(const struct cntr_entry *entry,
3936 void *context, int vl, int mode,
3939 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3941 return dd->sw_send_dma_eng_err_status_cnt[14];
3944 static u64 access_sdma_timeout_err_cnt(const struct cntr_entry *entry,
3945 void *context, int vl, int mode,
3948 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3950 return dd->sw_send_dma_eng_err_status_cnt[13];
3953 static u64 access_sdma_header_length_err_cnt(const struct cntr_entry *entry,
3954 void *context, int vl, int mode,
3957 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3959 return dd->sw_send_dma_eng_err_status_cnt[12];
3962 static u64 access_sdma_header_address_err_cnt(const struct cntr_entry *entry,
3963 void *context, int vl, int mode,
3966 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3968 return dd->sw_send_dma_eng_err_status_cnt[11];
3971 static u64 access_sdma_header_select_err_cnt(const struct cntr_entry *entry,
3972 void *context, int vl, int mode,
3975 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3977 return dd->sw_send_dma_eng_err_status_cnt[10];
3980 static u64 access_sdma_reserved_9_err_cnt(const struct cntr_entry *entry,
3981 void *context, int vl, int mode,
3984 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3986 return dd->sw_send_dma_eng_err_status_cnt[9];
3989 static u64 access_sdma_packet_desc_overflow_err_cnt(
3990 const struct cntr_entry *entry,
3991 void *context, int vl, int mode, u64 data)
3993 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
3995 return dd->sw_send_dma_eng_err_status_cnt[8];
3998 static u64 access_sdma_length_mismatch_err_cnt(const struct cntr_entry *entry,
3999 void *context, int vl,
4002 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4004 return dd->sw_send_dma_eng_err_status_cnt[7];
4007 static u64 access_sdma_halt_err_cnt(const struct cntr_entry *entry,
4008 void *context, int vl, int mode, u64 data)
4010 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4012 return dd->sw_send_dma_eng_err_status_cnt[6];
4015 static u64 access_sdma_mem_read_err_cnt(const struct cntr_entry *entry,
4016 void *context, int vl, int mode,
4019 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4021 return dd->sw_send_dma_eng_err_status_cnt[5];
4024 static u64 access_sdma_first_desc_err_cnt(const struct cntr_entry *entry,
4025 void *context, int vl, int mode,
4028 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4030 return dd->sw_send_dma_eng_err_status_cnt[4];
4033 static u64 access_sdma_tail_out_of_bounds_err_cnt(
4034 const struct cntr_entry *entry,
4035 void *context, int vl, int mode, u64 data)
4037 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4039 return dd->sw_send_dma_eng_err_status_cnt[3];
4042 static u64 access_sdma_too_long_err_cnt(const struct cntr_entry *entry,
4043 void *context, int vl, int mode,
4046 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4048 return dd->sw_send_dma_eng_err_status_cnt[2];
4051 static u64 access_sdma_gen_mismatch_err_cnt(const struct cntr_entry *entry,
4052 void *context, int vl, int mode,
4055 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4057 return dd->sw_send_dma_eng_err_status_cnt[1];
4060 static u64 access_sdma_wrong_dw_err_cnt(const struct cntr_entry *entry,
4061 void *context, int vl, int mode,
4064 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4066 return dd->sw_send_dma_eng_err_status_cnt[0];
4069 static u64 access_dc_rcv_err_cnt(const struct cntr_entry *entry,
4070 void *context, int vl, int mode,
4073 struct hfi1_devdata *dd = (struct hfi1_devdata *)context;
4076 u64 csr = entry->csr;
4078 val = read_write_csr(dd, csr, mode, data);
4079 if (mode == CNTR_MODE_R) {
4080 val = val > CNTR_MAX - dd->sw_rcv_bypass_packet_errors ?
4081 CNTR_MAX : val + dd->sw_rcv_bypass_packet_errors;
4082 } else if (mode == CNTR_MODE_W) {
4083 dd->sw_rcv_bypass_packet_errors = 0;
4085 dd_dev_err(dd, "Invalid cntr register access mode");
4091 #define def_access_sw_cpu(cntr) \
4092 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
4093 void *context, int vl, int mode, u64 data) \
4095 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4096 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
4097 ppd->ibport_data.rvp.cntr, vl, \
4101 def_access_sw_cpu(rc_acks);
4102 def_access_sw_cpu(rc_qacks);
4103 def_access_sw_cpu(rc_delayed_comp);
4105 #define def_access_ibp_counter(cntr) \
4106 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
4107 void *context, int vl, int mode, u64 data) \
4109 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4111 if (vl != CNTR_INVALID_VL) \
4114 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
4118 def_access_ibp_counter(loop_pkts);
4119 def_access_ibp_counter(rc_resends);
4120 def_access_ibp_counter(rnr_naks);
4121 def_access_ibp_counter(other_naks);
4122 def_access_ibp_counter(rc_timeouts);
4123 def_access_ibp_counter(pkt_drops);
4124 def_access_ibp_counter(dmawait);
4125 def_access_ibp_counter(rc_seqnak);
4126 def_access_ibp_counter(rc_dupreq);
4127 def_access_ibp_counter(rdma_seq);
4128 def_access_ibp_counter(unaligned);
4129 def_access_ibp_counter(seq_naks);
4130 def_access_ibp_counter(rc_crwaits);
4132 static struct cntr_entry dev_cntrs[DEV_CNTR_LAST] = {
4133 [C_RCV_OVF] = RXE32_DEV_CNTR_ELEM(RcvOverflow, RCV_BUF_OVFL_CNT, CNTR_SYNTH),
4134 [C_RX_LEN_ERR] = RXE32_DEV_CNTR_ELEM(RxLenErr, RCV_LENGTH_ERR_CNT, CNTR_SYNTH),
4135 [C_RX_SHORT_ERR] = RXE32_DEV_CNTR_ELEM(RxShrErr, RCV_SHORT_ERR_CNT, CNTR_SYNTH),
4136 [C_RX_ICRC_ERR] = RXE32_DEV_CNTR_ELEM(RxICrcErr, RCV_ICRC_ERR_CNT, CNTR_SYNTH),
4137 [C_RX_EBP] = RXE32_DEV_CNTR_ELEM(RxEbpCnt, RCV_EBP_CNT, CNTR_SYNTH),
4138 [C_RX_TID_FULL] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr, RCV_TID_FULL_ERR_CNT,
4140 [C_RX_TID_INVALID] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid, RCV_TID_VALID_ERR_CNT,
4142 [C_RX_TID_FLGMS] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs,
4143 RCV_TID_FLOW_GEN_MISMATCH_CNT,
4145 [C_RX_CTX_EGRS] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS, RCV_CONTEXT_EGR_STALL,
4147 [C_RCV_TID_FLSMS] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs,
4148 RCV_TID_FLOW_SEQ_MISMATCH_CNT, CNTR_NORMAL),
4149 [C_CCE_PCI_CR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt,
4150 CCE_PCIE_POSTED_CRDT_STALL_CNT, CNTR_NORMAL),
4151 [C_CCE_PCI_TR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt, CCE_PCIE_TRGT_STALL_CNT,
4153 [C_CCE_PIO_WR_ST] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt, CCE_PIO_WR_STALL_CNT,
4155 [C_CCE_ERR_INT] = CCE_INT_DEV_CNTR_ELEM(CceErrInt, CCE_ERR_INT_CNT,
4157 [C_CCE_SDMA_INT] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt, CCE_SDMA_INT_CNT,
4159 [C_CCE_MISC_INT] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt, CCE_MISC_INT_CNT,
4161 [C_CCE_RCV_AV_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt, CCE_RCV_AVAIL_INT_CNT,
4163 [C_CCE_RCV_URG_INT] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt,
4164 CCE_RCV_URGENT_INT_CNT, CNTR_NORMAL),
4165 [C_CCE_SEND_CR_INT] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt,
4166 CCE_SEND_CREDIT_INT_CNT, CNTR_NORMAL),
4167 [C_DC_UNC_ERR] = DC_PERF_CNTR(DcUnctblErr, DCC_ERR_UNCORRECTABLE_CNT,
4169 [C_DC_RCV_ERR] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT, 0, CNTR_SYNTH,
4170 access_dc_rcv_err_cnt),
4171 [C_DC_FM_CFG_ERR] = DC_PERF_CNTR(DcFmCfgErr, DCC_ERR_FMCONFIG_ERR_CNT,
4173 [C_DC_RMT_PHY_ERR] = DC_PERF_CNTR(DcRmtPhyErr, DCC_ERR_RCVREMOTE_PHY_ERR_CNT,
4175 [C_DC_DROPPED_PKT] = DC_PERF_CNTR(DcDroppedPkt, DCC_ERR_DROPPED_PKT_CNT,
4177 [C_DC_MC_XMIT_PKTS] = DC_PERF_CNTR(DcMcXmitPkts,
4178 DCC_PRF_PORT_XMIT_MULTICAST_CNT, CNTR_SYNTH),
4179 [C_DC_MC_RCV_PKTS] = DC_PERF_CNTR(DcMcRcvPkts,
4180 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT,
4182 [C_DC_XMIT_CERR] = DC_PERF_CNTR(DcXmitCorr,
4183 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT, CNTR_SYNTH),
4184 [C_DC_RCV_CERR] = DC_PERF_CNTR(DcRcvCorrCnt, DCC_PRF_PORT_RCV_CORRECTABLE_CNT,
4186 [C_DC_RCV_FCC] = DC_PERF_CNTR(DcRxFCntl, DCC_PRF_RX_FLOW_CRTL_CNT,
4188 [C_DC_XMIT_FCC] = DC_PERF_CNTR(DcXmitFCntl, DCC_PRF_TX_FLOW_CRTL_CNT,
4190 [C_DC_XMIT_FLITS] = DC_PERF_CNTR(DcXmitFlits, DCC_PRF_PORT_XMIT_DATA_CNT,
4192 [C_DC_RCV_FLITS] = DC_PERF_CNTR(DcRcvFlits, DCC_PRF_PORT_RCV_DATA_CNT,
4194 [C_DC_XMIT_PKTS] = DC_PERF_CNTR(DcXmitPkts, DCC_PRF_PORT_XMIT_PKTS_CNT,
4196 [C_DC_RCV_PKTS] = DC_PERF_CNTR(DcRcvPkts, DCC_PRF_PORT_RCV_PKTS_CNT,
4198 [C_DC_RX_FLIT_VL] = DC_PERF_CNTR(DcRxFlitVl, DCC_PRF_PORT_VL_RCV_DATA_CNT,
4199 CNTR_SYNTH | CNTR_VL),
4200 [C_DC_RX_PKT_VL] = DC_PERF_CNTR(DcRxPktVl, DCC_PRF_PORT_VL_RCV_PKTS_CNT,
4201 CNTR_SYNTH | CNTR_VL),
4202 [C_DC_RCV_FCN] = DC_PERF_CNTR(DcRcvFcn, DCC_PRF_PORT_RCV_FECN_CNT, CNTR_SYNTH),
4203 [C_DC_RCV_FCN_VL] = DC_PERF_CNTR(DcRcvFcnVl, DCC_PRF_PORT_VL_RCV_FECN_CNT,
4204 CNTR_SYNTH | CNTR_VL),
4205 [C_DC_RCV_BCN] = DC_PERF_CNTR(DcRcvBcn, DCC_PRF_PORT_RCV_BECN_CNT, CNTR_SYNTH),
4206 [C_DC_RCV_BCN_VL] = DC_PERF_CNTR(DcRcvBcnVl, DCC_PRF_PORT_VL_RCV_BECN_CNT,
4207 CNTR_SYNTH | CNTR_VL),
4208 [C_DC_RCV_BBL] = DC_PERF_CNTR(DcRcvBbl, DCC_PRF_PORT_RCV_BUBBLE_CNT,
4210 [C_DC_RCV_BBL_VL] = DC_PERF_CNTR(DcRcvBblVl, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT,
4211 CNTR_SYNTH | CNTR_VL),
4212 [C_DC_MARK_FECN] = DC_PERF_CNTR(DcMarkFcn, DCC_PRF_PORT_MARK_FECN_CNT,
4214 [C_DC_MARK_FECN_VL] = DC_PERF_CNTR(DcMarkFcnVl, DCC_PRF_PORT_VL_MARK_FECN_CNT,
4215 CNTR_SYNTH | CNTR_VL),
4217 DC_PERF_CNTR_LCB(DcTotCrc, DC_LCB_ERR_INFO_TOTAL_CRC_ERR,
4219 [C_DC_CRC_LN0] = DC_PERF_CNTR_LCB(DcCrcLn0, DC_LCB_ERR_INFO_CRC_ERR_LN0,
4221 [C_DC_CRC_LN1] = DC_PERF_CNTR_LCB(DcCrcLn1, DC_LCB_ERR_INFO_CRC_ERR_LN1,
4223 [C_DC_CRC_LN2] = DC_PERF_CNTR_LCB(DcCrcLn2, DC_LCB_ERR_INFO_CRC_ERR_LN2,
4225 [C_DC_CRC_LN3] = DC_PERF_CNTR_LCB(DcCrcLn3, DC_LCB_ERR_INFO_CRC_ERR_LN3,
4227 [C_DC_CRC_MULT_LN] =
4228 DC_PERF_CNTR_LCB(DcMultLn, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN,
4230 [C_DC_TX_REPLAY] = DC_PERF_CNTR_LCB(DcTxReplay, DC_LCB_ERR_INFO_TX_REPLAY_CNT,
4232 [C_DC_RX_REPLAY] = DC_PERF_CNTR_LCB(DcRxReplay, DC_LCB_ERR_INFO_RX_REPLAY_CNT,
4234 [C_DC_SEQ_CRC_CNT] =
4235 DC_PERF_CNTR_LCB(DcLinkSeqCrc, DC_LCB_ERR_INFO_SEQ_CRC_CNT,
4237 [C_DC_ESC0_ONLY_CNT] =
4238 DC_PERF_CNTR_LCB(DcEsc0, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT,
4240 [C_DC_ESC0_PLUS1_CNT] =
4241 DC_PERF_CNTR_LCB(DcEsc1, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT,
4243 [C_DC_ESC0_PLUS2_CNT] =
4244 DC_PERF_CNTR_LCB(DcEsc0Plus2, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT,
4246 [C_DC_REINIT_FROM_PEER_CNT] =
4247 DC_PERF_CNTR_LCB(DcReinitPeer, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT,
4249 [C_DC_SBE_CNT] = DC_PERF_CNTR_LCB(DcSbe, DC_LCB_ERR_INFO_SBE_CNT,
4251 [C_DC_MISC_FLG_CNT] =
4252 DC_PERF_CNTR_LCB(DcMiscFlg, DC_LCB_ERR_INFO_MISC_FLG_CNT,
4254 [C_DC_PRF_GOOD_LTP_CNT] =
4255 DC_PERF_CNTR_LCB(DcGoodLTP, DC_LCB_PRF_GOOD_LTP_CNT, CNTR_SYNTH),
4256 [C_DC_PRF_ACCEPTED_LTP_CNT] =
4257 DC_PERF_CNTR_LCB(DcAccLTP, DC_LCB_PRF_ACCEPTED_LTP_CNT,
4259 [C_DC_PRF_RX_FLIT_CNT] =
4260 DC_PERF_CNTR_LCB(DcPrfRxFlit, DC_LCB_PRF_RX_FLIT_CNT, CNTR_SYNTH),
4261 [C_DC_PRF_TX_FLIT_CNT] =
4262 DC_PERF_CNTR_LCB(DcPrfTxFlit, DC_LCB_PRF_TX_FLIT_CNT, CNTR_SYNTH),
4263 [C_DC_PRF_CLK_CNTR] =
4264 DC_PERF_CNTR_LCB(DcPrfClk, DC_LCB_PRF_CLK_CNTR, CNTR_SYNTH),
4265 [C_DC_PG_DBG_FLIT_CRDTS_CNT] =
4266 DC_PERF_CNTR_LCB(DcFltCrdts, DC_LCB_PG_DBG_FLIT_CRDTS_CNT, CNTR_SYNTH),
4267 [C_DC_PG_STS_PAUSE_COMPLETE_CNT] =
4268 DC_PERF_CNTR_LCB(DcPauseComp, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT,
4270 [C_DC_PG_STS_TX_SBE_CNT] =
4271 DC_PERF_CNTR_LCB(DcStsTxSbe, DC_LCB_PG_STS_TX_SBE_CNT, CNTR_SYNTH),
4272 [C_DC_PG_STS_TX_MBE_CNT] =
4273 DC_PERF_CNTR_LCB(DcStsTxMbe, DC_LCB_PG_STS_TX_MBE_CNT,
4275 [C_SW_CPU_INTR] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL,
4276 access_sw_cpu_intr),
4277 [C_SW_CPU_RCV_LIM] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL,
4278 access_sw_cpu_rcv_limit),
4279 [C_SW_CTX0_SEQ_DROP] = CNTR_ELEM("SeqDrop0", 0, 0, CNTR_NORMAL,
4280 access_sw_ctx0_seq_drop),
4281 [C_SW_VTX_WAIT] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL,
4282 access_sw_vtx_wait),
4283 [C_SW_PIO_WAIT] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL,
4284 access_sw_pio_wait),
4285 [C_SW_PIO_DRAIN] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL,
4286 access_sw_pio_drain),
4287 [C_SW_KMEM_WAIT] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL,
4288 access_sw_kmem_wait),
4289 [C_SW_TID_WAIT] = CNTR_ELEM("TidWait", 0, 0, CNTR_NORMAL,
4290 hfi1_access_sw_tid_wait),
4291 [C_SW_SEND_SCHED] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL,
4292 access_sw_send_schedule),
4293 [C_SDMA_DESC_FETCHED_CNT] = CNTR_ELEM("SDEDscFdCn",
4294 SEND_DMA_DESC_FETCHED_CNT, 0,
4295 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4296 dev_access_u32_csr),
4297 [C_SDMA_INT_CNT] = CNTR_ELEM("SDMAInt", 0, 0,
4298 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4299 access_sde_int_cnt),
4300 [C_SDMA_ERR_CNT] = CNTR_ELEM("SDMAErrCt", 0, 0,
4301 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4302 access_sde_err_cnt),
4303 [C_SDMA_IDLE_INT_CNT] = CNTR_ELEM("SDMAIdInt", 0, 0,
4304 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4305 access_sde_idle_int_cnt),
4306 [C_SDMA_PROGRESS_INT_CNT] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4307 CNTR_NORMAL | CNTR_32BIT | CNTR_SDMA,
4308 access_sde_progress_int_cnt),
4309 /* MISC_ERR_STATUS */
4310 [C_MISC_PLL_LOCK_FAIL_ERR] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4312 access_misc_pll_lock_fail_err_cnt),
4313 [C_MISC_MBIST_FAIL_ERR] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4315 access_misc_mbist_fail_err_cnt),
4316 [C_MISC_INVALID_EEP_CMD_ERR] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4318 access_misc_invalid_eep_cmd_err_cnt),
4319 [C_MISC_EFUSE_DONE_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4321 access_misc_efuse_done_parity_err_cnt),
4322 [C_MISC_EFUSE_WRITE_ERR] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4324 access_misc_efuse_write_err_cnt),
4325 [C_MISC_EFUSE_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4327 access_misc_efuse_read_bad_addr_err_cnt),
4328 [C_MISC_EFUSE_CSR_PARITY_ERR] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4330 access_misc_efuse_csr_parity_err_cnt),
4331 [C_MISC_FW_AUTH_FAILED_ERR] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4333 access_misc_fw_auth_failed_err_cnt),
4334 [C_MISC_KEY_MISMATCH_ERR] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4336 access_misc_key_mismatch_err_cnt),
4337 [C_MISC_SBUS_WRITE_FAILED_ERR] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4339 access_misc_sbus_write_failed_err_cnt),
4340 [C_MISC_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4342 access_misc_csr_write_bad_addr_err_cnt),
4343 [C_MISC_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4345 access_misc_csr_read_bad_addr_err_cnt),
4346 [C_MISC_CSR_PARITY_ERR] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4348 access_misc_csr_parity_err_cnt),
4350 [C_CCE_ERR_STATUS_AGGREGATED_CNT] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4352 access_sw_cce_err_status_aggregated_cnt),
4353 [C_CCE_MSIX_CSR_PARITY_ERR] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4355 access_cce_msix_csr_parity_err_cnt),
4356 [C_CCE_INT_MAP_UNC_ERR] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4358 access_cce_int_map_unc_err_cnt),
4359 [C_CCE_INT_MAP_COR_ERR] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4361 access_cce_int_map_cor_err_cnt),
4362 [C_CCE_MSIX_TABLE_UNC_ERR] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4364 access_cce_msix_table_unc_err_cnt),
4365 [C_CCE_MSIX_TABLE_COR_ERR] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4367 access_cce_msix_table_cor_err_cnt),
4368 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4370 access_cce_rxdma_conv_fifo_parity_err_cnt),
4371 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4373 access_cce_rcpl_async_fifo_parity_err_cnt),
4374 [C_CCE_SEG_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4376 access_cce_seg_write_bad_addr_err_cnt),
4377 [C_CCE_SEG_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4379 access_cce_seg_read_bad_addr_err_cnt),
4380 [C_LA_TRIGGERED] = CNTR_ELEM("Cce LATriggered", 0, 0,
4382 access_la_triggered_cnt),
4383 [C_CCE_TRGT_CPL_TIMEOUT_ERR] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4385 access_cce_trgt_cpl_timeout_err_cnt),
4386 [C_PCIC_RECEIVE_PARITY_ERR] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4388 access_pcic_receive_parity_err_cnt),
4389 [C_PCIC_TRANSMIT_BACK_PARITY_ERR] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4391 access_pcic_transmit_back_parity_err_cnt),
4392 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4394 access_pcic_transmit_front_parity_err_cnt),
4395 [C_PCIC_CPL_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4397 access_pcic_cpl_dat_q_unc_err_cnt),
4398 [C_PCIC_CPL_HD_Q_UNC_ERR] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4400 access_pcic_cpl_hd_q_unc_err_cnt),
4401 [C_PCIC_POST_DAT_Q_UNC_ERR] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4403 access_pcic_post_dat_q_unc_err_cnt),
4404 [C_PCIC_POST_HD_Q_UNC_ERR] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4406 access_pcic_post_hd_q_unc_err_cnt),
4407 [C_PCIC_RETRY_SOT_MEM_UNC_ERR] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4409 access_pcic_retry_sot_mem_unc_err_cnt),
4410 [C_PCIC_RETRY_MEM_UNC_ERR] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4412 access_pcic_retry_mem_unc_err),
4413 [C_PCIC_N_POST_DAT_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4415 access_pcic_n_post_dat_q_parity_err_cnt),
4416 [C_PCIC_N_POST_H_Q_PARITY_ERR] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4418 access_pcic_n_post_h_q_parity_err_cnt),
4419 [C_PCIC_CPL_DAT_Q_COR_ERR] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4421 access_pcic_cpl_dat_q_cor_err_cnt),
4422 [C_PCIC_CPL_HD_Q_COR_ERR] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4424 access_pcic_cpl_hd_q_cor_err_cnt),
4425 [C_PCIC_POST_DAT_Q_COR_ERR] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4427 access_pcic_post_dat_q_cor_err_cnt),
4428 [C_PCIC_POST_HD_Q_COR_ERR] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4430 access_pcic_post_hd_q_cor_err_cnt),
4431 [C_PCIC_RETRY_SOT_MEM_COR_ERR] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4433 access_pcic_retry_sot_mem_cor_err_cnt),
4434 [C_PCIC_RETRY_MEM_COR_ERR] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4436 access_pcic_retry_mem_cor_err_cnt),
4437 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR] = CNTR_ELEM(
4438 "CceCli1AsyncFifoDbgParityError", 0, 0,
4440 access_cce_cli1_async_fifo_dbg_parity_err_cnt),
4441 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR] = CNTR_ELEM(
4442 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4444 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4446 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR] = CNTR_ELEM(
4447 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4449 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt),
4450 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR] = CNTR_ELEM(
4451 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4453 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt),
4454 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4456 access_cce_cli2_async_fifo_parity_err_cnt),
4457 [C_CCE_CSR_CFG_BUS_PARITY_ERR] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4459 access_cce_csr_cfg_bus_parity_err_cnt),
4460 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4462 access_cce_cli0_async_fifo_parity_err_cnt),
4463 [C_CCE_RSPD_DATA_PARITY_ERR] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4465 access_cce_rspd_data_parity_err_cnt),
4466 [C_CCE_TRGT_ACCESS_ERR] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4468 access_cce_trgt_access_err_cnt),
4469 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4471 access_cce_trgt_async_fifo_parity_err_cnt),
4472 [C_CCE_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4474 access_cce_csr_write_bad_addr_err_cnt),
4475 [C_CCE_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4477 access_cce_csr_read_bad_addr_err_cnt),
4478 [C_CCE_CSR_PARITY_ERR] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4480 access_ccs_csr_parity_err_cnt),
4483 [C_RX_CSR_PARITY_ERR] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4485 access_rx_csr_parity_err_cnt),
4486 [C_RX_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4488 access_rx_csr_write_bad_addr_err_cnt),
4489 [C_RX_CSR_READ_BAD_ADDR_ERR] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4491 access_rx_csr_read_bad_addr_err_cnt),
4492 [C_RX_DMA_CSR_UNC_ERR] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4494 access_rx_dma_csr_unc_err_cnt),
4495 [C_RX_DMA_DQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4497 access_rx_dma_dq_fsm_encoding_err_cnt),
4498 [C_RX_DMA_EQ_FSM_ENCODING_ERR] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4500 access_rx_dma_eq_fsm_encoding_err_cnt),
4501 [C_RX_DMA_CSR_PARITY_ERR] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4503 access_rx_dma_csr_parity_err_cnt),
4504 [C_RX_RBUF_DATA_COR_ERR] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4506 access_rx_rbuf_data_cor_err_cnt),
4507 [C_RX_RBUF_DATA_UNC_ERR] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4509 access_rx_rbuf_data_unc_err_cnt),
4510 [C_RX_DMA_DATA_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4512 access_rx_dma_data_fifo_rd_cor_err_cnt),
4513 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4515 access_rx_dma_data_fifo_rd_unc_err_cnt),
4516 [C_RX_DMA_HDR_FIFO_RD_COR_ERR] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4518 access_rx_dma_hdr_fifo_rd_cor_err_cnt),
4519 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4521 access_rx_dma_hdr_fifo_rd_unc_err_cnt),
4522 [C_RX_RBUF_DESC_PART2_COR_ERR] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4524 access_rx_rbuf_desc_part2_cor_err_cnt),
4525 [C_RX_RBUF_DESC_PART2_UNC_ERR] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4527 access_rx_rbuf_desc_part2_unc_err_cnt),
4528 [C_RX_RBUF_DESC_PART1_COR_ERR] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4530 access_rx_rbuf_desc_part1_cor_err_cnt),
4531 [C_RX_RBUF_DESC_PART1_UNC_ERR] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4533 access_rx_rbuf_desc_part1_unc_err_cnt),
4534 [C_RX_HQ_INTR_FSM_ERR] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4536 access_rx_hq_intr_fsm_err_cnt),
4537 [C_RX_HQ_INTR_CSR_PARITY_ERR] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4539 access_rx_hq_intr_csr_parity_err_cnt),
4540 [C_RX_LOOKUP_CSR_PARITY_ERR] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4542 access_rx_lookup_csr_parity_err_cnt),
4543 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4545 access_rx_lookup_rcv_array_cor_err_cnt),
4546 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4548 access_rx_lookup_rcv_array_unc_err_cnt),
4549 [C_RX_LOOKUP_DES_PART2_PARITY_ERR] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4551 access_rx_lookup_des_part2_parity_err_cnt),
4552 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4554 access_rx_lookup_des_part1_unc_cor_err_cnt),
4555 [C_RX_LOOKUP_DES_PART1_UNC_ERR] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4557 access_rx_lookup_des_part1_unc_err_cnt),
4558 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4560 access_rx_rbuf_next_free_buf_cor_err_cnt),
4561 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4563 access_rx_rbuf_next_free_buf_unc_err_cnt),
4564 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR] = CNTR_ELEM(
4565 "RxRbufFlInitWrAddrParityErr", 0, 0,
4567 access_rbuf_fl_init_wr_addr_parity_err_cnt),
4568 [C_RX_RBUF_FL_INITDONE_PARITY_ERR] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4570 access_rx_rbuf_fl_initdone_parity_err_cnt),
4571 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4573 access_rx_rbuf_fl_write_addr_parity_err_cnt),
4574 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4576 access_rx_rbuf_fl_rd_addr_parity_err_cnt),
4577 [C_RX_RBUF_EMPTY_ERR] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4579 access_rx_rbuf_empty_err_cnt),
4580 [C_RX_RBUF_FULL_ERR] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4582 access_rx_rbuf_full_err_cnt),
4583 [C_RX_RBUF_BAD_LOOKUP_ERR] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4585 access_rbuf_bad_lookup_err_cnt),
4586 [C_RX_RBUF_CTX_ID_PARITY_ERR] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4588 access_rbuf_ctx_id_parity_err_cnt),
4589 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4591 access_rbuf_csr_qeopdw_parity_err_cnt),
4592 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR] = CNTR_ELEM(
4593 "RxRbufCsrQNumOfPktParityErr", 0, 0,
4595 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt),
4596 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR] = CNTR_ELEM(
4597 "RxRbufCsrQTlPtrParityErr", 0, 0,
4599 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt),
4600 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4602 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt),
4603 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4605 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt),
4606 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4608 access_rx_rbuf_csr_q_next_buf_parity_err_cnt),
4609 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4611 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt),
4612 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR] = CNTR_ELEM(
4613 "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4615 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt),
4616 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4618 access_rx_rbuf_block_list_read_cor_err_cnt),
4619 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4621 access_rx_rbuf_block_list_read_unc_err_cnt),
4622 [C_RX_RBUF_LOOKUP_DES_COR_ERR] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4624 access_rx_rbuf_lookup_des_cor_err_cnt),
4625 [C_RX_RBUF_LOOKUP_DES_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4627 access_rx_rbuf_lookup_des_unc_err_cnt),
4628 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR] = CNTR_ELEM(
4629 "RxRbufLookupDesRegUncCorErr", 0, 0,
4631 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt),
4632 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4634 access_rx_rbuf_lookup_des_reg_unc_err_cnt),
4635 [C_RX_RBUF_FREE_LIST_COR_ERR] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4637 access_rx_rbuf_free_list_cor_err_cnt),
4638 [C_RX_RBUF_FREE_LIST_UNC_ERR] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4640 access_rx_rbuf_free_list_unc_err_cnt),
4641 [C_RX_RCV_FSM_ENCODING_ERR] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4643 access_rx_rcv_fsm_encoding_err_cnt),
4644 [C_RX_DMA_FLAG_COR_ERR] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4646 access_rx_dma_flag_cor_err_cnt),
4647 [C_RX_DMA_FLAG_UNC_ERR] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4649 access_rx_dma_flag_unc_err_cnt),
4650 [C_RX_DC_SOP_EOP_PARITY_ERR] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4652 access_rx_dc_sop_eop_parity_err_cnt),
4653 [C_RX_RCV_CSR_PARITY_ERR] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4655 access_rx_rcv_csr_parity_err_cnt),
4656 [C_RX_RCV_QP_MAP_TABLE_COR_ERR] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4658 access_rx_rcv_qp_map_table_cor_err_cnt),
4659 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4661 access_rx_rcv_qp_map_table_unc_err_cnt),
4662 [C_RX_RCV_DATA_COR_ERR] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4664 access_rx_rcv_data_cor_err_cnt),
4665 [C_RX_RCV_DATA_UNC_ERR] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4667 access_rx_rcv_data_unc_err_cnt),
4668 [C_RX_RCV_HDR_COR_ERR] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4670 access_rx_rcv_hdr_cor_err_cnt),
4671 [C_RX_RCV_HDR_UNC_ERR] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4673 access_rx_rcv_hdr_unc_err_cnt),
4674 [C_RX_DC_INTF_PARITY_ERR] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4676 access_rx_dc_intf_parity_err_cnt),
4677 [C_RX_DMA_CSR_COR_ERR] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4679 access_rx_dma_csr_cor_err_cnt),
4680 /* SendPioErrStatus */
4681 [C_PIO_PEC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4683 access_pio_pec_sop_head_parity_err_cnt),
4684 [C_PIO_PCC_SOP_HEAD_PARITY_ERR] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4686 access_pio_pcc_sop_head_parity_err_cnt),
4687 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR] = CNTR_ELEM("PioLastReturnedCntParityErr",
4689 access_pio_last_returned_cnt_parity_err_cnt),
4690 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4692 access_pio_current_free_cnt_parity_err_cnt),
4693 [C_PIO_RSVD_31_ERR] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4695 access_pio_reserved_31_err_cnt),
4696 [C_PIO_RSVD_30_ERR] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4698 access_pio_reserved_30_err_cnt),
4699 [C_PIO_PPMC_SOP_LEN_ERR] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4701 access_pio_ppmc_sop_len_err_cnt),
4702 [C_PIO_PPMC_BQC_MEM_PARITY_ERR] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4704 access_pio_ppmc_bqc_mem_parity_err_cnt),
4705 [C_PIO_VL_FIFO_PARITY_ERR] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4707 access_pio_vl_fifo_parity_err_cnt),
4708 [C_PIO_VLF_SOP_PARITY_ERR] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4710 access_pio_vlf_sop_parity_err_cnt),
4711 [C_PIO_VLF_V1_LEN_PARITY_ERR] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4713 access_pio_vlf_v1_len_parity_err_cnt),
4714 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4716 access_pio_block_qw_count_parity_err_cnt),
4717 [C_PIO_WRITE_QW_VALID_PARITY_ERR] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4719 access_pio_write_qw_valid_parity_err_cnt),
4720 [C_PIO_STATE_MACHINE_ERR] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4722 access_pio_state_machine_err_cnt),
4723 [C_PIO_WRITE_DATA_PARITY_ERR] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4725 access_pio_write_data_parity_err_cnt),
4726 [C_PIO_HOST_ADDR_MEM_COR_ERR] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4728 access_pio_host_addr_mem_cor_err_cnt),
4729 [C_PIO_HOST_ADDR_MEM_UNC_ERR] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4731 access_pio_host_addr_mem_unc_err_cnt),
4732 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4734 access_pio_pkt_evict_sm_or_arb_sm_err_cnt),
4735 [C_PIO_INIT_SM_IN_ERR] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4737 access_pio_init_sm_in_err_cnt),
4738 [C_PIO_PPMC_PBL_FIFO_ERR] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4740 access_pio_ppmc_pbl_fifo_err_cnt),
4741 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4743 access_pio_credit_ret_fifo_parity_err_cnt),
4744 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4746 access_pio_v1_len_mem_bank1_cor_err_cnt),
4747 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4749 access_pio_v1_len_mem_bank0_cor_err_cnt),
4750 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4752 access_pio_v1_len_mem_bank1_unc_err_cnt),
4753 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4755 access_pio_v1_len_mem_bank0_unc_err_cnt),
4756 [C_PIO_SM_PKT_RESET_PARITY_ERR] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4758 access_pio_sm_pkt_reset_parity_err_cnt),
4759 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4761 access_pio_pkt_evict_fifo_parity_err_cnt),
4762 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR] = CNTR_ELEM(
4763 "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4765 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt),
4766 [C_PIO_SBRDCTL_CRREL_PARITY_ERR] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4768 access_pio_sbrdctl_crrel_parity_err_cnt),
4769 [C_PIO_PEC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4771 access_pio_pec_fifo_parity_err_cnt),
4772 [C_PIO_PCC_FIFO_PARITY_ERR] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4774 access_pio_pcc_fifo_parity_err_cnt),
4775 [C_PIO_SB_MEM_FIFO1_ERR] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4777 access_pio_sb_mem_fifo1_err_cnt),
4778 [C_PIO_SB_MEM_FIFO0_ERR] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4780 access_pio_sb_mem_fifo0_err_cnt),
4781 [C_PIO_CSR_PARITY_ERR] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4783 access_pio_csr_parity_err_cnt),
4784 [C_PIO_WRITE_ADDR_PARITY_ERR] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4786 access_pio_write_addr_parity_err_cnt),
4787 [C_PIO_WRITE_BAD_CTXT_ERR] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4789 access_pio_write_bad_ctxt_err_cnt),
4790 /* SendDmaErrStatus */
4791 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4793 access_sdma_pcie_req_tracking_cor_err_cnt),
4794 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4796 access_sdma_pcie_req_tracking_unc_err_cnt),
4797 [C_SDMA_CSR_PARITY_ERR] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4799 access_sdma_csr_parity_err_cnt),
4800 [C_SDMA_RPY_TAG_ERR] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4802 access_sdma_rpy_tag_err_cnt),
4803 /* SendEgressErrStatus */
4804 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4806 access_tx_read_pio_memory_csr_unc_err_cnt),
4807 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4809 access_tx_read_sdma_memory_csr_err_cnt),
4810 [C_TX_EGRESS_FIFO_COR_ERR] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4812 access_tx_egress_fifo_cor_err_cnt),
4813 [C_TX_READ_PIO_MEMORY_COR_ERR] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4815 access_tx_read_pio_memory_cor_err_cnt),
4816 [C_TX_READ_SDMA_MEMORY_COR_ERR] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4818 access_tx_read_sdma_memory_cor_err_cnt),
4819 [C_TX_SB_HDR_COR_ERR] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4821 access_tx_sb_hdr_cor_err_cnt),
4822 [C_TX_CREDIT_OVERRUN_ERR] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4824 access_tx_credit_overrun_err_cnt),
4825 [C_TX_LAUNCH_FIFO8_COR_ERR] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4827 access_tx_launch_fifo8_cor_err_cnt),
4828 [C_TX_LAUNCH_FIFO7_COR_ERR] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4830 access_tx_launch_fifo7_cor_err_cnt),
4831 [C_TX_LAUNCH_FIFO6_COR_ERR] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4833 access_tx_launch_fifo6_cor_err_cnt),
4834 [C_TX_LAUNCH_FIFO5_COR_ERR] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4836 access_tx_launch_fifo5_cor_err_cnt),
4837 [C_TX_LAUNCH_FIFO4_COR_ERR] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4839 access_tx_launch_fifo4_cor_err_cnt),
4840 [C_TX_LAUNCH_FIFO3_COR_ERR] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4842 access_tx_launch_fifo3_cor_err_cnt),
4843 [C_TX_LAUNCH_FIFO2_COR_ERR] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4845 access_tx_launch_fifo2_cor_err_cnt),
4846 [C_TX_LAUNCH_FIFO1_COR_ERR] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4848 access_tx_launch_fifo1_cor_err_cnt),
4849 [C_TX_LAUNCH_FIFO0_COR_ERR] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4851 access_tx_launch_fifo0_cor_err_cnt),
4852 [C_TX_CREDIT_RETURN_VL_ERR] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4854 access_tx_credit_return_vl_err_cnt),
4855 [C_TX_HCRC_INSERTION_ERR] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4857 access_tx_hcrc_insertion_err_cnt),
4858 [C_TX_EGRESS_FIFI_UNC_ERR] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4860 access_tx_egress_fifo_unc_err_cnt),
4861 [C_TX_READ_PIO_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4863 access_tx_read_pio_memory_unc_err_cnt),
4864 [C_TX_READ_SDMA_MEMORY_UNC_ERR] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4866 access_tx_read_sdma_memory_unc_err_cnt),
4867 [C_TX_SB_HDR_UNC_ERR] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4869 access_tx_sb_hdr_unc_err_cnt),
4870 [C_TX_CREDIT_RETURN_PARITY_ERR] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4872 access_tx_credit_return_partiy_err_cnt),
4873 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4875 access_tx_launch_fifo8_unc_or_parity_err_cnt),
4876 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4878 access_tx_launch_fifo7_unc_or_parity_err_cnt),
4879 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4881 access_tx_launch_fifo6_unc_or_parity_err_cnt),
4882 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4884 access_tx_launch_fifo5_unc_or_parity_err_cnt),
4885 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4887 access_tx_launch_fifo4_unc_or_parity_err_cnt),
4888 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4890 access_tx_launch_fifo3_unc_or_parity_err_cnt),
4891 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4893 access_tx_launch_fifo2_unc_or_parity_err_cnt),
4894 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4896 access_tx_launch_fifo1_unc_or_parity_err_cnt),
4897 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4899 access_tx_launch_fifo0_unc_or_parity_err_cnt),
4900 [C_TX_SDMA15_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4902 access_tx_sdma15_disallowed_packet_err_cnt),
4903 [C_TX_SDMA14_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4905 access_tx_sdma14_disallowed_packet_err_cnt),
4906 [C_TX_SDMA13_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4908 access_tx_sdma13_disallowed_packet_err_cnt),
4909 [C_TX_SDMA12_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4911 access_tx_sdma12_disallowed_packet_err_cnt),
4912 [C_TX_SDMA11_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4914 access_tx_sdma11_disallowed_packet_err_cnt),
4915 [C_TX_SDMA10_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4917 access_tx_sdma10_disallowed_packet_err_cnt),
4918 [C_TX_SDMA9_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4920 access_tx_sdma9_disallowed_packet_err_cnt),
4921 [C_TX_SDMA8_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4923 access_tx_sdma8_disallowed_packet_err_cnt),
4924 [C_TX_SDMA7_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4926 access_tx_sdma7_disallowed_packet_err_cnt),
4927 [C_TX_SDMA6_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4929 access_tx_sdma6_disallowed_packet_err_cnt),
4930 [C_TX_SDMA5_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4932 access_tx_sdma5_disallowed_packet_err_cnt),
4933 [C_TX_SDMA4_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4935 access_tx_sdma4_disallowed_packet_err_cnt),
4936 [C_TX_SDMA3_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4938 access_tx_sdma3_disallowed_packet_err_cnt),
4939 [C_TX_SDMA2_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4941 access_tx_sdma2_disallowed_packet_err_cnt),
4942 [C_TX_SDMA1_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4944 access_tx_sdma1_disallowed_packet_err_cnt),
4945 [C_TX_SDMA0_DISALLOWED_PACKET_ERR] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4947 access_tx_sdma0_disallowed_packet_err_cnt),
4948 [C_TX_CONFIG_PARITY_ERR] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4950 access_tx_config_parity_err_cnt),
4951 [C_TX_SBRD_CTL_CSR_PARITY_ERR] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4953 access_tx_sbrd_ctl_csr_parity_err_cnt),
4954 [C_TX_LAUNCH_CSR_PARITY_ERR] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4956 access_tx_launch_csr_parity_err_cnt),
4957 [C_TX_ILLEGAL_CL_ERR] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4959 access_tx_illegal_vl_err_cnt),
4960 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR] = CNTR_ELEM(
4961 "TxSbrdCtlStateMachineParityErr", 0, 0,
4963 access_tx_sbrd_ctl_state_machine_parity_err_cnt),
4964 [C_TX_RESERVED_10] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4966 access_egress_reserved_10_err_cnt),
4967 [C_TX_RESERVED_9] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4969 access_egress_reserved_9_err_cnt),
4970 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4972 access_tx_sdma_launch_intf_parity_err_cnt),
4973 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4975 access_tx_pio_launch_intf_parity_err_cnt),
4976 [C_TX_RESERVED_6] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4978 access_egress_reserved_6_err_cnt),
4979 [C_TX_INCORRECT_LINK_STATE_ERR] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4981 access_tx_incorrect_link_state_err_cnt),
4982 [C_TX_LINK_DOWN_ERR] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4984 access_tx_linkdown_err_cnt),
4985 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR] = CNTR_ELEM(
4986 "EgressFifoUnderrunOrParityErr", 0, 0,
4988 access_tx_egress_fifi_underrun_or_parity_err_cnt),
4989 [C_TX_RESERVED_2] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4991 access_egress_reserved_2_err_cnt),
4992 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4994 access_tx_pkt_integrity_mem_unc_err_cnt),
4995 [C_TX_PKT_INTEGRITY_MEM_COR_ERR] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4997 access_tx_pkt_integrity_mem_cor_err_cnt),
4999 [C_SEND_CSR_WRITE_BAD_ADDR_ERR] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
5001 access_send_csr_write_bad_addr_err_cnt),
5002 [C_SEND_CSR_READ_BAD_ADD_ERR] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
5004 access_send_csr_read_bad_addr_err_cnt),
5005 [C_SEND_CSR_PARITY_ERR] = CNTR_ELEM("SendCsrParityErr", 0, 0,
5007 access_send_csr_parity_cnt),
5008 /* SendCtxtErrStatus */
5009 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
5011 access_pio_write_out_of_bounds_err_cnt),
5012 [C_PIO_WRITE_OVERFLOW_ERR] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
5014 access_pio_write_overflow_err_cnt),
5015 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
5017 access_pio_write_crosses_boundary_err_cnt),
5018 [C_PIO_DISALLOWED_PACKET_ERR] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
5020 access_pio_disallowed_packet_err_cnt),
5021 [C_PIO_INCONSISTENT_SOP_ERR] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
5023 access_pio_inconsistent_sop_err_cnt),
5024 /* SendDmaEngErrStatus */
5025 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
5027 access_sdma_header_request_fifo_cor_err_cnt),
5028 [C_SDMA_HEADER_STORAGE_COR_ERR] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
5030 access_sdma_header_storage_cor_err_cnt),
5031 [C_SDMA_PACKET_TRACKING_COR_ERR] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
5033 access_sdma_packet_tracking_cor_err_cnt),
5034 [C_SDMA_ASSEMBLY_COR_ERR] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
5036 access_sdma_assembly_cor_err_cnt),
5037 [C_SDMA_DESC_TABLE_COR_ERR] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
5039 access_sdma_desc_table_cor_err_cnt),
5040 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
5042 access_sdma_header_request_fifo_unc_err_cnt),
5043 [C_SDMA_HEADER_STORAGE_UNC_ERR] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
5045 access_sdma_header_storage_unc_err_cnt),
5046 [C_SDMA_PACKET_TRACKING_UNC_ERR] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
5048 access_sdma_packet_tracking_unc_err_cnt),
5049 [C_SDMA_ASSEMBLY_UNC_ERR] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
5051 access_sdma_assembly_unc_err_cnt),
5052 [C_SDMA_DESC_TABLE_UNC_ERR] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
5054 access_sdma_desc_table_unc_err_cnt),
5055 [C_SDMA_TIMEOUT_ERR] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
5057 access_sdma_timeout_err_cnt),
5058 [C_SDMA_HEADER_LENGTH_ERR] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
5060 access_sdma_header_length_err_cnt),
5061 [C_SDMA_HEADER_ADDRESS_ERR] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
5063 access_sdma_header_address_err_cnt),
5064 [C_SDMA_HEADER_SELECT_ERR] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
5066 access_sdma_header_select_err_cnt),
5067 [C_SMDA_RESERVED_9] = CNTR_ELEM("SDma Reserved 9", 0, 0,
5069 access_sdma_reserved_9_err_cnt),
5070 [C_SDMA_PACKET_DESC_OVERFLOW_ERR] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
5072 access_sdma_packet_desc_overflow_err_cnt),
5073 [C_SDMA_LENGTH_MISMATCH_ERR] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
5075 access_sdma_length_mismatch_err_cnt),
5076 [C_SDMA_HALT_ERR] = CNTR_ELEM("SDmaHaltErr", 0, 0,
5078 access_sdma_halt_err_cnt),
5079 [C_SDMA_MEM_READ_ERR] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
5081 access_sdma_mem_read_err_cnt),
5082 [C_SDMA_FIRST_DESC_ERR] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
5084 access_sdma_first_desc_err_cnt),
5085 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
5087 access_sdma_tail_out_of_bounds_err_cnt),
5088 [C_SDMA_TOO_LONG_ERR] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
5090 access_sdma_too_long_err_cnt),
5091 [C_SDMA_GEN_MISMATCH_ERR] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
5093 access_sdma_gen_mismatch_err_cnt),
5094 [C_SDMA_WRONG_DW_ERR] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
5096 access_sdma_wrong_dw_err_cnt),
5099 static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
5100 [C_TX_UNSUP_VL] = TXE32_PORT_CNTR_ELEM(TxUnVLErr, SEND_UNSUP_VL_ERR_CNT,
5102 [C_TX_INVAL_LEN] = TXE32_PORT_CNTR_ELEM(TxInvalLen, SEND_LEN_ERR_CNT,
5104 [C_TX_MM_LEN_ERR] = TXE32_PORT_CNTR_ELEM(TxMMLenErr, SEND_MAX_MIN_LEN_ERR_CNT,
5106 [C_TX_UNDERRUN] = TXE32_PORT_CNTR_ELEM(TxUnderrun, SEND_UNDERRUN_CNT,
5108 [C_TX_FLOW_STALL] = TXE32_PORT_CNTR_ELEM(TxFlowStall, SEND_FLOW_STALL_CNT,
5110 [C_TX_DROPPED] = TXE32_PORT_CNTR_ELEM(TxDropped, SEND_DROPPED_PKT_CNT,
5112 [C_TX_HDR_ERR] = TXE32_PORT_CNTR_ELEM(TxHdrErr, SEND_HEADERS_ERR_CNT,
5114 [C_TX_PKT] = TXE64_PORT_CNTR_ELEM(TxPkt, SEND_DATA_PKT_CNT, CNTR_NORMAL),
5115 [C_TX_WORDS] = TXE64_PORT_CNTR_ELEM(TxWords, SEND_DWORD_CNT, CNTR_NORMAL),
5116 [C_TX_WAIT] = TXE64_PORT_CNTR_ELEM(TxWait, SEND_WAIT_CNT, CNTR_SYNTH),
5117 [C_TX_FLIT_VL] = TXE64_PORT_CNTR_ELEM(TxFlitVL, SEND_DATA_VL0_CNT,
5118 CNTR_SYNTH | CNTR_VL),
5119 [C_TX_PKT_VL] = TXE64_PORT_CNTR_ELEM(TxPktVL, SEND_DATA_PKT_VL0_CNT,
5120 CNTR_SYNTH | CNTR_VL),
5121 [C_TX_WAIT_VL] = TXE64_PORT_CNTR_ELEM(TxWaitVL, SEND_WAIT_VL0_CNT,
5122 CNTR_SYNTH | CNTR_VL),
5123 [C_RX_PKT] = RXE64_PORT_CNTR_ELEM(RxPkt, RCV_DATA_PKT_CNT, CNTR_NORMAL),
5124 [C_RX_WORDS] = RXE64_PORT_CNTR_ELEM(RxWords, RCV_DWORD_CNT, CNTR_NORMAL),
5125 [C_SW_LINK_DOWN] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5126 access_sw_link_dn_cnt),
5127 [C_SW_LINK_UP] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5128 access_sw_link_up_cnt),
5129 [C_SW_UNKNOWN_FRAME] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL,
5130 access_sw_unknown_frame_cnt),
5131 [C_SW_XMIT_DSCD] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH | CNTR_32BIT,
5132 access_sw_xmit_discards),
5133 [C_SW_XMIT_DSCD_VL] = CNTR_ELEM("XmitDscdVl", 0, 0,
5134 CNTR_SYNTH | CNTR_32BIT | CNTR_VL,
5135 access_sw_xmit_discards),
5136 [C_SW_XMIT_CSTR_ERR] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH,
5137 access_xmit_constraint_errs),
5138 [C_SW_RCV_CSTR_ERR] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH,
5139 access_rcv_constraint_errs),
5140 [C_SW_IBP_LOOP_PKTS] = SW_IBP_CNTR(LoopPkts, loop_pkts),
5141 [C_SW_IBP_RC_RESENDS] = SW_IBP_CNTR(RcResend, rc_resends),
5142 [C_SW_IBP_RNR_NAKS] = SW_IBP_CNTR(RnrNak, rnr_naks),
5143 [C_SW_IBP_OTHER_NAKS] = SW_IBP_CNTR(OtherNak, other_naks),
5144 [C_SW_IBP_RC_TIMEOUTS] = SW_IBP_CNTR(RcTimeOut, rc_timeouts),
5145 [C_SW_IBP_PKT_DROPS] = SW_IBP_CNTR(PktDrop, pkt_drops),
5146 [C_SW_IBP_DMA_WAIT] = SW_IBP_CNTR(DmaWait, dmawait),
5147 [C_SW_IBP_RC_SEQNAK] = SW_IBP_CNTR(RcSeqNak, rc_seqnak),
5148 [C_SW_IBP_RC_DUPREQ] = SW_IBP_CNTR(RcDupRew, rc_dupreq),
5149 [C_SW_IBP_RDMA_SEQ] = SW_IBP_CNTR(RdmaSeq, rdma_seq),
5150 [C_SW_IBP_UNALIGNED] = SW_IBP_CNTR(Unaligned, unaligned),
5151 [C_SW_IBP_SEQ_NAK] = SW_IBP_CNTR(SeqNak, seq_naks),
5152 [C_SW_IBP_RC_CRWAITS] = SW_IBP_CNTR(RcCrWait, rc_crwaits),
5153 [C_SW_CPU_RC_ACKS] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL,
5154 access_sw_cpu_rc_acks),
5155 [C_SW_CPU_RC_QACKS] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL,
5156 access_sw_cpu_rc_qacks),
5157 [C_SW_CPU_RC_DELAYED_COMP] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL,
5158 access_sw_cpu_rc_delayed_comp),
5159 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5160 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5161 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5162 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5163 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5164 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5165 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5166 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5167 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5168 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5169 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5170 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5171 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5172 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5173 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5174 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5175 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5176 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5177 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5178 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5179 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5180 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5181 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5182 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5183 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5184 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5185 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5186 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5187 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5188 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5189 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5190 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5191 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5192 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5193 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5194 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5195 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5196 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5197 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5198 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5199 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5200 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5201 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5202 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5203 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5204 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5205 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5206 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5207 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5208 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5209 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5210 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5211 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5212 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5213 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5214 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5215 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5216 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5217 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5218 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5219 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5220 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5221 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5222 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5223 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5224 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5225 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5226 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5227 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5228 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5229 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5230 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5231 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5232 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5233 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5234 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5235 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5236 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5237 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5238 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5241 /* ======================================================================== */
5243 /* return true if this is chip revision revision a */
5244 int is_ax(struct hfi1_devdata *dd)
5247 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5248 & CCE_REVISION_CHIP_REV_MINOR_MASK;
5249 return (chip_rev_minor & 0xf0) == 0;
5252 /* return true if this is chip revision revision b */
5253 int is_bx(struct hfi1_devdata *dd)
5256 dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5257 & CCE_REVISION_CHIP_REV_MINOR_MASK;
5258 return (chip_rev_minor & 0xF0) == 0x10;
5261 /* return true is kernel urg disabled for rcd */
5262 bool is_urg_masked(struct hfi1_ctxtdata *rcd)
5265 u32 is = IS_RCVURGENT_START + rcd->ctxt;
5268 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64)));
5269 return !(mask & BIT_ULL(bit));
5273 * Append string s to buffer buf. Arguments curp and len are the current
5274 * position and remaining length, respectively.
5276 * return 0 on success, 1 on out of room
5278 static int append_str(char *buf, char **curp, int *lenp, const char *s)
5282 int result = 0; /* success */
5285 /* add a comma, if first in the buffer */
5288 result = 1; /* out of room */
5295 /* copy the string */
5296 while ((c = *s++) != 0) {
5298 result = 1; /* out of room */
5306 /* write return values */
5314 * Using the given flag table, print a comma separated string into
5315 * the buffer. End in '*' if the buffer is too short.
5317 static char *flag_string(char *buf, int buf_len, u64 flags,
5318 struct flag_table *table, int table_size)
5326 /* make sure there is at least 2 so we can form "*" */
5330 len--; /* leave room for a nul */
5331 for (i = 0; i < table_size; i++) {
5332 if (flags & table[i].flag) {
5333 no_room = append_str(buf, &p, &len, table[i].str);
5336 flags &= ~table[i].flag;
5340 /* any undocumented bits left? */
5341 if (!no_room && flags) {
5342 snprintf(extra, sizeof(extra), "bits 0x%llx", flags);
5343 no_room = append_str(buf, &p, &len, extra);
5346 /* add * if ran out of room */
5348 /* may need to back up to add space for a '*' */
5354 /* add final nul - space already allocated above */
5359 /* first 8 CCE error interrupt source names */
5360 static const char * const cce_misc_names[] = {
5361 "CceErrInt", /* 0 */
5362 "RxeErrInt", /* 1 */
5363 "MiscErrInt", /* 2 */
5364 "Reserved3", /* 3 */
5365 "PioErrInt", /* 4 */
5366 "SDmaErrInt", /* 5 */
5367 "EgressErrInt", /* 6 */
5372 * Return the miscellaneous error interrupt name.
5374 static char *is_misc_err_name(char *buf, size_t bsize, unsigned int source)
5376 if (source < ARRAY_SIZE(cce_misc_names))
5377 strncpy(buf, cce_misc_names[source], bsize);
5379 snprintf(buf, bsize, "Reserved%u",
5380 source + IS_GENERAL_ERR_START);
5386 * Return the SDMA engine error interrupt name.
5388 static char *is_sdma_eng_err_name(char *buf, size_t bsize, unsigned int source)
5390 snprintf(buf, bsize, "SDmaEngErrInt%u", source);
5395 * Return the send context error interrupt name.
5397 static char *is_sendctxt_err_name(char *buf, size_t bsize, unsigned int source)
5399 snprintf(buf, bsize, "SendCtxtErrInt%u", source);
5403 static const char * const various_names[] = {
5412 * Return the various interrupt name.
5414 static char *is_various_name(char *buf, size_t bsize, unsigned int source)
5416 if (source < ARRAY_SIZE(various_names))
5417 strncpy(buf, various_names[source], bsize);
5419 snprintf(buf, bsize, "Reserved%u", source + IS_VARIOUS_START);
5424 * Return the DC interrupt name.
5426 static char *is_dc_name(char *buf, size_t bsize, unsigned int source)
5428 static const char * const dc_int_names[] = {
5432 "lbm" /* local block merge */
5435 if (source < ARRAY_SIZE(dc_int_names))
5436 snprintf(buf, bsize, "dc_%s_int", dc_int_names[source]);
5438 snprintf(buf, bsize, "DCInt%u", source);
5442 static const char * const sdma_int_names[] = {
5449 * Return the SDMA engine interrupt name.
5451 static char *is_sdma_eng_name(char *buf, size_t bsize, unsigned int source)
5453 /* what interrupt */
5454 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
5456 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
5458 if (likely(what < 3))
5459 snprintf(buf, bsize, "%s%u", sdma_int_names[what], which);
5461 snprintf(buf, bsize, "Invalid SDMA interrupt %u", source);
5466 * Return the receive available interrupt name.
5468 static char *is_rcv_avail_name(char *buf, size_t bsize, unsigned int source)
5470 snprintf(buf, bsize, "RcvAvailInt%u", source);
5475 * Return the receive urgent interrupt name.
5477 static char *is_rcv_urgent_name(char *buf, size_t bsize, unsigned int source)
5479 snprintf(buf, bsize, "RcvUrgentInt%u", source);
5484 * Return the send credit interrupt name.
5486 static char *is_send_credit_name(char *buf, size_t bsize, unsigned int source)
5488 snprintf(buf, bsize, "SendCreditInt%u", source);
5493 * Return the reserved interrupt name.
5495 static char *is_reserved_name(char *buf, size_t bsize, unsigned int source)
5497 snprintf(buf, bsize, "Reserved%u", source + IS_RESERVED_START);
5501 static char *cce_err_status_string(char *buf, int buf_len, u64 flags)
5503 return flag_string(buf, buf_len, flags,
5504 cce_err_status_flags,
5505 ARRAY_SIZE(cce_err_status_flags));
5508 static char *rxe_err_status_string(char *buf, int buf_len, u64 flags)
5510 return flag_string(buf, buf_len, flags,
5511 rxe_err_status_flags,
5512 ARRAY_SIZE(rxe_err_status_flags));
5515 static char *misc_err_status_string(char *buf, int buf_len, u64 flags)
5517 return flag_string(buf, buf_len, flags, misc_err_status_flags,
5518 ARRAY_SIZE(misc_err_status_flags));
5521 static char *pio_err_status_string(char *buf, int buf_len, u64 flags)
5523 return flag_string(buf, buf_len, flags,
5524 pio_err_status_flags,
5525 ARRAY_SIZE(pio_err_status_flags));
5528 static char *sdma_err_status_string(char *buf, int buf_len, u64 flags)
5530 return flag_string(buf, buf_len, flags,
5531 sdma_err_status_flags,
5532 ARRAY_SIZE(sdma_err_status_flags));
5535 static char *egress_err_status_string(char *buf, int buf_len, u64 flags)
5537 return flag_string(buf, buf_len, flags,
5538 egress_err_status_flags,
5539 ARRAY_SIZE(egress_err_status_flags));
5542 static char *egress_err_info_string(char *buf, int buf_len, u64 flags)
5544 return flag_string(buf, buf_len, flags,
5545 egress_err_info_flags,
5546 ARRAY_SIZE(egress_err_info_flags));
5549 static char *send_err_status_string(char *buf, int buf_len, u64 flags)
5551 return flag_string(buf, buf_len, flags,
5552 send_err_status_flags,
5553 ARRAY_SIZE(send_err_status_flags));
5556 static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5562 * For most these errors, there is nothing that can be done except
5563 * report or record it.
5565 dd_dev_info(dd, "CCE Error: %s\n",
5566 cce_err_status_string(buf, sizeof(buf), reg));
5568 if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
5569 is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
5570 /* this error requires a manual drop into SPC freeze mode */
5572 start_freeze_handling(dd->pport, FREEZE_SELF);
5575 for (i = 0; i < NUM_CCE_ERR_STATUS_COUNTERS; i++) {
5576 if (reg & (1ull << i)) {
5577 incr_cntr64(&dd->cce_err_status_cnt[i]);
5578 /* maintain a counter over all cce_err_status errors */
5579 incr_cntr64(&dd->sw_cce_err_status_aggregate);
5585 * Check counters for receive errors that do not have an interrupt
5586 * associated with them.
5588 #define RCVERR_CHECK_TIME 10
5589 static void update_rcverr_timer(struct timer_list *t)
5591 struct hfi1_devdata *dd = from_timer(dd, t, rcverr_timer);
5592 struct hfi1_pportdata *ppd = dd->pport;
5593 u32 cur_ovfl_cnt = read_dev_cntr(dd, C_RCV_OVF, CNTR_INVALID_VL);
5595 if (dd->rcv_ovfl_cnt < cur_ovfl_cnt &&
5596 ppd->port_error_action & OPA_PI_MASK_EX_BUFFER_OVERRUN) {
5597 dd_dev_info(dd, "%s: PortErrorAction bounce\n", __func__);
5598 set_link_down_reason(
5599 ppd, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN, 0,
5600 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN);
5601 queue_work(ppd->link_wq, &ppd->link_bounce_work);
5603 dd->rcv_ovfl_cnt = (u32)cur_ovfl_cnt;
5605 mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5608 static int init_rcverr(struct hfi1_devdata *dd)
5610 timer_setup(&dd->rcverr_timer, update_rcverr_timer, 0);
5611 /* Assume the hardware counter has been reset */
5612 dd->rcv_ovfl_cnt = 0;
5613 return mod_timer(&dd->rcverr_timer, jiffies + HZ * RCVERR_CHECK_TIME);
5616 static void free_rcverr(struct hfi1_devdata *dd)
5618 if (dd->rcverr_timer.function)
5619 del_timer_sync(&dd->rcverr_timer);
5622 static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5627 dd_dev_info(dd, "Receive Error: %s\n",
5628 rxe_err_status_string(buf, sizeof(buf), reg));
5630 if (reg & ALL_RXE_FREEZE_ERR) {
5634 * Freeze mode recovery is disabled for the errors
5635 * in RXE_FREEZE_ABORT_MASK
5637 if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
5638 flags = FREEZE_ABORT;
5640 start_freeze_handling(dd->pport, flags);
5643 for (i = 0; i < NUM_RCV_ERR_STATUS_COUNTERS; i++) {
5644 if (reg & (1ull << i))
5645 incr_cntr64(&dd->rcv_err_status_cnt[i]);
5649 static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5654 dd_dev_info(dd, "Misc Error: %s",
5655 misc_err_status_string(buf, sizeof(buf), reg));
5656 for (i = 0; i < NUM_MISC_ERR_STATUS_COUNTERS; i++) {
5657 if (reg & (1ull << i))
5658 incr_cntr64(&dd->misc_err_status_cnt[i]);
5662 static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5667 dd_dev_info(dd, "PIO Error: %s\n",
5668 pio_err_status_string(buf, sizeof(buf), reg));
5670 if (reg & ALL_PIO_FREEZE_ERR)
5671 start_freeze_handling(dd->pport, 0);
5673 for (i = 0; i < NUM_SEND_PIO_ERR_STATUS_COUNTERS; i++) {
5674 if (reg & (1ull << i))
5675 incr_cntr64(&dd->send_pio_err_status_cnt[i]);
5679 static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5684 dd_dev_info(dd, "SDMA Error: %s\n",
5685 sdma_err_status_string(buf, sizeof(buf), reg));
5687 if (reg & ALL_SDMA_FREEZE_ERR)
5688 start_freeze_handling(dd->pport, 0);
5690 for (i = 0; i < NUM_SEND_DMA_ERR_STATUS_COUNTERS; i++) {
5691 if (reg & (1ull << i))
5692 incr_cntr64(&dd->send_dma_err_status_cnt[i]);
5696 static inline void __count_port_discards(struct hfi1_pportdata *ppd)
5698 incr_cntr64(&ppd->port_xmit_discards);
5701 static void count_port_inactive(struct hfi1_devdata *dd)
5703 __count_port_discards(dd->pport);
5707 * We have had a "disallowed packet" error during egress. Determine the
5708 * integrity check which failed, and update relevant error counter, etc.
5710 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5711 * bit of state per integrity check, and so we can miss the reason for an
5712 * egress error if more than one packet fails the same integrity check
5713 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5715 static void handle_send_egress_err_info(struct hfi1_devdata *dd,
5718 struct hfi1_pportdata *ppd = dd->pport;
5719 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
5720 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
5723 /* clear down all observed info as quickly as possible after read */
5724 write_csr(dd, SEND_EGRESS_ERR_INFO, info);
5727 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5728 info, egress_err_info_string(buf, sizeof(buf), info), src);
5730 /* Eventually add other counters for each bit */
5731 if (info & PORT_DISCARD_EGRESS_ERRS) {
5735 * Count all applicable bits as individual errors and
5736 * attribute them to the packet that triggered this handler.
5737 * This may not be completely accurate due to limitations
5738 * on the available hardware error information. There is
5739 * a single information register and any number of error
5740 * packets may have occurred and contributed to it before
5741 * this routine is called. This means that:
5742 * a) If multiple packets with the same error occur before
5743 * this routine is called, earlier packets are missed.
5744 * There is only a single bit for each error type.
5745 * b) Errors may not be attributed to the correct VL.
5746 * The driver is attributing all bits in the info register
5747 * to the packet that triggered this call, but bits
5748 * could be an accumulation of different packets with
5750 * c) A single error packet may have multiple counts attached
5751 * to it. There is no way for the driver to know if
5752 * multiple bits set in the info register are due to a
5753 * single packet or multiple packets. The driver assumes
5756 weight = hweight64(info & PORT_DISCARD_EGRESS_ERRS);
5757 for (i = 0; i < weight; i++) {
5758 __count_port_discards(ppd);
5759 if (vl >= 0 && vl < TXE_NUM_DATA_VL)
5760 incr_cntr64(&ppd->port_xmit_discards_vl[vl]);
5762 incr_cntr64(&ppd->port_xmit_discards_vl
5769 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5770 * register. Does it represent a 'port inactive' error?
5772 static inline int port_inactive_err(u64 posn)
5774 return (posn >= SEES(TX_LINKDOWN) &&
5775 posn <= SEES(TX_INCORRECT_LINK_STATE));
5779 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5780 * register. Does it represent a 'disallowed packet' error?
5782 static inline int disallowed_pkt_err(int posn)
5784 return (posn >= SEES(TX_SDMA0_DISALLOWED_PACKET) &&
5785 posn <= SEES(TX_SDMA15_DISALLOWED_PACKET));
5789 * Input value is a bit position of one of the SDMA engine disallowed
5790 * packet errors. Return which engine. Use of this must be guarded by
5791 * disallowed_pkt_err().
5793 static inline int disallowed_pkt_engine(int posn)
5795 return posn - SEES(TX_SDMA0_DISALLOWED_PACKET);
5799 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5802 static int engine_to_vl(struct hfi1_devdata *dd, int engine)
5804 struct sdma_vl_map *m;
5808 if (engine < 0 || engine >= TXE_NUM_SDMA_ENGINES)
5812 m = rcu_dereference(dd->sdma_map);
5813 vl = m->engine_to_vl[engine];
5820 * Translate the send context (sofware index) into a VL. Return -1 if the
5821 * translation cannot be done.
5823 static int sc_to_vl(struct hfi1_devdata *dd, int sw_index)
5825 struct send_context_info *sci;
5826 struct send_context *sc;
5829 sci = &dd->send_contexts[sw_index];
5831 /* there is no information for user (PSM) and ack contexts */
5832 if ((sci->type != SC_KERNEL) && (sci->type != SC_VL15))
5838 if (dd->vld[15].sc == sc)
5840 for (i = 0; i < num_vls; i++)
5841 if (dd->vld[i].sc == sc)
5847 static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5849 u64 reg_copy = reg, handled = 0;
5853 if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
5854 start_freeze_handling(dd->pport, 0);
5855 else if (is_ax(dd) &&
5856 (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) &&
5857 (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
5858 start_freeze_handling(dd->pport, 0);
5861 int posn = fls64(reg_copy);
5862 /* fls64() returns a 1-based offset, we want it zero based */
5863 int shift = posn - 1;
5864 u64 mask = 1ULL << shift;
5866 if (port_inactive_err(shift)) {
5867 count_port_inactive(dd);
5869 } else if (disallowed_pkt_err(shift)) {
5870 int vl = engine_to_vl(dd, disallowed_pkt_engine(shift));
5872 handle_send_egress_err_info(dd, vl);
5881 dd_dev_info(dd, "Egress Error: %s\n",
5882 egress_err_status_string(buf, sizeof(buf), reg));
5884 for (i = 0; i < NUM_SEND_EGRESS_ERR_STATUS_COUNTERS; i++) {
5885 if (reg & (1ull << i))
5886 incr_cntr64(&dd->send_egress_err_status_cnt[i]);
5890 static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
5895 dd_dev_info(dd, "Send Error: %s\n",
5896 send_err_status_string(buf, sizeof(buf), reg));
5898 for (i = 0; i < NUM_SEND_ERR_STATUS_COUNTERS; i++) {
5899 if (reg & (1ull << i))
5900 incr_cntr64(&dd->send_err_status_cnt[i]);
5905 * The maximum number of times the error clear down will loop before
5906 * blocking a repeating error. This value is arbitrary.
5908 #define MAX_CLEAR_COUNT 20
5911 * Clear and handle an error register. All error interrupts are funneled
5912 * through here to have a central location to correctly handle single-
5913 * or multi-shot errors.
5915 * For non per-context registers, call this routine with a context value
5916 * of 0 so the per-context offset is zero.
5918 * If the handler loops too many times, assume that something is wrong
5919 * and can't be fixed, so mask the error bits.
5921 static void interrupt_clear_down(struct hfi1_devdata *dd,
5923 const struct err_reg_info *eri)
5928 /* read in a loop until no more errors are seen */
5931 reg = read_kctxt_csr(dd, context, eri->status);
5934 write_kctxt_csr(dd, context, eri->clear, reg);
5935 if (likely(eri->handler))
5936 eri->handler(dd, context, reg);
5938 if (count > MAX_CLEAR_COUNT) {
5941 dd_dev_err(dd, "Repeating %s bits 0x%llx - masking\n",
5944 * Read-modify-write so any other masked bits
5947 mask = read_kctxt_csr(dd, context, eri->mask);
5949 write_kctxt_csr(dd, context, eri->mask, mask);
5956 * CCE block "misc" interrupt. Source is < 16.
5958 static void is_misc_err_int(struct hfi1_devdata *dd, unsigned int source)
5960 const struct err_reg_info *eri = &misc_errs[source];
5963 interrupt_clear_down(dd, 0, eri);
5965 dd_dev_err(dd, "Unexpected misc interrupt (%u) - reserved\n",
5970 static char *send_context_err_status_string(char *buf, int buf_len, u64 flags)
5972 return flag_string(buf, buf_len, flags,
5973 sc_err_status_flags,
5974 ARRAY_SIZE(sc_err_status_flags));
5978 * Send context error interrupt. Source (hw_context) is < 160.
5980 * All send context errors cause the send context to halt. The normal
5981 * clear-down mechanism cannot be used because we cannot clear the
5982 * error bits until several other long-running items are done first.
5983 * This is OK because with the context halted, nothing else is going
5984 * to happen on it anyway.
5986 static void is_sendctxt_err_int(struct hfi1_devdata *dd,
5987 unsigned int hw_context)
5989 struct send_context_info *sci;
5990 struct send_context *sc;
5995 unsigned long irq_flags;
5997 sw_index = dd->hw_to_sw[hw_context];
5998 if (sw_index >= dd->num_send_contexts) {
6000 "out of range sw index %u for send context %u\n",
6001 sw_index, hw_context);
6004 sci = &dd->send_contexts[sw_index];
6005 spin_lock_irqsave(&dd->sc_lock, irq_flags);
6008 dd_dev_err(dd, "%s: context %u(%u): no sc?\n", __func__,
6009 sw_index, hw_context);
6010 spin_unlock_irqrestore(&dd->sc_lock, irq_flags);
6014 /* tell the software that a halt has begun */
6015 sc_stop(sc, SCF_HALTED);
6017 status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
6019 dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
6020 send_context_err_status_string(flags, sizeof(flags),
6023 if (status & SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK)
6024 handle_send_egress_err_info(dd, sc_to_vl(dd, sw_index));
6027 * Automatically restart halted kernel contexts out of interrupt
6028 * context. User contexts must ask the driver to restart the context.
6030 if (sc->type != SC_USER)
6031 queue_work(dd->pport->hfi1_wq, &sc->halt_work);
6032 spin_unlock_irqrestore(&dd->sc_lock, irq_flags);
6035 * Update the counters for the corresponding status bits.
6036 * Note that these particular counters are aggregated over all
6039 for (i = 0; i < NUM_SEND_CTXT_ERR_STATUS_COUNTERS; i++) {
6040 if (status & (1ull << i))
6041 incr_cntr64(&dd->sw_ctxt_err_status_cnt[i]);
6045 static void handle_sdma_eng_err(struct hfi1_devdata *dd,
6046 unsigned int source, u64 status)
6048 struct sdma_engine *sde;
6051 sde = &dd->per_sdma[source];
6052 #ifdef CONFIG_SDMA_VERBOSITY
6053 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
6054 slashstrip(__FILE__), __LINE__, __func__);
6055 dd_dev_err(sde->dd, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
6056 sde->this_idx, source, (unsigned long long)status);
6059 sdma_engine_error(sde, status);
6062 * Update the counters for the corresponding status bits.
6063 * Note that these particular counters are aggregated over
6064 * all 16 DMA engines.
6066 for (i = 0; i < NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS; i++) {
6067 if (status & (1ull << i))
6068 incr_cntr64(&dd->sw_send_dma_eng_err_status_cnt[i]);
6073 * CCE block SDMA error interrupt. Source is < 16.
6075 static void is_sdma_eng_err_int(struct hfi1_devdata *dd, unsigned int source)
6077 #ifdef CONFIG_SDMA_VERBOSITY
6078 struct sdma_engine *sde = &dd->per_sdma[source];
6080 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
6081 slashstrip(__FILE__), __LINE__, __func__);
6082 dd_dev_err(dd, "CONFIG SDMA(%u) source: %u\n", sde->this_idx,
6084 sdma_dumpstate(sde);
6086 interrupt_clear_down(dd, source, &sdma_eng_err);
6090 * CCE block "various" interrupt. Source is < 8.
6092 static void is_various_int(struct hfi1_devdata *dd, unsigned int source)
6094 const struct err_reg_info *eri = &various_err[source];
6097 * TCritInt cannot go through interrupt_clear_down()
6098 * because it is not a second tier interrupt. The handler
6099 * should be called directly.
6101 if (source == TCRIT_INT_SOURCE)
6102 handle_temp_err(dd);
6103 else if (eri->handler)
6104 interrupt_clear_down(dd, 0, eri);
6107 "%s: Unimplemented/reserved interrupt %d\n",
6111 static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg)
6113 /* src_ctx is always zero */
6114 struct hfi1_pportdata *ppd = dd->pport;
6115 unsigned long flags;
6116 u64 qsfp_int_mgmt = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
6118 if (reg & QSFP_HFI0_MODPRST_N) {
6119 if (!qsfp_mod_present(ppd)) {
6120 dd_dev_info(dd, "%s: QSFP module removed\n",
6123 ppd->driver_link_ready = 0;
6125 * Cable removed, reset all our information about the
6126 * cache and cable capabilities
6129 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6131 * We don't set cache_refresh_required here as we expect
6132 * an interrupt when a cable is inserted
6134 ppd->qsfp_info.cache_valid = 0;
6135 ppd->qsfp_info.reset_needed = 0;
6136 ppd->qsfp_info.limiting_active = 0;
6137 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
6139 /* Invert the ModPresent pin now to detect plug-in */
6140 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6141 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6143 if ((ppd->offline_disabled_reason >
6145 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED)) ||
6146 (ppd->offline_disabled_reason ==
6147 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE)))
6148 ppd->offline_disabled_reason =
6150 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
6152 if (ppd->host_link_state == HLS_DN_POLL) {
6154 * The link is still in POLL. This means
6155 * that the normal link down processing
6156 * will not happen. We have to do it here
6157 * before turning the DC off.
6159 queue_work(ppd->link_wq, &ppd->link_down_work);
6162 dd_dev_info(dd, "%s: QSFP module inserted\n",
6165 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6166 ppd->qsfp_info.cache_valid = 0;
6167 ppd->qsfp_info.cache_refresh_required = 1;
6168 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
6172 * Stop inversion of ModPresent pin to detect
6173 * removal of the cable
6175 qsfp_int_mgmt &= ~(u64)QSFP_HFI0_MODPRST_N;
6176 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT :
6177 ASIC_QSFP1_INVERT, qsfp_int_mgmt);
6179 ppd->offline_disabled_reason =
6180 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
6184 if (reg & QSFP_HFI0_INT_N) {
6185 dd_dev_info(dd, "%s: Interrupt received from QSFP module\n",
6187 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
6188 ppd->qsfp_info.check_interrupt_flags = 1;
6189 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock, flags);
6192 /* Schedule the QSFP work only if there is a cable attached. */
6193 if (qsfp_mod_present(ppd))
6194 queue_work(ppd->link_wq, &ppd->qsfp_info.qsfp_work);
6197 static int request_host_lcb_access(struct hfi1_devdata *dd)
6201 ret = do_8051_command(dd, HCMD_MISC,
6202 (u64)HCMD_MISC_REQUEST_LCB_ACCESS <<
6203 LOAD_DATA_FIELD_ID_SHIFT, NULL);
6204 if (ret != HCMD_SUCCESS) {
6205 dd_dev_err(dd, "%s: command failed with error %d\n",
6208 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6211 static int request_8051_lcb_access(struct hfi1_devdata *dd)
6215 ret = do_8051_command(dd, HCMD_MISC,
6216 (u64)HCMD_MISC_GRANT_LCB_ACCESS <<
6217 LOAD_DATA_FIELD_ID_SHIFT, NULL);
6218 if (ret != HCMD_SUCCESS) {
6219 dd_dev_err(dd, "%s: command failed with error %d\n",
6222 return ret == HCMD_SUCCESS ? 0 : -EBUSY;
6226 * Set the LCB selector - allow host access. The DCC selector always
6227 * points to the host.
6229 static inline void set_host_lcb_access(struct hfi1_devdata *dd)
6231 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6232 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK |
6233 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK);
6237 * Clear the LCB selector - allow 8051 access. The DCC selector always
6238 * points to the host.
6240 static inline void set_8051_lcb_access(struct hfi1_devdata *dd)
6242 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL,
6243 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK);
6247 * Acquire LCB access from the 8051. If the host already has access,
6248 * just increment a counter. Otherwise, inform the 8051 that the
6249 * host is taking access.
6253 * -EBUSY if the 8051 has control and cannot be disturbed
6254 * -errno if unable to acquire access from the 8051
6256 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6258 struct hfi1_pportdata *ppd = dd->pport;
6262 * Use the host link state lock so the operation of this routine
6263 * { link state check, selector change, count increment } can occur
6264 * as a unit against a link state change. Otherwise there is a
6265 * race between the state change and the count increment.
6268 mutex_lock(&ppd->hls_lock);
6270 while (!mutex_trylock(&ppd->hls_lock))
6274 /* this access is valid only when the link is up */
6275 if (ppd->host_link_state & HLS_DOWN) {
6276 dd_dev_info(dd, "%s: link state %s not up\n",
6277 __func__, link_state_name(ppd->host_link_state));
6282 if (dd->lcb_access_count == 0) {
6283 ret = request_host_lcb_access(dd);
6286 "%s: unable to acquire LCB access, err %d\n",
6290 set_host_lcb_access(dd);
6292 dd->lcb_access_count++;
6294 mutex_unlock(&ppd->hls_lock);
6299 * Release LCB access by decrementing the use count. If the count is moving
6300 * from 1 to 0, inform 8051 that it has control back.
6304 * -errno if unable to release access to the 8051
6306 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok)
6311 * Use the host link state lock because the acquire needed it.
6312 * Here, we only need to keep { selector change, count decrement }
6316 mutex_lock(&dd->pport->hls_lock);
6318 while (!mutex_trylock(&dd->pport->hls_lock))
6322 if (dd->lcb_access_count == 0) {
6323 dd_dev_err(dd, "%s: LCB access count is zero. Skipping.\n",
6328 if (dd->lcb_access_count == 1) {
6329 set_8051_lcb_access(dd);
6330 ret = request_8051_lcb_access(dd);
6333 "%s: unable to release LCB access, err %d\n",
6335 /* restore host access if the grant didn't work */
6336 set_host_lcb_access(dd);
6340 dd->lcb_access_count--;
6342 mutex_unlock(&dd->pport->hls_lock);
6347 * Initialize LCB access variables and state. Called during driver load,
6348 * after most of the initialization is finished.
6350 * The DC default is LCB access on for the host. The driver defaults to
6351 * leaving access to the 8051. Assign access now - this constrains the call
6352 * to this routine to be after all LCB set-up is done. In particular, after
6353 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6355 static void init_lcb_access(struct hfi1_devdata *dd)
6357 dd->lcb_access_count = 0;
6361 * Write a response back to a 8051 request.
6363 static void hreq_response(struct hfi1_devdata *dd, u8 return_code, u16 rsp_data)
6365 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0,
6366 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK |
6368 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT |
6369 (u64)rsp_data << DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
6373 * Handle host requests from the 8051.
6375 static void handle_8051_request(struct hfi1_pportdata *ppd)
6377 struct hfi1_devdata *dd = ppd->dd;
6382 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
6383 if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0)
6384 return; /* no request */
6386 /* zero out COMPLETED so the response is seen */
6387 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0);
6389 /* extract request details */
6390 type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT)
6391 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK;
6392 data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT)
6393 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK;
6396 case HREQ_LOAD_CONFIG:
6397 case HREQ_SAVE_CONFIG:
6398 case HREQ_READ_CONFIG:
6399 case HREQ_SET_TX_EQ_ABS:
6400 case HREQ_SET_TX_EQ_REL:
6402 dd_dev_info(dd, "8051 request: request 0x%x not supported\n",
6404 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6406 case HREQ_LCB_RESET:
6407 /* Put the LCB, RX FPE and TX FPE into reset */
6408 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET);
6409 /* Make sure the write completed */
6410 (void)read_csr(dd, DCC_CFG_RESET);
6411 /* Hold the reset long enough to take effect */
6413 /* Take the LCB, RX FPE and TX FPE out of reset */
6414 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
6415 hreq_response(dd, HREQ_SUCCESS, 0);
6418 case HREQ_CONFIG_DONE:
6419 hreq_response(dd, HREQ_SUCCESS, 0);
6422 case HREQ_INTERFACE_TEST:
6423 hreq_response(dd, HREQ_SUCCESS, data);
6426 dd_dev_err(dd, "8051 request: unknown request 0x%x\n", type);
6427 hreq_response(dd, HREQ_NOT_SUPPORTED, 0);
6433 * Set up allocation unit vaulue.
6435 void set_up_vau(struct hfi1_devdata *dd, u8 vau)
6437 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6439 /* do not modify other values in the register */
6440 reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK;
6441 reg |= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT;
6442 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6446 * Set up initial VL15 credits of the remote. Assumes the rest of
6447 * the CM credit registers are zero from a previous global or credit reset.
6448 * Shared limit for VL15 will always be 0.
6450 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf)
6452 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
6454 /* set initial values for total and shared credit limit */
6455 reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK |
6456 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK);
6459 * Set total limit to be equal to VL15 credits.
6460 * Leave shared limit at 0.
6462 reg |= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
6463 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
6465 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf
6466 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT);
6470 * Zero all credit details from the previous connection and
6471 * reset the CM manager's internal counters.
6473 void reset_link_credits(struct hfi1_devdata *dd)
6477 /* remove all previous VL credit limits */
6478 for (i = 0; i < TXE_NUM_DATA_VL; i++)
6479 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
6480 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
6481 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0);
6482 /* reset the CM block */
6483 pio_send_control(dd, PSC_CM_RESET);
6484 /* reset cached value */
6485 dd->vl15buf_cached = 0;
6488 /* convert a vCU to a CU */
6489 static u32 vcu_to_cu(u8 vcu)
6494 /* convert a CU to a vCU */
6495 static u8 cu_to_vcu(u32 cu)
6500 /* convert a vAU to an AU */
6501 static u32 vau_to_au(u8 vau)
6503 return 8 * (1 << vau);
6506 static void set_linkup_defaults(struct hfi1_pportdata *ppd)
6508 ppd->sm_trap_qp = 0x0;
6513 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6515 static void lcb_shutdown(struct hfi1_devdata *dd, int abort)
6519 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6520 write_csr(dd, DC_LCB_CFG_RUN, 0);
6521 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6522 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET,
6523 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT);
6524 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6525 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
6526 reg = read_csr(dd, DCC_CFG_RESET);
6527 write_csr(dd, DCC_CFG_RESET, reg |
6528 DCC_CFG_RESET_RESET_LCB | DCC_CFG_RESET_RESET_RX_FPE);
6529 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
6531 udelay(1); /* must hold for the longer of 16cclks or 20ns */
6532 write_csr(dd, DCC_CFG_RESET, reg);
6533 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6538 * This routine should be called after the link has been transitioned to
6539 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6542 * The expectation is that the caller of this routine would have taken
6543 * care of properly transitioning the link into the correct state.
6544 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6545 * before calling this function.
6547 static void _dc_shutdown(struct hfi1_devdata *dd)
6549 lockdep_assert_held(&dd->dc8051_lock);
6551 if (dd->dc_shutdown)
6554 dd->dc_shutdown = 1;
6555 /* Shutdown the LCB */
6556 lcb_shutdown(dd, 1);
6558 * Going to OFFLINE would have causes the 8051 to put the
6559 * SerDes into reset already. Just need to shut down the 8051,
6562 write_csr(dd, DC_DC8051_CFG_RST, 0x1);
6565 static void dc_shutdown(struct hfi1_devdata *dd)
6567 mutex_lock(&dd->dc8051_lock);
6569 mutex_unlock(&dd->dc8051_lock);
6573 * Calling this after the DC has been brought out of reset should not
6575 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6576 * before calling this function.
6578 static void _dc_start(struct hfi1_devdata *dd)
6580 lockdep_assert_held(&dd->dc8051_lock);
6582 if (!dd->dc_shutdown)
6585 /* Take the 8051 out of reset */
6586 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
6587 /* Wait until 8051 is ready */
6588 if (wait_fm_ready(dd, TIMEOUT_8051_START))
6589 dd_dev_err(dd, "%s: timeout starting 8051 firmware\n",
6592 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6593 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET);
6594 /* lcb_shutdown() with abort=1 does not restore these */
6595 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en);
6596 dd->dc_shutdown = 0;
6599 static void dc_start(struct hfi1_devdata *dd)
6601 mutex_lock(&dd->dc8051_lock);
6603 mutex_unlock(&dd->dc8051_lock);
6607 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6609 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
6611 u64 rx_radr, tx_radr;
6614 if (dd->icode != ICODE_FPGA_EMULATION)
6618 * These LCB defaults on emulator _s are good, nothing to do here:
6619 * LCB_CFG_TX_FIFOS_RADR
6620 * LCB_CFG_RX_FIFOS_RADR
6622 * LCB_CFG_IGNORE_LOST_RCLK
6624 if (is_emulator_s(dd))
6626 /* else this is _p */
6628 version = emulator_rev(dd);
6630 version = 0x2d; /* all B0 use 0x2d or higher settings */
6632 if (version <= 0x12) {
6633 /* release 0x12 and below */
6636 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6637 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6638 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6641 0xaull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6642 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6643 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6645 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6646 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6648 tx_radr = 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6649 } else if (version <= 0x18) {
6650 /* release 0x13 up to 0x18 */
6651 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6653 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6654 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6655 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6656 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6657 } else if (version == 0x19) {
6659 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6661 0xAull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6662 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6663 | 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6664 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6665 } else if (version == 0x1a) {
6667 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6669 0x9ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6670 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6671 | 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6672 tx_radr = 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6673 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull);
6675 /* release 0x1b and higher */
6676 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6678 0x8ull << DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6679 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6680 | 0x7ull << DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT;
6681 tx_radr = 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT;
6684 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr);
6685 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6686 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
6687 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
6688 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr);
6692 * Handle a SMA idle message
6694 * This is a work-queue function outside of the interrupt.
6696 void handle_sma_message(struct work_struct *work)
6698 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6700 struct hfi1_devdata *dd = ppd->dd;
6705 * msg is bytes 1-4 of the 40-bit idle message - the command code
6708 ret = read_idle_sma(dd, &msg);
6711 dd_dev_info(dd, "%s: SMA message 0x%llx\n", __func__, msg);
6713 * React to the SMA message. Byte[1] (0 for us) is the command.
6715 switch (msg & 0xff) {
6718 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6721 * Only expected in INIT or ARMED, discard otherwise.
6723 if (ppd->host_link_state & (HLS_UP_INIT | HLS_UP_ARMED))
6724 ppd->neighbor_normal = 1;
6726 case SMA_IDLE_ACTIVE:
6728 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6731 * Can activate the node. Discard otherwise.
6733 if (ppd->host_link_state == HLS_UP_ARMED &&
6734 ppd->is_active_optimize_enabled) {
6735 ppd->neighbor_normal = 1;
6736 ret = set_link_state(ppd, HLS_UP_ACTIVE);
6740 "%s: received Active SMA idle message, couldn't set link to Active\n",
6746 "%s: received unexpected SMA idle message 0x%llx\n",
6752 static void adjust_rcvctrl(struct hfi1_devdata *dd, u64 add, u64 clear)
6755 unsigned long flags;
6757 spin_lock_irqsave(&dd->rcvctrl_lock, flags);
6758 rcvctrl = read_csr(dd, RCV_CTRL);
6761 write_csr(dd, RCV_CTRL, rcvctrl);
6762 spin_unlock_irqrestore(&dd->rcvctrl_lock, flags);
6765 static inline void add_rcvctrl(struct hfi1_devdata *dd, u64 add)
6767 adjust_rcvctrl(dd, add, 0);
6770 static inline void clear_rcvctrl(struct hfi1_devdata *dd, u64 clear)
6772 adjust_rcvctrl(dd, 0, clear);
6776 * Called from all interrupt handlers to start handling an SPC freeze.
6778 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags)
6780 struct hfi1_devdata *dd = ppd->dd;
6781 struct send_context *sc;
6785 if (flags & FREEZE_SELF)
6786 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6788 /* enter frozen mode */
6789 dd->flags |= HFI1_FROZEN;
6791 /* notify all SDMA engines that they are going into a freeze */
6792 sdma_freeze_notify(dd, !!(flags & FREEZE_LINK_DOWN));
6794 sc_flags = SCF_FROZEN | SCF_HALTED | (flags & FREEZE_LINK_DOWN ?
6796 /* do halt pre-handling on all enabled send contexts */
6797 for (i = 0; i < dd->num_send_contexts; i++) {
6798 sc = dd->send_contexts[i].sc;
6799 if (sc && (sc->flags & SCF_ENABLED))
6800 sc_stop(sc, sc_flags);
6803 /* Send context are frozen. Notify user space */
6804 hfi1_set_uevent_bits(ppd, _HFI1_EVENT_FROZEN_BIT);
6806 if (flags & FREEZE_ABORT) {
6808 "Aborted freeze recovery. Please REBOOT system\n");
6811 /* queue non-interrupt handler */
6812 queue_work(ppd->hfi1_wq, &ppd->freeze_work);
6816 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6817 * depending on the "freeze" parameter.
6819 * No need to return an error if it times out, our only option
6820 * is to proceed anyway.
6822 static void wait_for_freeze_status(struct hfi1_devdata *dd, int freeze)
6824 unsigned long timeout;
6827 timeout = jiffies + msecs_to_jiffies(FREEZE_STATUS_TIMEOUT);
6829 reg = read_csr(dd, CCE_STATUS);
6831 /* waiting until all indicators are set */
6832 if ((reg & ALL_FROZE) == ALL_FROZE)
6833 return; /* all done */
6835 /* waiting until all indicators are clear */
6836 if ((reg & ALL_FROZE) == 0)
6837 return; /* all done */
6840 if (time_after(jiffies, timeout)) {
6842 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6843 freeze ? "" : "un", reg & ALL_FROZE,
6844 freeze ? ALL_FROZE : 0ull);
6847 usleep_range(80, 120);
6852 * Do all freeze handling for the RXE block.
6854 static void rxe_freeze(struct hfi1_devdata *dd)
6857 struct hfi1_ctxtdata *rcd;
6860 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6862 /* disable all receive contexts */
6863 for (i = 0; i < dd->num_rcv_contexts; i++) {
6864 rcd = hfi1_rcd_get_by_index(dd, i);
6865 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS, rcd);
6871 * Unfreeze handling for the RXE block - kernel contexts only.
6872 * This will also enable the port. User contexts will do unfreeze
6873 * handling on a per-context basis as they call into the driver.
6876 static void rxe_kernel_unfreeze(struct hfi1_devdata *dd)
6880 struct hfi1_ctxtdata *rcd;
6882 /* enable all kernel contexts */
6883 for (i = 0; i < dd->num_rcv_contexts; i++) {
6884 rcd = hfi1_rcd_get_by_index(dd, i);
6886 /* Ensure all non-user contexts(including vnic) are enabled */
6888 (i >= dd->first_dyn_alloc_ctxt && !rcd->is_vnic)) {
6892 rcvmask = HFI1_RCVCTRL_CTXT_ENB;
6893 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6894 rcvmask |= hfi1_rcvhdrtail_kvaddr(rcd) ?
6895 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
6896 hfi1_rcvctrl(dd, rcvmask, rcd);
6901 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
6905 * Non-interrupt SPC freeze handling.
6907 * This is a work-queue function outside of the triggering interrupt.
6909 void handle_freeze(struct work_struct *work)
6911 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
6913 struct hfi1_devdata *dd = ppd->dd;
6915 /* wait for freeze indicators on all affected blocks */
6916 wait_for_freeze_status(dd, 1);
6918 /* SPC is now frozen */
6920 /* do send PIO freeze steps */
6923 /* do send DMA freeze steps */
6926 /* do send egress freeze steps - nothing to do */
6928 /* do receive freeze steps */
6932 * Unfreeze the hardware - clear the freeze, wait for each
6933 * block's frozen bit to clear, then clear the frozen flag.
6935 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6936 wait_for_freeze_status(dd, 0);
6939 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
6940 wait_for_freeze_status(dd, 1);
6941 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
6942 wait_for_freeze_status(dd, 0);
6945 /* do send PIO unfreeze steps for kernel contexts */
6946 pio_kernel_unfreeze(dd);
6948 /* do send DMA unfreeze steps */
6951 /* do send egress unfreeze steps - nothing to do */
6953 /* do receive unfreeze steps for kernel contexts */
6954 rxe_kernel_unfreeze(dd);
6957 * The unfreeze procedure touches global device registers when
6958 * it disables and re-enables RXE. Mark the device unfrozen
6959 * after all that is done so other parts of the driver waiting
6960 * for the device to unfreeze don't do things out of order.
6962 * The above implies that the meaning of HFI1_FROZEN flag is
6963 * "Device has gone into freeze mode and freeze mode handling
6964 * is still in progress."
6966 * The flag will be removed when freeze mode processing has
6969 dd->flags &= ~HFI1_FROZEN;
6970 wake_up(&dd->event_queue);
6972 /* no longer frozen */
6976 * update_xmit_counters - update PortXmitWait/PortVlXmitWait
6978 * @ppd: info of physical Hfi port
6979 * @link_width: new link width after link up or downgrade
6981 * Update the PortXmitWait and PortVlXmitWait counters after
6982 * a link up or downgrade event to reflect a link width change.
6984 static void update_xmit_counters(struct hfi1_pportdata *ppd, u16 link_width)
6990 tx_width = tx_link_width(link_width);
6991 link_speed = get_link_speed(ppd->link_speed_active);
6994 * There are C_VL_COUNT number of PortVLXmitWait counters.
6995 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter.
6997 for (i = 0; i < C_VL_COUNT + 1; i++)
6998 get_xmit_wait_counters(ppd, tx_width, link_speed, i);
7002 * Handle a link up interrupt from the 8051.
7004 * This is a work-queue function outside of the interrupt.
7006 void handle_link_up(struct work_struct *work)
7008 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7010 struct hfi1_devdata *dd = ppd->dd;
7012 set_link_state(ppd, HLS_UP_INIT);
7014 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
7017 * OPA specifies that certain counters are cleared on a transition
7018 * to link up, so do that.
7020 clear_linkup_counters(dd);
7022 * And (re)set link up default values.
7024 set_linkup_defaults(ppd);
7027 * Set VL15 credits. Use cached value from verify cap interrupt.
7028 * In case of quick linkup or simulator, vl15 value will be set by
7029 * handle_linkup_change. VerifyCap interrupt handler will not be
7030 * called in those scenarios.
7032 if (!(quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR))
7033 set_up_vl15(dd, dd->vl15buf_cached);
7035 /* enforce link speed enabled */
7036 if ((ppd->link_speed_active & ppd->link_speed_enabled) == 0) {
7037 /* oops - current speed is not enabled, bounce */
7039 "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
7040 ppd->link_speed_active, ppd->link_speed_enabled);
7041 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_SPEED_POLICY, 0,
7042 OPA_LINKDOWN_REASON_SPEED_POLICY);
7043 set_link_state(ppd, HLS_DN_OFFLINE);
7049 * Several pieces of LNI information were cached for SMA in ppd.
7050 * Reset these on link down
7052 static void reset_neighbor_info(struct hfi1_pportdata *ppd)
7054 ppd->neighbor_guid = 0;
7055 ppd->neighbor_port_number = 0;
7056 ppd->neighbor_type = 0;
7057 ppd->neighbor_fm_security = 0;
7060 static const char * const link_down_reason_strs[] = {
7061 [OPA_LINKDOWN_REASON_NONE] = "None",
7062 [OPA_LINKDOWN_REASON_RCV_ERROR_0] = "Receive error 0",
7063 [OPA_LINKDOWN_REASON_BAD_PKT_LEN] = "Bad packet length",
7064 [OPA_LINKDOWN_REASON_PKT_TOO_LONG] = "Packet too long",
7065 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT] = "Packet too short",
7066 [OPA_LINKDOWN_REASON_BAD_SLID] = "Bad SLID",
7067 [OPA_LINKDOWN_REASON_BAD_DLID] = "Bad DLID",
7068 [OPA_LINKDOWN_REASON_BAD_L2] = "Bad L2",
7069 [OPA_LINKDOWN_REASON_BAD_SC] = "Bad SC",
7070 [OPA_LINKDOWN_REASON_RCV_ERROR_8] = "Receive error 8",
7071 [OPA_LINKDOWN_REASON_BAD_MID_TAIL] = "Bad mid tail",
7072 [OPA_LINKDOWN_REASON_RCV_ERROR_10] = "Receive error 10",
7073 [OPA_LINKDOWN_REASON_PREEMPT_ERROR] = "Preempt error",
7074 [OPA_LINKDOWN_REASON_PREEMPT_VL15] = "Preempt vl15",
7075 [OPA_LINKDOWN_REASON_BAD_VL_MARKER] = "Bad VL marker",
7076 [OPA_LINKDOWN_REASON_RCV_ERROR_14] = "Receive error 14",
7077 [OPA_LINKDOWN_REASON_RCV_ERROR_15] = "Receive error 15",
7078 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST] = "Bad head distance",
7079 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST] = "Bad tail distance",
7080 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST] = "Bad control distance",
7081 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK] = "Bad credit ack",
7082 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER] = "Unsupported VL marker",
7083 [OPA_LINKDOWN_REASON_BAD_PREEMPT] = "Bad preempt",
7084 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT] = "Bad control flit",
7085 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT] = "Exceed multicast limit",
7086 [OPA_LINKDOWN_REASON_RCV_ERROR_24] = "Receive error 24",
7087 [OPA_LINKDOWN_REASON_RCV_ERROR_25] = "Receive error 25",
7088 [OPA_LINKDOWN_REASON_RCV_ERROR_26] = "Receive error 26",
7089 [OPA_LINKDOWN_REASON_RCV_ERROR_27] = "Receive error 27",
7090 [OPA_LINKDOWN_REASON_RCV_ERROR_28] = "Receive error 28",
7091 [OPA_LINKDOWN_REASON_RCV_ERROR_29] = "Receive error 29",
7092 [OPA_LINKDOWN_REASON_RCV_ERROR_30] = "Receive error 30",
7093 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN] =
7094 "Excessive buffer overrun",
7095 [OPA_LINKDOWN_REASON_UNKNOWN] = "Unknown",
7096 [OPA_LINKDOWN_REASON_REBOOT] = "Reboot",
7097 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN] = "Neighbor unknown",
7098 [OPA_LINKDOWN_REASON_FM_BOUNCE] = "FM bounce",
7099 [OPA_LINKDOWN_REASON_SPEED_POLICY] = "Speed policy",
7100 [OPA_LINKDOWN_REASON_WIDTH_POLICY] = "Width policy",
7101 [OPA_LINKDOWN_REASON_DISCONNECTED] = "Disconnected",
7102 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED] =
7103 "Local media not installed",
7104 [OPA_LINKDOWN_REASON_NOT_INSTALLED] = "Not installed",
7105 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG] = "Chassis config",
7106 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED] =
7107 "End to end not installed",
7108 [OPA_LINKDOWN_REASON_POWER_POLICY] = "Power policy",
7109 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY] = "Link speed policy",
7110 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY] = "Link width policy",
7111 [OPA_LINKDOWN_REASON_SWITCH_MGMT] = "Switch management",
7112 [OPA_LINKDOWN_REASON_SMA_DISABLED] = "SMA disabled",
7113 [OPA_LINKDOWN_REASON_TRANSIENT] = "Transient"
7116 /* return the neighbor link down reason string */
7117 static const char *link_down_reason_str(u8 reason)
7119 const char *str = NULL;
7121 if (reason < ARRAY_SIZE(link_down_reason_strs))
7122 str = link_down_reason_strs[reason];
7130 * Handle a link down interrupt from the 8051.
7132 * This is a work-queue function outside of the interrupt.
7134 void handle_link_down(struct work_struct *work)
7136 u8 lcl_reason, neigh_reason = 0;
7137 u8 link_down_reason;
7138 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7141 static const char ldr_str[] = "Link down reason: ";
7143 if ((ppd->host_link_state &
7144 (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) &&
7145 ppd->port_type == PORT_TYPE_FIXED)
7146 ppd->offline_disabled_reason =
7147 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED);
7149 /* Go offline first, then deal with reading/writing through 8051 */
7150 was_up = !!(ppd->host_link_state & HLS_UP);
7151 set_link_state(ppd, HLS_DN_OFFLINE);
7152 xchg(&ppd->is_link_down_queued, 0);
7156 /* link down reason is only valid if the link was up */
7157 read_link_down_reason(ppd->dd, &link_down_reason);
7158 switch (link_down_reason) {
7159 case LDR_LINK_TRANSFER_ACTIVE_LOW:
7160 /* the link went down, no idle message reason */
7161 dd_dev_info(ppd->dd, "%sUnexpected link down\n",
7164 case LDR_RECEIVED_LINKDOWN_IDLE_MSG:
7166 * The neighbor reason is only valid if an idle message
7167 * was received for it.
7169 read_planned_down_reason_code(ppd->dd, &neigh_reason);
7170 dd_dev_info(ppd->dd,
7171 "%sNeighbor link down message %d, %s\n",
7172 ldr_str, neigh_reason,
7173 link_down_reason_str(neigh_reason));
7175 case LDR_RECEIVED_HOST_OFFLINE_REQ:
7176 dd_dev_info(ppd->dd,
7177 "%sHost requested link to go offline\n",
7181 dd_dev_info(ppd->dd, "%sUnknown reason 0x%x\n",
7182 ldr_str, link_down_reason);
7187 * If no reason, assume peer-initiated but missed
7188 * LinkGoingDown idle flits.
7190 if (neigh_reason == 0)
7191 lcl_reason = OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN;
7193 /* went down while polling or going up */
7194 lcl_reason = OPA_LINKDOWN_REASON_TRANSIENT;
7197 set_link_down_reason(ppd, lcl_reason, neigh_reason, 0);
7199 /* inform the SMA when the link transitions from up to down */
7200 if (was_up && ppd->local_link_down_reason.sma == 0 &&
7201 ppd->neigh_link_down_reason.sma == 0) {
7202 ppd->local_link_down_reason.sma =
7203 ppd->local_link_down_reason.latest;
7204 ppd->neigh_link_down_reason.sma =
7205 ppd->neigh_link_down_reason.latest;
7208 reset_neighbor_info(ppd);
7210 /* disable the port */
7211 clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
7214 * If there is no cable attached, turn the DC off. Otherwise,
7215 * start the link bring up.
7217 if (ppd->port_type == PORT_TYPE_QSFP && !qsfp_mod_present(ppd))
7218 dc_shutdown(ppd->dd);
7223 void handle_link_bounce(struct work_struct *work)
7225 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7229 * Only do something if the link is currently up.
7231 if (ppd->host_link_state & HLS_UP) {
7232 set_link_state(ppd, HLS_DN_OFFLINE);
7235 dd_dev_info(ppd->dd, "%s: link not up (%s), nothing to do\n",
7236 __func__, link_state_name(ppd->host_link_state));
7241 * Mask conversion: Capability exchange to Port LTP. The capability
7242 * exchange has an implicit 16b CRC that is mandatory.
7244 static int cap_to_port_ltp(int cap)
7246 int port_ltp = PORT_LTP_CRC_MODE_16; /* this mode is mandatory */
7248 if (cap & CAP_CRC_14B)
7249 port_ltp |= PORT_LTP_CRC_MODE_14;
7250 if (cap & CAP_CRC_48B)
7251 port_ltp |= PORT_LTP_CRC_MODE_48;
7252 if (cap & CAP_CRC_12B_16B_PER_LANE)
7253 port_ltp |= PORT_LTP_CRC_MODE_PER_LANE;
7259 * Convert an OPA Port LTP mask to capability mask
7261 int port_ltp_to_cap(int port_ltp)
7265 if (port_ltp & PORT_LTP_CRC_MODE_14)
7266 cap_mask |= CAP_CRC_14B;
7267 if (port_ltp & PORT_LTP_CRC_MODE_48)
7268 cap_mask |= CAP_CRC_48B;
7269 if (port_ltp & PORT_LTP_CRC_MODE_PER_LANE)
7270 cap_mask |= CAP_CRC_12B_16B_PER_LANE;
7276 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7278 static int lcb_to_port_ltp(int lcb_crc)
7282 if (lcb_crc == LCB_CRC_12B_16B_PER_LANE)
7283 port_ltp = PORT_LTP_CRC_MODE_PER_LANE;
7284 else if (lcb_crc == LCB_CRC_48B)
7285 port_ltp = PORT_LTP_CRC_MODE_48;
7286 else if (lcb_crc == LCB_CRC_14B)
7287 port_ltp = PORT_LTP_CRC_MODE_14;
7289 port_ltp = PORT_LTP_CRC_MODE_16;
7294 static void clear_full_mgmt_pkey(struct hfi1_pportdata *ppd)
7296 if (ppd->pkeys[2] != 0) {
7298 (void)hfi1_set_ib_cfg(ppd, HFI1_IB_CFG_PKEYS, 0);
7299 hfi1_event_pkey_change(ppd->dd, ppd->port);
7304 * Convert the given link width to the OPA link width bitmask.
7306 static u16 link_width_to_bits(struct hfi1_devdata *dd, u16 width)
7311 * Simulator and quick linkup do not set the width.
7312 * Just set it to 4x without complaint.
7314 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR || quick_linkup)
7315 return OPA_LINK_WIDTH_4X;
7316 return 0; /* no lanes up */
7317 case 1: return OPA_LINK_WIDTH_1X;
7318 case 2: return OPA_LINK_WIDTH_2X;
7319 case 3: return OPA_LINK_WIDTH_3X;
7320 case 4: return OPA_LINK_WIDTH_4X;
7322 dd_dev_info(dd, "%s: invalid width %d, using 4\n",
7324 return OPA_LINK_WIDTH_4X;
7329 * Do a population count on the bottom nibble.
7331 static const u8 bit_counts[16] = {
7332 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
7335 static inline u8 nibble_to_count(u8 nibble)
7337 return bit_counts[nibble & 0xf];
7341 * Read the active lane information from the 8051 registers and return
7344 * Active lane information is found in these 8051 registers:
7348 static void get_link_widths(struct hfi1_devdata *dd, u16 *tx_width,
7354 u8 tx_polarity_inversion;
7355 u8 rx_polarity_inversion;
7358 /* read the active lanes */
7359 read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
7360 &rx_polarity_inversion, &max_rate);
7361 read_local_lni(dd, &enable_lane_rx);
7363 /* convert to counts */
7364 tx = nibble_to_count(enable_lane_tx);
7365 rx = nibble_to_count(enable_lane_rx);
7368 * Set link_speed_active here, overriding what was set in
7369 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7370 * set the max_rate field in handle_verify_cap until v0.19.
7372 if ((dd->icode == ICODE_RTL_SILICON) &&
7373 (dd->dc8051_ver < dc8051_ver(0, 19, 0))) {
7374 /* max_rate: 0 = 12.5G, 1 = 25G */
7377 dd->pport[0].link_speed_active = OPA_LINK_SPEED_12_5G;
7380 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7384 "%s: unexpected max rate %d, using 25Gb\n",
7385 __func__, (int)max_rate);
7386 dd->pport[0].link_speed_active = OPA_LINK_SPEED_25G;
7392 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7393 enable_lane_tx, tx, enable_lane_rx, rx);
7394 *tx_width = link_width_to_bits(dd, tx);
7395 *rx_width = link_width_to_bits(dd, rx);
7399 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7400 * Valid after the end of VerifyCap and during LinkUp. Does not change
7401 * after link up. I.e. look elsewhere for downgrade information.
7404 * + bits [7:4] contain the number of active transmitters
7405 * + bits [3:0] contain the number of active receivers
7406 * These are numbers 1 through 4 and can be different values if the
7407 * link is asymmetric.
7409 * verify_cap_local_fm_link_width[0] retains its original value.
7411 static void get_linkup_widths(struct hfi1_devdata *dd, u16 *tx_width,
7415 u8 misc_bits, local_flags;
7416 u16 active_tx, active_rx;
7418 read_vc_local_link_mode(dd, &misc_bits, &local_flags, &widths);
7420 rx = (widths >> 8) & 0xf;
7422 *tx_width = link_width_to_bits(dd, tx);
7423 *rx_width = link_width_to_bits(dd, rx);
7425 /* print the active widths */
7426 get_link_widths(dd, &active_tx, &active_rx);
7430 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7431 * hardware information when the link first comes up.
7433 * The link width is not available until after VerifyCap.AllFramesReceived
7434 * (the trigger for handle_verify_cap), so this is outside that routine
7435 * and should be called when the 8051 signals linkup.
7437 void get_linkup_link_widths(struct hfi1_pportdata *ppd)
7439 u16 tx_width, rx_width;
7441 /* get end-of-LNI link widths */
7442 get_linkup_widths(ppd->dd, &tx_width, &rx_width);
7444 /* use tx_width as the link is supposed to be symmetric on link up */
7445 ppd->link_width_active = tx_width;
7446 /* link width downgrade active (LWD.A) starts out matching LW.A */
7447 ppd->link_width_downgrade_tx_active = ppd->link_width_active;
7448 ppd->link_width_downgrade_rx_active = ppd->link_width_active;
7449 /* per OPA spec, on link up LWD.E resets to LWD.S */
7450 ppd->link_width_downgrade_enabled = ppd->link_width_downgrade_supported;
7451 /* cache the active egress rate (units {10^6 bits/sec]) */
7452 ppd->current_egress_rate = active_egress_rate(ppd);
7456 * Handle a verify capabilities interrupt from the 8051.
7458 * This is a work-queue function outside of the interrupt.
7460 void handle_verify_cap(struct work_struct *work)
7462 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7464 struct hfi1_devdata *dd = ppd->dd;
7466 u8 power_management;
7476 u16 active_tx, active_rx;
7477 u8 partner_supported_crc;
7481 set_link_state(ppd, HLS_VERIFY_CAP);
7483 lcb_shutdown(dd, 0);
7484 adjust_lcb_for_fpga_serdes(dd);
7486 read_vc_remote_phy(dd, &power_management, &continuous);
7487 read_vc_remote_fabric(dd, &vau, &z, &vcu, &vl15buf,
7488 &partner_supported_crc);
7489 read_vc_remote_link_width(dd, &remote_tx_rate, &link_widths);
7490 read_remote_device_id(dd, &device_id, &device_rev);
7492 /* print the active widths */
7493 get_link_widths(dd, &active_tx, &active_rx);
7495 "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7496 (int)power_management, (int)continuous);
7498 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7499 (int)vau, (int)z, (int)vcu, (int)vl15buf,
7500 (int)partner_supported_crc);
7501 dd_dev_info(dd, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
7502 (u32)remote_tx_rate, (u32)link_widths);
7503 dd_dev_info(dd, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
7504 (u32)device_id, (u32)device_rev);
7506 * The peer vAU value just read is the peer receiver value. HFI does
7507 * not support a transmit vAU of 0 (AU == 8). We advertised that
7508 * with Z=1 in the fabric capabilities sent to the peer. The peer
7509 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7510 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7511 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7512 * subject to the Z value exception.
7516 set_up_vau(dd, vau);
7519 * Set VL15 credits to 0 in global credit register. Cache remote VL15
7520 * credits value and wait for link-up interrupt ot set it.
7523 dd->vl15buf_cached = vl15buf;
7525 /* set up the LCB CRC mode */
7526 crc_mask = ppd->port_crc_mode_enabled & partner_supported_crc;
7528 /* order is important: use the lowest bit in common */
7529 if (crc_mask & CAP_CRC_14B)
7530 crc_val = LCB_CRC_14B;
7531 else if (crc_mask & CAP_CRC_48B)
7532 crc_val = LCB_CRC_48B;
7533 else if (crc_mask & CAP_CRC_12B_16B_PER_LANE)
7534 crc_val = LCB_CRC_12B_16B_PER_LANE;
7536 crc_val = LCB_CRC_16B;
7538 dd_dev_info(dd, "Final LCB CRC mode: %d\n", (int)crc_val);
7539 write_csr(dd, DC_LCB_CFG_CRC_MODE,
7540 (u64)crc_val << DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT);
7542 /* set (14b only) or clear sideband credit */
7543 reg = read_csr(dd, SEND_CM_CTRL);
7544 if (crc_val == LCB_CRC_14B && crc_14b_sideband) {
7545 write_csr(dd, SEND_CM_CTRL,
7546 reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7548 write_csr(dd, SEND_CM_CTRL,
7549 reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK);
7552 ppd->link_speed_active = 0; /* invalid value */
7553 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) {
7554 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7555 switch (remote_tx_rate) {
7557 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7560 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7564 /* actual rate is highest bit of the ANDed rates */
7565 u8 rate = remote_tx_rate & ppd->local_tx_rate;
7568 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7570 ppd->link_speed_active = OPA_LINK_SPEED_12_5G;
7572 if (ppd->link_speed_active == 0) {
7573 dd_dev_err(dd, "%s: unexpected remote tx rate %d, using 25Gb\n",
7574 __func__, (int)remote_tx_rate);
7575 ppd->link_speed_active = OPA_LINK_SPEED_25G;
7579 * Cache the values of the supported, enabled, and active
7580 * LTP CRC modes to return in 'portinfo' queries. But the bit
7581 * flags that are returned in the portinfo query differ from
7582 * what's in the link_crc_mask, crc_sizes, and crc_val
7583 * variables. Convert these here.
7585 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
7586 /* supported crc modes */
7587 ppd->port_ltp_crc_mode |=
7588 cap_to_port_ltp(ppd->port_crc_mode_enabled) << 4;
7589 /* enabled crc modes */
7590 ppd->port_ltp_crc_mode |= lcb_to_port_ltp(crc_val);
7591 /* active crc mode */
7593 /* set up the remote credit return table */
7594 assign_remote_cm_au_table(dd, vcu);
7597 * The LCB is reset on entry to handle_verify_cap(), so this must
7598 * be applied on every link up.
7600 * Adjust LCB error kill enable to kill the link if
7601 * these RBUF errors are seen:
7602 * REPLAY_BUF_MBE_SMASK
7603 * FLIT_INPUT_BUF_MBE_SMASK
7605 if (is_ax(dd)) { /* fixed in B0 */
7606 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
7607 reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7608 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
7609 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg);
7612 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7613 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
7615 /* give 8051 access to the LCB CSRs */
7616 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
7617 set_8051_lcb_access(dd);
7619 /* tell the 8051 to go to LinkUp */
7620 set_link_state(ppd, HLS_GOING_UP);
7624 * apply_link_downgrade_policy - Apply the link width downgrade enabled
7625 * policy against the current active link widths.
7626 * @ppd: info of physical Hfi port
7627 * @refresh_widths: True indicates link downgrade event
7628 * @return: True indicates a successful link downgrade. False indicates
7629 * link downgrade event failed and the link will bounce back to
7630 * default link width.
7632 * Called when the enabled policy changes or the active link widths
7634 * Refresh_widths indicates that a link downgrade occurred. The
7635 * link_downgraded variable is set by refresh_widths and
7636 * determines the success/failure of the policy application.
7638 bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd,
7639 bool refresh_widths)
7645 bool link_downgraded = refresh_widths;
7647 /* use the hls lock to avoid a race with actual link up */
7650 mutex_lock(&ppd->hls_lock);
7651 /* only apply if the link is up */
7652 if (ppd->host_link_state & HLS_DOWN) {
7653 /* still going up..wait and retry */
7654 if (ppd->host_link_state & HLS_GOING_UP) {
7655 if (++tries < 1000) {
7656 mutex_unlock(&ppd->hls_lock);
7657 usleep_range(100, 120); /* arbitrary */
7661 "%s: giving up waiting for link state change\n",
7667 lwde = ppd->link_width_downgrade_enabled;
7669 if (refresh_widths) {
7670 get_link_widths(ppd->dd, &tx, &rx);
7671 ppd->link_width_downgrade_tx_active = tx;
7672 ppd->link_width_downgrade_rx_active = rx;
7675 if (ppd->link_width_downgrade_tx_active == 0 ||
7676 ppd->link_width_downgrade_rx_active == 0) {
7677 /* the 8051 reported a dead link as a downgrade */
7678 dd_dev_err(ppd->dd, "Link downgrade is really a link down, ignoring\n");
7679 link_downgraded = false;
7680 } else if (lwde == 0) {
7681 /* downgrade is disabled */
7683 /* bounce if not at starting active width */
7684 if ((ppd->link_width_active !=
7685 ppd->link_width_downgrade_tx_active) ||
7686 (ppd->link_width_active !=
7687 ppd->link_width_downgrade_rx_active)) {
7689 "Link downgrade is disabled and link has downgraded, downing link\n");
7691 " original 0x%x, tx active 0x%x, rx active 0x%x\n",
7692 ppd->link_width_active,
7693 ppd->link_width_downgrade_tx_active,
7694 ppd->link_width_downgrade_rx_active);
7696 link_downgraded = false;
7698 } else if ((lwde & ppd->link_width_downgrade_tx_active) == 0 ||
7699 (lwde & ppd->link_width_downgrade_rx_active) == 0) {
7700 /* Tx or Rx is outside the enabled policy */
7702 "Link is outside of downgrade allowed, downing link\n");
7704 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7705 lwde, ppd->link_width_downgrade_tx_active,
7706 ppd->link_width_downgrade_rx_active);
7708 link_downgraded = false;
7712 mutex_unlock(&ppd->hls_lock);
7715 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_WIDTH_POLICY, 0,
7716 OPA_LINKDOWN_REASON_WIDTH_POLICY);
7717 set_link_state(ppd, HLS_DN_OFFLINE);
7721 return link_downgraded;
7725 * Handle a link downgrade interrupt from the 8051.
7727 * This is a work-queue function outside of the interrupt.
7729 void handle_link_downgrade(struct work_struct *work)
7731 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
7732 link_downgrade_work);
7734 dd_dev_info(ppd->dd, "8051: Link width downgrade\n");
7735 if (apply_link_downgrade_policy(ppd, true))
7736 update_xmit_counters(ppd, ppd->link_width_downgrade_tx_active);
7739 static char *dcc_err_string(char *buf, int buf_len, u64 flags)
7741 return flag_string(buf, buf_len, flags, dcc_err_flags,
7742 ARRAY_SIZE(dcc_err_flags));
7745 static char *lcb_err_string(char *buf, int buf_len, u64 flags)
7747 return flag_string(buf, buf_len, flags, lcb_err_flags,
7748 ARRAY_SIZE(lcb_err_flags));
7751 static char *dc8051_err_string(char *buf, int buf_len, u64 flags)
7753 return flag_string(buf, buf_len, flags, dc8051_err_flags,
7754 ARRAY_SIZE(dc8051_err_flags));
7757 static char *dc8051_info_err_string(char *buf, int buf_len, u64 flags)
7759 return flag_string(buf, buf_len, flags, dc8051_info_err_flags,
7760 ARRAY_SIZE(dc8051_info_err_flags));
7763 static char *dc8051_info_host_msg_string(char *buf, int buf_len, u64 flags)
7765 return flag_string(buf, buf_len, flags, dc8051_info_host_msg_flags,
7766 ARRAY_SIZE(dc8051_info_host_msg_flags));
7769 static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
7771 struct hfi1_pportdata *ppd = dd->pport;
7772 u64 info, err, host_msg;
7773 int queue_link_down = 0;
7776 /* look at the flags */
7777 if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) {
7778 /* 8051 information set by firmware */
7779 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7780 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
7781 err = (info >> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT)
7782 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK;
7784 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT)
7785 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK;
7788 * Handle error flags.
7790 if (err & FAILED_LNI) {
7792 * LNI error indications are cleared by the 8051
7793 * only when starting polling. Only pay attention
7794 * to them when in the states that occur during
7797 if (ppd->host_link_state
7798 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
7799 queue_link_down = 1;
7800 dd_dev_info(dd, "Link error: %s\n",
7801 dc8051_info_err_string(buf,
7806 err &= ~(u64)FAILED_LNI;
7808 /* unknown frames can happen durning LNI, just count */
7809 if (err & UNKNOWN_FRAME) {
7810 ppd->unknown_frame_count++;
7811 err &= ~(u64)UNKNOWN_FRAME;
7814 /* report remaining errors, but do not do anything */
7815 dd_dev_err(dd, "8051 info error: %s\n",
7816 dc8051_info_err_string(buf, sizeof(buf),
7821 * Handle host message flags.
7823 if (host_msg & HOST_REQ_DONE) {
7825 * Presently, the driver does a busy wait for
7826 * host requests to complete. This is only an
7827 * informational message.
7828 * NOTE: The 8051 clears the host message
7829 * information *on the next 8051 command*.
7830 * Therefore, when linkup is achieved,
7831 * this flag will still be set.
7833 host_msg &= ~(u64)HOST_REQ_DONE;
7835 if (host_msg & BC_SMA_MSG) {
7836 queue_work(ppd->link_wq, &ppd->sma_message_work);
7837 host_msg &= ~(u64)BC_SMA_MSG;
7839 if (host_msg & LINKUP_ACHIEVED) {
7840 dd_dev_info(dd, "8051: Link up\n");
7841 queue_work(ppd->link_wq, &ppd->link_up_work);
7842 host_msg &= ~(u64)LINKUP_ACHIEVED;
7844 if (host_msg & EXT_DEVICE_CFG_REQ) {
7845 handle_8051_request(ppd);
7846 host_msg &= ~(u64)EXT_DEVICE_CFG_REQ;
7848 if (host_msg & VERIFY_CAP_FRAME) {
7849 queue_work(ppd->link_wq, &ppd->link_vc_work);
7850 host_msg &= ~(u64)VERIFY_CAP_FRAME;
7852 if (host_msg & LINK_GOING_DOWN) {
7853 const char *extra = "";
7854 /* no downgrade action needed if going down */
7855 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7856 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7857 extra = " (ignoring downgrade)";
7859 dd_dev_info(dd, "8051: Link down%s\n", extra);
7860 queue_link_down = 1;
7861 host_msg &= ~(u64)LINK_GOING_DOWN;
7863 if (host_msg & LINK_WIDTH_DOWNGRADED) {
7864 queue_work(ppd->link_wq, &ppd->link_downgrade_work);
7865 host_msg &= ~(u64)LINK_WIDTH_DOWNGRADED;
7868 /* report remaining messages, but do not do anything */
7869 dd_dev_info(dd, "8051 info host message: %s\n",
7870 dc8051_info_host_msg_string(buf,
7875 reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK;
7877 if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) {
7879 * Lost the 8051 heartbeat. If this happens, we
7880 * receive constant interrupts about it. Disable
7881 * the interrupt after the first.
7883 dd_dev_err(dd, "Lost 8051 heartbeat\n");
7884 write_csr(dd, DC_DC8051_ERR_EN,
7885 read_csr(dd, DC_DC8051_ERR_EN) &
7886 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK);
7888 reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK;
7891 /* report the error, but do not do anything */
7892 dd_dev_err(dd, "8051 error: %s\n",
7893 dc8051_err_string(buf, sizeof(buf), reg));
7896 if (queue_link_down) {
7898 * if the link is already going down or disabled, do not
7899 * queue another. If there's a link down entry already
7900 * queued, don't queue another one.
7902 if ((ppd->host_link_state &
7903 (HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
7904 ppd->link_enabled == 0) {
7905 dd_dev_info(dd, "%s: not queuing link down. host_link_state %x, link_enabled %x\n",
7906 __func__, ppd->host_link_state,
7909 if (xchg(&ppd->is_link_down_queued, 1) == 1)
7911 "%s: link down request already queued\n",
7914 queue_work(ppd->link_wq, &ppd->link_down_work);
7919 static const char * const fm_config_txt[] = {
7921 "BadHeadDist: Distance violation between two head flits",
7923 "BadTailDist: Distance violation between two tail flits",
7925 "BadCtrlDist: Distance violation between two credit control flits",
7927 "BadCrdAck: Credits return for unsupported VL",
7929 "UnsupportedVLMarker: Received VL Marker",
7931 "BadPreempt: Exceeded the preemption nesting level",
7933 "BadControlFlit: Received unsupported control flit",
7936 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7939 static const char * const port_rcv_txt[] = {
7941 "BadPktLen: Illegal PktLen",
7943 "PktLenTooLong: Packet longer than PktLen",
7945 "PktLenTooShort: Packet shorter than PktLen",
7947 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7949 "BadDLID: Illegal DLID (0, doesn't match HFI)",
7951 "BadL2: Illegal L2 opcode",
7953 "BadSC: Unsupported SC",
7955 "BadRC: Illegal RC",
7957 "PreemptError: Preempting with same VL",
7959 "PreemptVL15: Preempting a VL15 packet",
7962 #define OPA_LDR_FMCONFIG_OFFSET 16
7963 #define OPA_LDR_PORTRCV_OFFSET 0
7964 static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
7966 u64 info, hdr0, hdr1;
7969 struct hfi1_pportdata *ppd = dd->pport;
7973 if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) {
7974 if (!(dd->err_info_uncorrectable & OPA_EI_STATUS_SMASK)) {
7975 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
7976 dd->err_info_uncorrectable = info & OPA_EI_CODE_SMASK;
7977 /* set status bit */
7978 dd->err_info_uncorrectable |= OPA_EI_STATUS_SMASK;
7980 reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK;
7983 if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) {
7984 struct hfi1_pportdata *ppd = dd->pport;
7985 /* this counter saturates at (2^32) - 1 */
7986 if (ppd->link_downed < (u32)UINT_MAX)
7988 reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK;
7991 if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) {
7992 u8 reason_valid = 1;
7994 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
7995 if (!(dd->err_info_fmconfig & OPA_EI_STATUS_SMASK)) {
7996 dd->err_info_fmconfig = info & OPA_EI_CODE_SMASK;
7997 /* set status bit */
7998 dd->err_info_fmconfig |= OPA_EI_STATUS_SMASK;
8008 extra = fm_config_txt[info];
8011 extra = fm_config_txt[info];
8012 if (ppd->port_error_action &
8013 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER) {
8016 * lcl_reason cannot be derived from info
8020 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER;
8025 snprintf(buf, sizeof(buf), "reserved%lld", info);
8030 if (reason_valid && !do_bounce) {
8031 do_bounce = ppd->port_error_action &
8032 (1 << (OPA_LDR_FMCONFIG_OFFSET + info));
8033 lcl_reason = info + OPA_LINKDOWN_REASON_BAD_HEAD_DIST;
8036 /* just report this */
8037 dd_dev_info_ratelimited(dd, "DCC Error: fmconfig error: %s\n",
8039 reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK;
8042 if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) {
8043 u8 reason_valid = 1;
8045 info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
8046 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
8047 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
8048 if (!(dd->err_info_rcvport.status_and_code &
8049 OPA_EI_STATUS_SMASK)) {
8050 dd->err_info_rcvport.status_and_code =
8051 info & OPA_EI_CODE_SMASK;
8052 /* set status bit */
8053 dd->err_info_rcvport.status_and_code |=
8054 OPA_EI_STATUS_SMASK;
8056 * save first 2 flits in the packet that caused
8059 dd->err_info_rcvport.packet_flit1 = hdr0;
8060 dd->err_info_rcvport.packet_flit2 = hdr1;
8073 extra = port_rcv_txt[info];
8077 snprintf(buf, sizeof(buf), "reserved%lld", info);
8082 if (reason_valid && !do_bounce) {
8083 do_bounce = ppd->port_error_action &
8084 (1 << (OPA_LDR_PORTRCV_OFFSET + info));
8085 lcl_reason = info + OPA_LINKDOWN_REASON_RCV_ERROR_0;
8088 /* just report this */
8089 dd_dev_info_ratelimited(dd, "DCC Error: PortRcv error: %s\n"
8090 " hdr0 0x%llx, hdr1 0x%llx\n",
8093 reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK;
8096 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) {
8097 /* informative only */
8098 dd_dev_info_ratelimited(dd, "8051 access to LCB blocked\n");
8099 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK;
8101 if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) {
8102 /* informative only */
8103 dd_dev_info_ratelimited(dd, "host access to LCB blocked\n");
8104 reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK;
8107 if (unlikely(hfi1_dbg_fault_suppress_err(&dd->verbs_dev)))
8108 reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK;
8110 /* report any remaining errors */
8112 dd_dev_info_ratelimited(dd, "DCC Error: %s\n",
8113 dcc_err_string(buf, sizeof(buf), reg));
8115 if (lcl_reason == 0)
8116 lcl_reason = OPA_LINKDOWN_REASON_UNKNOWN;
8119 dd_dev_info_ratelimited(dd, "%s: PortErrorAction bounce\n",
8121 set_link_down_reason(ppd, lcl_reason, 0, lcl_reason);
8122 queue_work(ppd->link_wq, &ppd->link_bounce_work);
8126 static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
8130 dd_dev_info(dd, "LCB Error: %s\n",
8131 lcb_err_string(buf, sizeof(buf), reg));
8135 * CCE block DC interrupt. Source is < 8.
8137 static void is_dc_int(struct hfi1_devdata *dd, unsigned int source)
8139 const struct err_reg_info *eri = &dc_errs[source];
8142 interrupt_clear_down(dd, 0, eri);
8143 } else if (source == 3 /* dc_lbm_int */) {
8145 * This indicates that a parity error has occurred on the
8146 * address/control lines presented to the LBM. The error
8147 * is a single pulse, there is no associated error flag,
8148 * and it is non-maskable. This is because if a parity
8149 * error occurs on the request the request is dropped.
8150 * This should never occur, but it is nice to know if it
8153 dd_dev_err(dd, "Parity error in DC LBM block\n");
8155 dd_dev_err(dd, "Invalid DC interrupt %u\n", source);
8160 * TX block send credit interrupt. Source is < 160.
8162 static void is_send_credit_int(struct hfi1_devdata *dd, unsigned int source)
8164 sc_group_release_update(dd, source);
8168 * TX block SDMA interrupt. Source is < 48.
8170 * SDMA interrupts are grouped by type:
8173 * N - 2N-1 = SDmaProgress
8174 * 2N - 3N-1 = SDmaIdle
8176 static void is_sdma_eng_int(struct hfi1_devdata *dd, unsigned int source)
8178 /* what interrupt */
8179 unsigned int what = source / TXE_NUM_SDMA_ENGINES;
8181 unsigned int which = source % TXE_NUM_SDMA_ENGINES;
8183 #ifdef CONFIG_SDMA_VERBOSITY
8184 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", which,
8185 slashstrip(__FILE__), __LINE__, __func__);
8186 sdma_dumpstate(&dd->per_sdma[which]);
8189 if (likely(what < 3 && which < dd->num_sdma)) {
8190 sdma_engine_interrupt(&dd->per_sdma[which], 1ull << source);
8192 /* should not happen */
8193 dd_dev_err(dd, "Invalid SDMA interrupt 0x%x\n", source);
8198 * is_rcv_avail_int() - User receive context available IRQ handler
8200 * @source: logical IRQ source (offset from IS_RCVAVAIL_START)
8202 * RX block receive available interrupt. Source is < 160.
8204 * This is the general interrupt handler for user (PSM) receive contexts,
8205 * and can only be used for non-threaded IRQs.
8207 static void is_rcv_avail_int(struct hfi1_devdata *dd, unsigned int source)
8209 struct hfi1_ctxtdata *rcd;
8212 if (likely(source < dd->num_rcv_contexts)) {
8213 rcd = hfi1_rcd_get_by_index(dd, source);
8215 handle_user_interrupt(rcd);
8219 /* received an interrupt, but no rcd */
8220 err_detail = "dataless";
8222 /* received an interrupt, but are not using that context */
8223 err_detail = "out of range";
8225 dd_dev_err(dd, "unexpected %s receive available context interrupt %u\n",
8226 err_detail, source);
8230 * is_rcv_urgent_int() - User receive context urgent IRQ handler
8232 * @source: logical IRQ source (offset from IS_RCVURGENT_START)
8234 * RX block receive urgent interrupt. Source is < 160.
8236 * NOTE: kernel receive contexts specifically do NOT enable this IRQ.
8238 static void is_rcv_urgent_int(struct hfi1_devdata *dd, unsigned int source)
8240 struct hfi1_ctxtdata *rcd;
8243 if (likely(source < dd->num_rcv_contexts)) {
8244 rcd = hfi1_rcd_get_by_index(dd, source);
8246 handle_user_interrupt(rcd);
8250 /* received an interrupt, but no rcd */
8251 err_detail = "dataless";
8253 /* received an interrupt, but are not using that context */
8254 err_detail = "out of range";
8256 dd_dev_err(dd, "unexpected %s receive urgent context interrupt %u\n",
8257 err_detail, source);
8261 * Reserved range interrupt. Should not be called in normal operation.
8263 static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
8267 dd_dev_err(dd, "unexpected %s interrupt\n",
8268 is_reserved_name(name, sizeof(name), source));
8271 static const struct is_table is_table[] = {
8274 * name func interrupt func
8276 { IS_GENERAL_ERR_START, IS_GENERAL_ERR_END,
8277 is_misc_err_name, is_misc_err_int },
8278 { IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END,
8279 is_sdma_eng_err_name, is_sdma_eng_err_int },
8280 { IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END,
8281 is_sendctxt_err_name, is_sendctxt_err_int },
8282 { IS_SDMA_START, IS_SDMA_IDLE_END,
8283 is_sdma_eng_name, is_sdma_eng_int },
8284 { IS_VARIOUS_START, IS_VARIOUS_END,
8285 is_various_name, is_various_int },
8286 { IS_DC_START, IS_DC_END,
8287 is_dc_name, is_dc_int },
8288 { IS_RCVAVAIL_START, IS_RCVAVAIL_END,
8289 is_rcv_avail_name, is_rcv_avail_int },
8290 { IS_RCVURGENT_START, IS_RCVURGENT_END,
8291 is_rcv_urgent_name, is_rcv_urgent_int },
8292 { IS_SENDCREDIT_START, IS_SENDCREDIT_END,
8293 is_send_credit_name, is_send_credit_int},
8294 { IS_RESERVED_START, IS_RESERVED_END,
8295 is_reserved_name, is_reserved_int},
8299 * Interrupt source interrupt - called when the given source has an interrupt.
8300 * Source is a bit index into an array of 64-bit integers.
8302 static void is_interrupt(struct hfi1_devdata *dd, unsigned int source)
8304 const struct is_table *entry;
8306 /* avoids a double compare by walking the table in-order */
8307 for (entry = &is_table[0]; entry->is_name; entry++) {
8308 if (source <= entry->end) {
8309 trace_hfi1_interrupt(dd, entry, source);
8310 entry->is_int(dd, source - entry->start);
8314 /* fell off the end */
8315 dd_dev_err(dd, "invalid interrupt source %u\n", source);
8319 * gerneral_interrupt() - General interrupt handler
8320 * @irq: MSIx IRQ vector
8321 * @data: hfi1 devdata
8323 * This is able to correctly handle all non-threaded interrupts. Receive
8324 * context DATA IRQs are threaded and are not supported by this handler.
8327 irqreturn_t general_interrupt(int irq, void *data)
8329 struct hfi1_devdata *dd = data;
8330 u64 regs[CCE_NUM_INT_CSRS];
8333 irqreturn_t handled = IRQ_NONE;
8335 this_cpu_inc(*dd->int_counter);
8337 /* phase 1: scan and clear all handled interrupts */
8338 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
8339 if (dd->gi_mask[i] == 0) {
8340 regs[i] = 0; /* used later */
8343 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
8345 /* only clear if anything is set */
8347 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]);
8350 /* phase 2: call the appropriate handler */
8351 for_each_set_bit(bit, (unsigned long *)®s[0],
8352 CCE_NUM_INT_CSRS * 64) {
8353 is_interrupt(dd, bit);
8354 handled = IRQ_HANDLED;
8360 irqreturn_t sdma_interrupt(int irq, void *data)
8362 struct sdma_engine *sde = data;
8363 struct hfi1_devdata *dd = sde->dd;
8366 #ifdef CONFIG_SDMA_VERBOSITY
8367 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
8368 slashstrip(__FILE__), __LINE__, __func__);
8369 sdma_dumpstate(sde);
8372 this_cpu_inc(*dd->int_counter);
8374 /* This read_csr is really bad in the hot path */
8375 status = read_csr(dd,
8376 CCE_INT_STATUS + (8 * (IS_SDMA_START / 64)))
8378 if (likely(status)) {
8379 /* clear the interrupt(s) */
8381 CCE_INT_CLEAR + (8 * (IS_SDMA_START / 64)),
8384 /* handle the interrupt(s) */
8385 sdma_engine_interrupt(sde, status);
8387 dd_dev_info_ratelimited(dd, "SDMA engine %u interrupt, but no status bits set\n",
8394 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8395 * to insure that the write completed. This does NOT guarantee that
8396 * queued DMA writes to memory from the chip are pushed.
8398 static inline void clear_recv_intr(struct hfi1_ctxtdata *rcd)
8400 struct hfi1_devdata *dd = rcd->dd;
8401 u32 addr = CCE_INT_CLEAR + (8 * rcd->ireg);
8403 write_csr(dd, addr, rcd->imask);
8404 /* force the above write on the chip and get a value back */
8405 (void)read_csr(dd, addr);
8408 /* force the receive interrupt */
8409 void force_recv_intr(struct hfi1_ctxtdata *rcd)
8411 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask);
8415 * Return non-zero if a packet is present.
8417 * This routine is called when rechecking for packets after the RcvAvail
8418 * interrupt has been cleared down. First, do a quick check of memory for
8419 * a packet present. If not found, use an expensive CSR read of the context
8420 * tail to determine the actual tail. The CSR read is necessary because there
8421 * is no method to push pending DMAs to memory other than an interrupt and we
8422 * are trying to determine if we need to force an interrupt.
8424 static inline int check_packet_present(struct hfi1_ctxtdata *rcd)
8428 if (hfi1_packet_present(rcd))
8431 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8432 tail = (u32)read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
8433 return hfi1_rcd_head(rcd) != tail;
8437 * Common code for receive contexts interrupt handlers.
8438 * Update traces, increment kernel IRQ counter and
8439 * setup ASPM when needed.
8441 static void receive_interrupt_common(struct hfi1_ctxtdata *rcd)
8443 struct hfi1_devdata *dd = rcd->dd;
8445 trace_hfi1_receive_interrupt(dd, rcd);
8446 this_cpu_inc(*dd->int_counter);
8447 aspm_ctx_disable(rcd);
8451 * __hfi1_rcd_eoi_intr() - Make HW issue receive interrupt
8452 * when there are packets present in the queue. When calling
8453 * with interrupts enabled please use hfi1_rcd_eoi_intr.
8455 * @rcd: valid receive context
8457 static void __hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd)
8461 clear_recv_intr(rcd);
8462 if (check_packet_present(rcd))
8463 force_recv_intr(rcd);
8467 * hfi1_rcd_eoi_intr() - End of Interrupt processing action
8469 * @rcd: Ptr to hfi1_ctxtdata of receive context
8471 * Hold IRQs so we can safely clear the interrupt and
8472 * recheck for a packet that may have arrived after the previous
8473 * check and the interrupt clear. If a packet arrived, force another
8474 * interrupt. This routine can be called at the end of receive packet
8475 * processing in interrupt service routines, interrupt service thread
8478 static void hfi1_rcd_eoi_intr(struct hfi1_ctxtdata *rcd)
8480 unsigned long flags;
8482 local_irq_save(flags);
8483 __hfi1_rcd_eoi_intr(rcd);
8484 local_irq_restore(flags);
8488 * hfi1_netdev_rx_napi - napi poll function to move eoi inline
8489 * @napi - pointer to napi object
8490 * @budget - netdev budget
8492 int hfi1_netdev_rx_napi(struct napi_struct *napi, int budget)
8494 struct hfi1_netdev_rxq *rxq = container_of(napi,
8495 struct hfi1_netdev_rxq, napi);
8496 struct hfi1_ctxtdata *rcd = rxq->rcd;
8499 work_done = rcd->do_interrupt(rcd, budget);
8501 if (work_done < budget) {
8502 napi_complete_done(napi, work_done);
8503 hfi1_rcd_eoi_intr(rcd);
8509 /* Receive packet napi handler for netdevs VNIC and AIP */
8510 irqreturn_t receive_context_interrupt_napi(int irq, void *data)
8512 struct hfi1_ctxtdata *rcd = data;
8514 receive_interrupt_common(rcd);
8516 if (likely(rcd->napi)) {
8517 if (likely(napi_schedule_prep(rcd->napi)))
8518 __napi_schedule_irqoff(rcd->napi);
8520 __hfi1_rcd_eoi_intr(rcd);
8522 WARN_ONCE(1, "Napi IRQ handler without napi set up ctxt=%d\n",
8524 __hfi1_rcd_eoi_intr(rcd);
8531 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8532 * This routine will try to handle packets immediately (latency), but if
8533 * it finds too many, it will invoke the thread handler (bandwitdh). The
8534 * chip receive interrupt is *not* cleared down until this or the thread (if
8535 * invoked) is finished. The intent is to avoid extra interrupts while we
8536 * are processing packets anyway.
8538 irqreturn_t receive_context_interrupt(int irq, void *data)
8540 struct hfi1_ctxtdata *rcd = data;
8543 receive_interrupt_common(rcd);
8545 /* receive interrupt remains blocked while processing packets */
8546 disposition = rcd->do_interrupt(rcd, 0);
8549 * Too many packets were seen while processing packets in this
8550 * IRQ handler. Invoke the handler thread. The receive interrupt
8553 if (disposition == RCV_PKT_LIMIT)
8554 return IRQ_WAKE_THREAD;
8556 __hfi1_rcd_eoi_intr(rcd);
8561 * Receive packet thread handler. This expects to be invoked with the
8562 * receive interrupt still blocked.
8564 irqreturn_t receive_context_thread(int irq, void *data)
8566 struct hfi1_ctxtdata *rcd = data;
8568 /* receive interrupt is still blocked from the IRQ handler */
8569 (void)rcd->do_interrupt(rcd, 1);
8571 hfi1_rcd_eoi_intr(rcd);
8576 /* ========================================================================= */
8578 u32 read_physical_state(struct hfi1_devdata *dd)
8582 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
8583 return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT)
8584 & DC_DC8051_STS_CUR_STATE_PORT_MASK;
8587 u32 read_logical_state(struct hfi1_devdata *dd)
8591 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8592 return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT)
8593 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK;
8596 static void set_logical_state(struct hfi1_devdata *dd, u32 chip_lstate)
8600 reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
8601 /* clear current state, set new state */
8602 reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK;
8603 reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT;
8604 write_csr(dd, DCC_CFG_PORT_CONFIG, reg);
8608 * Use the 8051 to read a LCB CSR.
8610 static int read_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 *data)
8615 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
8616 if (acquire_lcb_access(dd, 0) == 0) {
8617 *data = read_csr(dd, addr);
8618 release_lcb_access(dd, 0);
8624 /* register is an index of LCB registers: (offset - base) / 8 */
8625 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8626 ret = do_8051_command(dd, HCMD_READ_LCB_CSR, regno, data);
8627 if (ret != HCMD_SUCCESS)
8633 * Provide a cache for some of the LCB registers in case the LCB is
8635 * (The LCB is unavailable in certain link states, for example.)
8642 static struct lcb_datum lcb_cache[] = {
8643 { DC_LCB_ERR_INFO_RX_REPLAY_CNT, 0},
8644 { DC_LCB_ERR_INFO_SEQ_CRC_CNT, 0 },
8645 { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT, 0 },
8648 static void update_lcb_cache(struct hfi1_devdata *dd)
8654 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8655 ret = read_lcb_csr(dd, lcb_cache[i].off, &val);
8657 /* Update if we get good data */
8658 if (likely(ret != -EBUSY))
8659 lcb_cache[i].val = val;
8663 static int read_lcb_cache(u32 off, u64 *val)
8667 for (i = 0; i < ARRAY_SIZE(lcb_cache); i++) {
8668 if (lcb_cache[i].off == off) {
8669 *val = lcb_cache[i].val;
8674 pr_warn("%s bad offset 0x%x\n", __func__, off);
8679 * Read an LCB CSR. Access may not be in host control, so check.
8680 * Return 0 on success, -EBUSY on failure.
8682 int read_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 *data)
8684 struct hfi1_pportdata *ppd = dd->pport;
8686 /* if up, go through the 8051 for the value */
8687 if (ppd->host_link_state & HLS_UP)
8688 return read_lcb_via_8051(dd, addr, data);
8689 /* if going up or down, check the cache, otherwise, no access */
8690 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE)) {
8691 if (read_lcb_cache(addr, data))
8696 /* otherwise, host has access */
8697 *data = read_csr(dd, addr);
8702 * Use the 8051 to write a LCB CSR.
8704 static int write_lcb_via_8051(struct hfi1_devdata *dd, u32 addr, u64 data)
8709 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR ||
8710 (dd->dc8051_ver < dc8051_ver(0, 20, 0))) {
8711 if (acquire_lcb_access(dd, 0) == 0) {
8712 write_csr(dd, addr, data);
8713 release_lcb_access(dd, 0);
8719 /* register is an index of LCB registers: (offset - base) / 8 */
8720 regno = (addr - DC_LCB_CFG_RUN) >> 3;
8721 ret = do_8051_command(dd, HCMD_WRITE_LCB_CSR, regno, &data);
8722 if (ret != HCMD_SUCCESS)
8728 * Write an LCB CSR. Access may not be in host control, so check.
8729 * Return 0 on success, -EBUSY on failure.
8731 int write_lcb_csr(struct hfi1_devdata *dd, u32 addr, u64 data)
8733 struct hfi1_pportdata *ppd = dd->pport;
8735 /* if up, go through the 8051 for the value */
8736 if (ppd->host_link_state & HLS_UP)
8737 return write_lcb_via_8051(dd, addr, data);
8738 /* if going up or down, no access */
8739 if (ppd->host_link_state & (HLS_GOING_UP | HLS_GOING_OFFLINE))
8741 /* otherwise, host has access */
8742 write_csr(dd, addr, data);
8748 * < 0 = Linux error, not able to get access
8749 * > 0 = 8051 command RETURN_CODE
8751 static int do_8051_command(struct hfi1_devdata *dd, u32 type, u64 in_data,
8756 unsigned long timeout;
8758 hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
8760 mutex_lock(&dd->dc8051_lock);
8762 /* We can't send any commands to the 8051 if it's in reset */
8763 if (dd->dc_shutdown) {
8764 return_code = -ENODEV;
8769 * If an 8051 host command timed out previously, then the 8051 is
8772 * On first timeout, attempt to reset and restart the entire DC
8773 * block (including 8051). (Is this too big of a hammer?)
8775 * If the 8051 times out a second time, the reset did not bring it
8776 * back to healthy life. In that case, fail any subsequent commands.
8778 if (dd->dc8051_timed_out) {
8779 if (dd->dc8051_timed_out > 1) {
8781 "Previous 8051 host command timed out, skipping command %u\n",
8783 return_code = -ENXIO;
8791 * If there is no timeout, then the 8051 command interface is
8792 * waiting for a command.
8796 * When writing a LCB CSR, out_data contains the full value to
8797 * to be written, while in_data contains the relative LCB
8798 * address in 7:0. Do the work here, rather than the caller,
8799 * of distrubting the write data to where it needs to go:
8802 * 39:00 -> in_data[47:8]
8803 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8804 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8806 if (type == HCMD_WRITE_LCB_CSR) {
8807 in_data |= ((*out_data) & 0xffffffffffull) << 8;
8808 /* must preserve COMPLETED - it is tied to hardware */
8809 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);
8810 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK;
8811 reg |= ((((*out_data) >> 40) & 0xff) <<
8812 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8813 | ((((*out_data) >> 48) & 0xffff) <<
8814 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
8815 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg);
8819 * Do two writes: the first to stabilize the type and req_data, the
8820 * second to activate.
8822 reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK)
8823 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8824 | (in_data & DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK)
8825 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT;
8826 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8827 reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK;
8828 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg);
8830 /* wait for completion, alternate: interrupt */
8831 timeout = jiffies + msecs_to_jiffies(DC8051_COMMAND_TIMEOUT);
8833 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
8834 completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK;
8837 if (time_after(jiffies, timeout)) {
8838 dd->dc8051_timed_out++;
8839 dd_dev_err(dd, "8051 host command %u timeout\n", type);
8842 return_code = -ETIMEDOUT;
8849 *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT)
8850 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK;
8851 if (type == HCMD_READ_LCB_CSR) {
8852 /* top 16 bits are in a different register */
8853 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
8854 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK)
8856 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT);
8859 return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT)
8860 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK;
8861 dd->dc8051_timed_out = 0;
8863 * Clear command for next user.
8865 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0);
8868 mutex_unlock(&dd->dc8051_lock);
8872 static int set_physical_link_state(struct hfi1_devdata *dd, u64 state)
8874 return do_8051_command(dd, HCMD_CHANGE_PHY_STATE, state, NULL);
8877 int load_8051_config(struct hfi1_devdata *dd, u8 field_id,
8878 u8 lane_id, u32 config_data)
8883 data = (u64)field_id << LOAD_DATA_FIELD_ID_SHIFT
8884 | (u64)lane_id << LOAD_DATA_LANE_ID_SHIFT
8885 | (u64)config_data << LOAD_DATA_DATA_SHIFT;
8886 ret = do_8051_command(dd, HCMD_LOAD_CONFIG_DATA, data, NULL);
8887 if (ret != HCMD_SUCCESS) {
8889 "load 8051 config: field id %d, lane %d, err %d\n",
8890 (int)field_id, (int)lane_id, ret);
8896 * Read the 8051 firmware "registers". Use the RAM directly. Always
8897 * set the result, even on error.
8898 * Return 0 on success, -errno on failure
8900 int read_8051_config(struct hfi1_devdata *dd, u8 field_id, u8 lane_id,
8907 /* address start depends on the lane_id */
8909 addr = (4 * NUM_GENERAL_FIELDS)
8910 + (lane_id * 4 * NUM_LANE_FIELDS);
8913 addr += field_id * 4;
8915 /* read is in 8-byte chunks, hardware will truncate the address down */
8916 ret = read_8051_data(dd, addr, 8, &big_data);
8919 /* extract the 4 bytes we want */
8921 *result = (u32)(big_data >> 32);
8923 *result = (u32)big_data;
8926 dd_dev_err(dd, "%s: direct read failed, lane %d, field %d!\n",
8927 __func__, lane_id, field_id);
8933 static int write_vc_local_phy(struct hfi1_devdata *dd, u8 power_management,
8938 frame = continuous << CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8939 | power_management << POWER_MANAGEMENT_SHIFT;
8940 return load_8051_config(dd, VERIFY_CAP_LOCAL_PHY,
8941 GENERAL_CONFIG, frame);
8944 static int write_vc_local_fabric(struct hfi1_devdata *dd, u8 vau, u8 z, u8 vcu,
8945 u16 vl15buf, u8 crc_sizes)
8949 frame = (u32)vau << VAU_SHIFT
8951 | (u32)vcu << VCU_SHIFT
8952 | (u32)vl15buf << VL15BUF_SHIFT
8953 | (u32)crc_sizes << CRC_SIZES_SHIFT;
8954 return load_8051_config(dd, VERIFY_CAP_LOCAL_FABRIC,
8955 GENERAL_CONFIG, frame);
8958 static void read_vc_local_link_mode(struct hfi1_devdata *dd, u8 *misc_bits,
8959 u8 *flag_bits, u16 *link_widths)
8963 read_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG,
8965 *misc_bits = (frame >> MISC_CONFIG_BITS_SHIFT) & MISC_CONFIG_BITS_MASK;
8966 *flag_bits = (frame >> LOCAL_FLAG_BITS_SHIFT) & LOCAL_FLAG_BITS_MASK;
8967 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
8970 static int write_vc_local_link_mode(struct hfi1_devdata *dd,
8977 frame = (u32)misc_bits << MISC_CONFIG_BITS_SHIFT
8978 | (u32)flag_bits << LOCAL_FLAG_BITS_SHIFT
8979 | (u32)link_widths << LINK_WIDTH_SHIFT;
8980 return load_8051_config(dd, VERIFY_CAP_LOCAL_LINK_MODE, GENERAL_CONFIG,
8984 static int write_local_device_id(struct hfi1_devdata *dd, u16 device_id,
8989 frame = ((u32)device_id << LOCAL_DEVICE_ID_SHIFT)
8990 | ((u32)device_rev << LOCAL_DEVICE_REV_SHIFT);
8991 return load_8051_config(dd, LOCAL_DEVICE_ID, GENERAL_CONFIG, frame);
8994 static void read_remote_device_id(struct hfi1_devdata *dd, u16 *device_id,
8999 read_8051_config(dd, REMOTE_DEVICE_ID, GENERAL_CONFIG, &frame);
9000 *device_id = (frame >> REMOTE_DEVICE_ID_SHIFT) & REMOTE_DEVICE_ID_MASK;
9001 *device_rev = (frame >> REMOTE_DEVICE_REV_SHIFT)
9002 & REMOTE_DEVICE_REV_MASK;
9005 int write_host_interface_version(struct hfi1_devdata *dd, u8 version)
9010 mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT);
9011 read_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG, &frame);
9012 /* Clear, then set field */
9014 frame |= ((u32)version << HOST_INTERFACE_VERSION_SHIFT);
9015 return load_8051_config(dd, RESERVED_REGISTERS, GENERAL_CONFIG,
9019 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor,
9024 read_8051_config(dd, MISC_STATUS, GENERAL_CONFIG, &frame);
9025 *ver_major = (frame >> STS_FM_VERSION_MAJOR_SHIFT) &
9026 STS_FM_VERSION_MAJOR_MASK;
9027 *ver_minor = (frame >> STS_FM_VERSION_MINOR_SHIFT) &
9028 STS_FM_VERSION_MINOR_MASK;
9030 read_8051_config(dd, VERSION_PATCH, GENERAL_CONFIG, &frame);
9031 *ver_patch = (frame >> STS_FM_VERSION_PATCH_SHIFT) &
9032 STS_FM_VERSION_PATCH_MASK;
9035 static void read_vc_remote_phy(struct hfi1_devdata *dd, u8 *power_management,
9040 read_8051_config(dd, VERIFY_CAP_REMOTE_PHY, GENERAL_CONFIG, &frame);
9041 *power_management = (frame >> POWER_MANAGEMENT_SHIFT)
9042 & POWER_MANAGEMENT_MASK;
9043 *continuous = (frame >> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT)
9044 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK;
9047 static void read_vc_remote_fabric(struct hfi1_devdata *dd, u8 *vau, u8 *z,
9048 u8 *vcu, u16 *vl15buf, u8 *crc_sizes)
9052 read_8051_config(dd, VERIFY_CAP_REMOTE_FABRIC, GENERAL_CONFIG, &frame);
9053 *vau = (frame >> VAU_SHIFT) & VAU_MASK;
9054 *z = (frame >> Z_SHIFT) & Z_MASK;
9055 *vcu = (frame >> VCU_SHIFT) & VCU_MASK;
9056 *vl15buf = (frame >> VL15BUF_SHIFT) & VL15BUF_MASK;
9057 *crc_sizes = (frame >> CRC_SIZES_SHIFT) & CRC_SIZES_MASK;
9060 static void read_vc_remote_link_width(struct hfi1_devdata *dd,
9066 read_8051_config(dd, VERIFY_CAP_REMOTE_LINK_WIDTH, GENERAL_CONFIG,
9068 *remote_tx_rate = (frame >> REMOTE_TX_RATE_SHIFT)
9069 & REMOTE_TX_RATE_MASK;
9070 *link_widths = (frame >> LINK_WIDTH_SHIFT) & LINK_WIDTH_MASK;
9073 static void read_local_lni(struct hfi1_devdata *dd, u8 *enable_lane_rx)
9077 read_8051_config(dd, LOCAL_LNI_INFO, GENERAL_CONFIG, &frame);
9078 *enable_lane_rx = (frame >> ENABLE_LANE_RX_SHIFT) & ENABLE_LANE_RX_MASK;
9081 static void read_last_local_state(struct hfi1_devdata *dd, u32 *lls)
9083 read_8051_config(dd, LAST_LOCAL_STATE_COMPLETE, GENERAL_CONFIG, lls);
9086 static void read_last_remote_state(struct hfi1_devdata *dd, u32 *lrs)
9088 read_8051_config(dd, LAST_REMOTE_STATE_COMPLETE, GENERAL_CONFIG, lrs);
9091 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality)
9097 if (dd->pport->host_link_state & HLS_UP) {
9098 ret = read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG,
9101 *link_quality = (frame >> LINK_QUALITY_SHIFT)
9102 & LINK_QUALITY_MASK;
9106 static void read_planned_down_reason_code(struct hfi1_devdata *dd, u8 *pdrrc)
9110 read_8051_config(dd, LINK_QUALITY_INFO, GENERAL_CONFIG, &frame);
9111 *pdrrc = (frame >> DOWN_REMOTE_REASON_SHIFT) & DOWN_REMOTE_REASON_MASK;
9114 static void read_link_down_reason(struct hfi1_devdata *dd, u8 *ldr)
9118 read_8051_config(dd, LINK_DOWN_REASON, GENERAL_CONFIG, &frame);
9119 *ldr = (frame & 0xff);
9122 static int read_tx_settings(struct hfi1_devdata *dd,
9124 u8 *tx_polarity_inversion,
9125 u8 *rx_polarity_inversion,
9131 ret = read_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, &frame);
9132 *enable_lane_tx = (frame >> ENABLE_LANE_TX_SHIFT)
9133 & ENABLE_LANE_TX_MASK;
9134 *tx_polarity_inversion = (frame >> TX_POLARITY_INVERSION_SHIFT)
9135 & TX_POLARITY_INVERSION_MASK;
9136 *rx_polarity_inversion = (frame >> RX_POLARITY_INVERSION_SHIFT)
9137 & RX_POLARITY_INVERSION_MASK;
9138 *max_rate = (frame >> MAX_RATE_SHIFT) & MAX_RATE_MASK;
9142 static int write_tx_settings(struct hfi1_devdata *dd,
9144 u8 tx_polarity_inversion,
9145 u8 rx_polarity_inversion,
9150 /* no need to mask, all variable sizes match field widths */
9151 frame = enable_lane_tx << ENABLE_LANE_TX_SHIFT
9152 | tx_polarity_inversion << TX_POLARITY_INVERSION_SHIFT
9153 | rx_polarity_inversion << RX_POLARITY_INVERSION_SHIFT
9154 | max_rate << MAX_RATE_SHIFT;
9155 return load_8051_config(dd, TX_SETTINGS, GENERAL_CONFIG, frame);
9159 * Read an idle LCB message.
9161 * Returns 0 on success, -EINVAL on error
9163 static int read_idle_message(struct hfi1_devdata *dd, u64 type, u64 *data_out)
9167 ret = do_8051_command(dd, HCMD_READ_LCB_IDLE_MSG, type, data_out);
9168 if (ret != HCMD_SUCCESS) {
9169 dd_dev_err(dd, "read idle message: type %d, err %d\n",
9173 dd_dev_info(dd, "%s: read idle message 0x%llx\n", __func__, *data_out);
9174 /* return only the payload as we already know the type */
9175 *data_out >>= IDLE_PAYLOAD_SHIFT;
9180 * Read an idle SMA message. To be done in response to a notification from
9183 * Returns 0 on success, -EINVAL on error
9185 static int read_idle_sma(struct hfi1_devdata *dd, u64 *data)
9187 return read_idle_message(dd, (u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT,
9192 * Send an idle LCB message.
9194 * Returns 0 on success, -EINVAL on error
9196 static int send_idle_message(struct hfi1_devdata *dd, u64 data)
9200 dd_dev_info(dd, "%s: sending idle message 0x%llx\n", __func__, data);
9201 ret = do_8051_command(dd, HCMD_SEND_LCB_IDLE_MSG, data, NULL);
9202 if (ret != HCMD_SUCCESS) {
9203 dd_dev_err(dd, "send idle message: data 0x%llx, err %d\n",
9211 * Send an idle SMA message.
9213 * Returns 0 on success, -EINVAL on error
9215 int send_idle_sma(struct hfi1_devdata *dd, u64 message)
9219 data = ((message & IDLE_PAYLOAD_MASK) << IDLE_PAYLOAD_SHIFT) |
9220 ((u64)IDLE_SMA << IDLE_MSG_TYPE_SHIFT);
9221 return send_idle_message(dd, data);
9225 * Initialize the LCB then do a quick link up. This may or may not be
9228 * return 0 on success, -errno on error
9230 static int do_quick_linkup(struct hfi1_devdata *dd)
9234 lcb_shutdown(dd, 0);
9237 /* LCB_CFG_LOOPBACK.VAL = 2 */
9238 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
9239 write_csr(dd, DC_LCB_CFG_LOOPBACK,
9240 IB_PACKET_TYPE << DC_LCB_CFG_LOOPBACK_VAL_SHIFT);
9241 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
9244 /* start the LCBs */
9245 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
9246 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
9248 /* simulator only loopback steps */
9249 if (loopback && dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
9250 /* LCB_CFG_RUN.EN = 1 */
9251 write_csr(dd, DC_LCB_CFG_RUN,
9252 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
9254 ret = wait_link_transfer_active(dd, 10);
9258 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP,
9259 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT);
9264 * When doing quick linkup and not in loopback, both
9265 * sides must be done with LCB set-up before either
9266 * starts the quick linkup. Put a delay here so that
9267 * both sides can be started and have a chance to be
9268 * done with LCB set up before resuming.
9271 "Pausing for peer to be finished with LCB set up\n");
9273 dd_dev_err(dd, "Continuing with quick linkup\n");
9276 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */
9277 set_8051_lcb_access(dd);
9280 * State "quick" LinkUp request sets the physical link state to
9281 * LinkUp without a verify capability sequence.
9282 * This state is in simulator v37 and later.
9284 ret = set_physical_link_state(dd, PLS_QUICK_LINKUP);
9285 if (ret != HCMD_SUCCESS) {
9287 "%s: set physical link state to quick LinkUp failed with return %d\n",
9290 set_host_lcb_access(dd);
9291 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
9298 return 0; /* success */
9302 * Do all special steps to set up loopback.
9304 static int init_loopback(struct hfi1_devdata *dd)
9306 dd_dev_info(dd, "Entering loopback mode\n");
9308 /* all loopbacks should disable self GUID check */
9309 write_csr(dd, DC_DC8051_CFG_MODE,
9310 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
9313 * The simulator has only one loopback option - LCB. Switch
9314 * to that option, which includes quick link up.
9316 * Accept all valid loopback values.
9318 if ((dd->icode == ICODE_FUNCTIONAL_SIMULATOR) &&
9319 (loopback == LOOPBACK_SERDES || loopback == LOOPBACK_LCB ||
9320 loopback == LOOPBACK_CABLE)) {
9321 loopback = LOOPBACK_LCB;
9327 * SerDes loopback init sequence is handled in set_local_link_attributes
9329 if (loopback == LOOPBACK_SERDES)
9332 /* LCB loopback - handled at poll time */
9333 if (loopback == LOOPBACK_LCB) {
9334 quick_linkup = 1; /* LCB is always quick linkup */
9336 /* not supported in emulation due to emulation RTL changes */
9337 if (dd->icode == ICODE_FPGA_EMULATION) {
9339 "LCB loopback not supported in emulation\n");
9345 /* external cable loopback requires no extra steps */
9346 if (loopback == LOOPBACK_CABLE)
9349 dd_dev_err(dd, "Invalid loopback mode %d\n", loopback);
9354 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9355 * used in the Verify Capability link width attribute.
9357 static u16 opa_to_vc_link_widths(u16 opa_widths)
9362 static const struct link_bits {
9365 } opa_link_xlate[] = {
9366 { OPA_LINK_WIDTH_1X, 1 << (1 - 1) },
9367 { OPA_LINK_WIDTH_2X, 1 << (2 - 1) },
9368 { OPA_LINK_WIDTH_3X, 1 << (3 - 1) },
9369 { OPA_LINK_WIDTH_4X, 1 << (4 - 1) },
9372 for (i = 0; i < ARRAY_SIZE(opa_link_xlate); i++) {
9373 if (opa_widths & opa_link_xlate[i].from)
9374 result |= opa_link_xlate[i].to;
9380 * Set link attributes before moving to polling.
9382 static int set_local_link_attributes(struct hfi1_pportdata *ppd)
9384 struct hfi1_devdata *dd = ppd->dd;
9386 u8 tx_polarity_inversion;
9387 u8 rx_polarity_inversion;
9390 /* reset our fabric serdes to clear any lingering problems */
9391 fabric_serdes_reset(dd);
9393 /* set the local tx rate - need to read-modify-write */
9394 ret = read_tx_settings(dd, &enable_lane_tx, &tx_polarity_inversion,
9395 &rx_polarity_inversion, &ppd->local_tx_rate);
9397 goto set_local_link_attributes_fail;
9399 if (dd->dc8051_ver < dc8051_ver(0, 20, 0)) {
9400 /* set the tx rate to the fastest enabled */
9401 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9402 ppd->local_tx_rate = 1;
9404 ppd->local_tx_rate = 0;
9406 /* set the tx rate to all enabled */
9407 ppd->local_tx_rate = 0;
9408 if (ppd->link_speed_enabled & OPA_LINK_SPEED_25G)
9409 ppd->local_tx_rate |= 2;
9410 if (ppd->link_speed_enabled & OPA_LINK_SPEED_12_5G)
9411 ppd->local_tx_rate |= 1;
9414 enable_lane_tx = 0xF; /* enable all four lanes */
9415 ret = write_tx_settings(dd, enable_lane_tx, tx_polarity_inversion,
9416 rx_polarity_inversion, ppd->local_tx_rate);
9417 if (ret != HCMD_SUCCESS)
9418 goto set_local_link_attributes_fail;
9420 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION);
9421 if (ret != HCMD_SUCCESS) {
9423 "Failed to set host interface version, return 0x%x\n",
9425 goto set_local_link_attributes_fail;
9429 * DC supports continuous updates.
9431 ret = write_vc_local_phy(dd,
9432 0 /* no power management */,
9433 1 /* continuous updates */);
9434 if (ret != HCMD_SUCCESS)
9435 goto set_local_link_attributes_fail;
9437 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9438 ret = write_vc_local_fabric(dd, dd->vau, 1, dd->vcu, dd->vl15_init,
9439 ppd->port_crc_mode_enabled);
9440 if (ret != HCMD_SUCCESS)
9441 goto set_local_link_attributes_fail;
9444 * SerDes loopback init sequence requires
9445 * setting bit 0 of MISC_CONFIG_BITS
9447 if (loopback == LOOPBACK_SERDES)
9448 misc_bits |= 1 << LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT;
9451 * An external device configuration request is used to reset the LCB
9452 * to retry to obtain operational lanes when the first attempt is
9455 if (dd->dc8051_ver >= dc8051_ver(1, 25, 0))
9456 misc_bits |= 1 << EXT_CFG_LCB_RESET_SUPPORTED_SHIFT;
9458 ret = write_vc_local_link_mode(dd, misc_bits, 0,
9459 opa_to_vc_link_widths(
9460 ppd->link_width_enabled));
9461 if (ret != HCMD_SUCCESS)
9462 goto set_local_link_attributes_fail;
9464 /* let peer know who we are */
9465 ret = write_local_device_id(dd, dd->pcidev->device, dd->minrev);
9466 if (ret == HCMD_SUCCESS)
9469 set_local_link_attributes_fail:
9471 "Failed to set local link attributes, return 0x%x\n",
9477 * Call this to start the link.
9478 * Do not do anything if the link is disabled.
9479 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9481 int start_link(struct hfi1_pportdata *ppd)
9484 * Tune the SerDes to a ballpark setting for optimal signal and bit
9485 * error rate. Needs to be done before starting the link.
9489 if (!ppd->driver_link_ready) {
9490 dd_dev_info(ppd->dd,
9491 "%s: stopping link start because driver is not ready\n",
9497 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9498 * pkey table can be configured properly if the HFI unit is connected
9499 * to switch port with MgmtAllowed=NO
9501 clear_full_mgmt_pkey(ppd);
9503 return set_link_state(ppd, HLS_DN_POLL);
9506 static void wait_for_qsfp_init(struct hfi1_pportdata *ppd)
9508 struct hfi1_devdata *dd = ppd->dd;
9510 unsigned long timeout;
9513 * Some QSFP cables have a quirk that asserts the IntN line as a side
9514 * effect of power up on plug-in. We ignore this false positive
9515 * interrupt until the module has finished powering up by waiting for
9516 * a minimum timeout of the module inrush initialization time of
9517 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9518 * module have stabilized.
9523 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
9525 timeout = jiffies + msecs_to_jiffies(2000);
9527 mask = read_csr(dd, dd->hfi1_id ?
9528 ASIC_QSFP2_IN : ASIC_QSFP1_IN);
9529 if (!(mask & QSFP_HFI0_INT_N))
9531 if (time_after(jiffies, timeout)) {
9532 dd_dev_info(dd, "%s: No IntN detected, reset complete\n",
9540 static void set_qsfp_int_n(struct hfi1_pportdata *ppd, u8 enable)
9542 struct hfi1_devdata *dd = ppd->dd;
9545 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
9548 * Clear the status register to avoid an immediate interrupt
9549 * when we re-enable the IntN pin
9551 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9553 mask |= (u64)QSFP_HFI0_INT_N;
9555 mask &= ~(u64)QSFP_HFI0_INT_N;
9557 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask);
9560 int reset_qsfp(struct hfi1_pportdata *ppd)
9562 struct hfi1_devdata *dd = ppd->dd;
9563 u64 mask, qsfp_mask;
9565 /* Disable INT_N from triggering QSFP interrupts */
9566 set_qsfp_int_n(ppd, 0);
9568 /* Reset the QSFP */
9569 mask = (u64)QSFP_HFI0_RESET_N;
9571 qsfp_mask = read_csr(dd,
9572 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT);
9575 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9581 dd->hfi1_id ? ASIC_QSFP2_OUT : ASIC_QSFP1_OUT, qsfp_mask);
9583 wait_for_qsfp_init(ppd);
9586 * Allow INT_N to trigger the QSFP interrupt to watch
9587 * for alarms and warnings
9589 set_qsfp_int_n(ppd, 1);
9592 * After the reset, AOC transmitters are enabled by default. They need
9593 * to be turned off to complete the QSFP setup before they can be
9596 return set_qsfp_tx(ppd, 0);
9599 static int handle_qsfp_error_conditions(struct hfi1_pportdata *ppd,
9600 u8 *qsfp_interrupt_status)
9602 struct hfi1_devdata *dd = ppd->dd;
9604 if ((qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_ALARM) ||
9605 (qsfp_interrupt_status[0] & QSFP_HIGH_TEMP_WARNING))
9606 dd_dev_err(dd, "%s: QSFP cable temperature too high\n",
9609 if ((qsfp_interrupt_status[0] & QSFP_LOW_TEMP_ALARM) ||
9610 (qsfp_interrupt_status[0] & QSFP_LOW_TEMP_WARNING))
9611 dd_dev_err(dd, "%s: QSFP cable temperature too low\n",
9615 * The remaining alarms/warnings don't matter if the link is down.
9617 if (ppd->host_link_state & HLS_DOWN)
9620 if ((qsfp_interrupt_status[1] & QSFP_HIGH_VCC_ALARM) ||
9621 (qsfp_interrupt_status[1] & QSFP_HIGH_VCC_WARNING))
9622 dd_dev_err(dd, "%s: QSFP supply voltage too high\n",
9625 if ((qsfp_interrupt_status[1] & QSFP_LOW_VCC_ALARM) ||
9626 (qsfp_interrupt_status[1] & QSFP_LOW_VCC_WARNING))
9627 dd_dev_err(dd, "%s: QSFP supply voltage too low\n",
9630 /* Byte 2 is vendor specific */
9632 if ((qsfp_interrupt_status[3] & QSFP_HIGH_POWER_ALARM) ||
9633 (qsfp_interrupt_status[3] & QSFP_HIGH_POWER_WARNING))
9634 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too high\n",
9637 if ((qsfp_interrupt_status[3] & QSFP_LOW_POWER_ALARM) ||
9638 (qsfp_interrupt_status[3] & QSFP_LOW_POWER_WARNING))
9639 dd_dev_err(dd, "%s: Cable RX channel 1/2 power too low\n",
9642 if ((qsfp_interrupt_status[4] & QSFP_HIGH_POWER_ALARM) ||
9643 (qsfp_interrupt_status[4] & QSFP_HIGH_POWER_WARNING))
9644 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too high\n",
9647 if ((qsfp_interrupt_status[4] & QSFP_LOW_POWER_ALARM) ||
9648 (qsfp_interrupt_status[4] & QSFP_LOW_POWER_WARNING))
9649 dd_dev_err(dd, "%s: Cable RX channel 3/4 power too low\n",
9652 if ((qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_ALARM) ||
9653 (qsfp_interrupt_status[5] & QSFP_HIGH_BIAS_WARNING))
9654 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too high\n",
9657 if ((qsfp_interrupt_status[5] & QSFP_LOW_BIAS_ALARM) ||
9658 (qsfp_interrupt_status[5] & QSFP_LOW_BIAS_WARNING))
9659 dd_dev_err(dd, "%s: Cable TX channel 1/2 bias too low\n",
9662 if ((qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_ALARM) ||
9663 (qsfp_interrupt_status[6] & QSFP_HIGH_BIAS_WARNING))
9664 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too high\n",
9667 if ((qsfp_interrupt_status[6] & QSFP_LOW_BIAS_ALARM) ||
9668 (qsfp_interrupt_status[6] & QSFP_LOW_BIAS_WARNING))
9669 dd_dev_err(dd, "%s: Cable TX channel 3/4 bias too low\n",
9672 if ((qsfp_interrupt_status[7] & QSFP_HIGH_POWER_ALARM) ||
9673 (qsfp_interrupt_status[7] & QSFP_HIGH_POWER_WARNING))
9674 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too high\n",
9677 if ((qsfp_interrupt_status[7] & QSFP_LOW_POWER_ALARM) ||
9678 (qsfp_interrupt_status[7] & QSFP_LOW_POWER_WARNING))
9679 dd_dev_err(dd, "%s: Cable TX channel 1/2 power too low\n",
9682 if ((qsfp_interrupt_status[8] & QSFP_HIGH_POWER_ALARM) ||
9683 (qsfp_interrupt_status[8] & QSFP_HIGH_POWER_WARNING))
9684 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too high\n",
9687 if ((qsfp_interrupt_status[8] & QSFP_LOW_POWER_ALARM) ||
9688 (qsfp_interrupt_status[8] & QSFP_LOW_POWER_WARNING))
9689 dd_dev_err(dd, "%s: Cable TX channel 3/4 power too low\n",
9692 /* Bytes 9-10 and 11-12 are reserved */
9693 /* Bytes 13-15 are vendor specific */
9698 /* This routine will only be scheduled if the QSFP module present is asserted */
9699 void qsfp_event(struct work_struct *work)
9701 struct qsfp_data *qd;
9702 struct hfi1_pportdata *ppd;
9703 struct hfi1_devdata *dd;
9705 qd = container_of(work, struct qsfp_data, qsfp_work);
9710 if (!qsfp_mod_present(ppd))
9713 if (ppd->host_link_state == HLS_DN_DISABLE) {
9714 dd_dev_info(ppd->dd,
9715 "%s: stopping link start because link is disabled\n",
9721 * Turn DC back on after cable has been re-inserted. Up until
9722 * now, the DC has been in reset to save power.
9726 if (qd->cache_refresh_required) {
9727 set_qsfp_int_n(ppd, 0);
9729 wait_for_qsfp_init(ppd);
9732 * Allow INT_N to trigger the QSFP interrupt to watch
9733 * for alarms and warnings
9735 set_qsfp_int_n(ppd, 1);
9740 if (qd->check_interrupt_flags) {
9741 u8 qsfp_interrupt_status[16] = {0,};
9743 if (one_qsfp_read(ppd, dd->hfi1_id, 6,
9744 &qsfp_interrupt_status[0], 16) != 16) {
9746 "%s: Failed to read status of QSFP module\n",
9749 unsigned long flags;
9751 handle_qsfp_error_conditions(
9752 ppd, qsfp_interrupt_status);
9753 spin_lock_irqsave(&ppd->qsfp_info.qsfp_lock, flags);
9754 ppd->qsfp_info.check_interrupt_flags = 0;
9755 spin_unlock_irqrestore(&ppd->qsfp_info.qsfp_lock,
9761 void init_qsfp_int(struct hfi1_devdata *dd)
9763 struct hfi1_pportdata *ppd = dd->pport;
9766 qsfp_mask = (u64)(QSFP_HFI0_INT_N | QSFP_HFI0_MODPRST_N);
9767 /* Clear current status to avoid spurious interrupts */
9768 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR,
9770 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK,
9773 set_qsfp_int_n(ppd, 0);
9775 /* Handle active low nature of INT_N and MODPRST_N pins */
9776 if (qsfp_mod_present(ppd))
9777 qsfp_mask &= ~(u64)QSFP_HFI0_MODPRST_N;
9779 dd->hfi1_id ? ASIC_QSFP2_INVERT : ASIC_QSFP1_INVERT,
9782 /* Enable the appropriate QSFP IRQ source */
9784 set_intr_bits(dd, QSFP1_INT, QSFP1_INT, true);
9786 set_intr_bits(dd, QSFP2_INT, QSFP2_INT, true);
9790 * Do a one-time initialize of the LCB block.
9792 static void init_lcb(struct hfi1_devdata *dd)
9794 /* simulator does not correctly handle LCB cclk loopback, skip */
9795 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
9798 /* the DC has been reset earlier in the driver load */
9800 /* set LCB for cclk loopback on the port */
9801 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01);
9802 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00);
9803 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00);
9804 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
9805 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08);
9806 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02);
9807 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00);
9811 * Perform a test read on the QSFP. Return 0 on success, -ERRNO
9814 static int test_qsfp_read(struct hfi1_pportdata *ppd)
9820 * Report success if not a QSFP or, if it is a QSFP, but the cable is
9823 if (ppd->port_type != PORT_TYPE_QSFP || !qsfp_mod_present(ppd))
9826 /* read byte 2, the status byte */
9827 ret = one_qsfp_read(ppd, ppd->dd->hfi1_id, 2, &status, 1);
9833 return 0; /* success */
9837 * Values for QSFP retry.
9839 * Give up after 10s (20 x 500ms). The overall timeout was empirically
9840 * arrived at from experience on a large cluster.
9842 #define MAX_QSFP_RETRIES 20
9843 #define QSFP_RETRY_WAIT 500 /* msec */
9846 * Try a QSFP read. If it fails, schedule a retry for later.
9847 * Called on first link activation after driver load.
9849 static void try_start_link(struct hfi1_pportdata *ppd)
9851 if (test_qsfp_read(ppd)) {
9853 if (ppd->qsfp_retry_count >= MAX_QSFP_RETRIES) {
9854 dd_dev_err(ppd->dd, "QSFP not responding, giving up\n");
9857 dd_dev_info(ppd->dd,
9858 "QSFP not responding, waiting and retrying %d\n",
9859 (int)ppd->qsfp_retry_count);
9860 ppd->qsfp_retry_count++;
9861 queue_delayed_work(ppd->link_wq, &ppd->start_link_work,
9862 msecs_to_jiffies(QSFP_RETRY_WAIT));
9865 ppd->qsfp_retry_count = 0;
9871 * Workqueue function to start the link after a delay.
9873 void handle_start_link(struct work_struct *work)
9875 struct hfi1_pportdata *ppd = container_of(work, struct hfi1_pportdata,
9876 start_link_work.work);
9877 try_start_link(ppd);
9880 int bringup_serdes(struct hfi1_pportdata *ppd)
9882 struct hfi1_devdata *dd = ppd->dd;
9886 if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9887 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9889 guid = ppd->guids[HFI1_PORT_GUID_INDEX];
9892 guid = dd->base_guid + ppd->port - 1;
9893 ppd->guids[HFI1_PORT_GUID_INDEX] = guid;
9896 /* Set linkinit_reason on power up per OPA spec */
9897 ppd->linkinit_reason = OPA_LINKINIT_REASON_LINKUP;
9899 /* one-time init of the LCB */
9903 ret = init_loopback(dd);
9909 if (ppd->port_type == PORT_TYPE_QSFP) {
9910 set_qsfp_int_n(ppd, 0);
9911 wait_for_qsfp_init(ppd);
9912 set_qsfp_int_n(ppd, 1);
9915 try_start_link(ppd);
9919 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd)
9921 struct hfi1_devdata *dd = ppd->dd;
9924 * Shut down the link and keep it down. First turn off that the
9925 * driver wants to allow the link to be up (driver_link_ready).
9926 * Then make sure the link is not automatically restarted
9927 * (link_enabled). Cancel any pending restart. And finally
9930 ppd->driver_link_ready = 0;
9931 ppd->link_enabled = 0;
9933 ppd->qsfp_retry_count = MAX_QSFP_RETRIES; /* prevent more retries */
9934 flush_delayed_work(&ppd->start_link_work);
9935 cancel_delayed_work_sync(&ppd->start_link_work);
9937 ppd->offline_disabled_reason =
9938 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_REBOOT);
9939 set_link_down_reason(ppd, OPA_LINKDOWN_REASON_REBOOT, 0,
9940 OPA_LINKDOWN_REASON_REBOOT);
9941 set_link_state(ppd, HLS_DN_OFFLINE);
9943 /* disable the port */
9944 clear_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
9945 cancel_work_sync(&ppd->freeze_work);
9948 static inline int init_cpu_counters(struct hfi1_devdata *dd)
9950 struct hfi1_pportdata *ppd;
9953 ppd = (struct hfi1_pportdata *)(dd + 1);
9954 for (i = 0; i < dd->num_pports; i++, ppd++) {
9955 ppd->ibport_data.rvp.rc_acks = NULL;
9956 ppd->ibport_data.rvp.rc_qacks = NULL;
9957 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
9958 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
9959 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
9960 if (!ppd->ibport_data.rvp.rc_acks ||
9961 !ppd->ibport_data.rvp.rc_delayed_comp ||
9962 !ppd->ibport_data.rvp.rc_qacks)
9970 * index is the index into the receive array
9972 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
9973 u32 type, unsigned long pa, u16 order)
9977 if (!(dd->flags & HFI1_PRESENT))
9980 if (type == PT_INVALID || type == PT_INVALID_FLUSH) {
9983 } else if (type > PT_INVALID) {
9985 "unexpected receive array type %u for index %u, not handled\n",
9989 trace_hfi1_put_tid(dd, index, type, pa, order);
9991 #define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */
9992 reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9993 | (u64)order << RCV_ARRAY_RT_BUF_SIZE_SHIFT
9994 | ((pa >> RT_ADDR_SHIFT) & RCV_ARRAY_RT_ADDR_MASK)
9995 << RCV_ARRAY_RT_ADDR_SHIFT;
9996 trace_hfi1_write_rcvarray(dd->rcvarray_wc + (index * 8), reg);
9997 writeq(reg, dd->rcvarray_wc + (index * 8));
9999 if (type == PT_EAGER || type == PT_INVALID_FLUSH || (index & 3) == 3)
10001 * Eager entries are written and flushed
10003 * Expected entries are flushed every 4 writes
10010 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd)
10012 struct hfi1_devdata *dd = rcd->dd;
10015 /* this could be optimized */
10016 for (i = rcd->eager_base; i < rcd->eager_base +
10017 rcd->egrbufs.alloced; i++)
10018 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
10020 for (i = rcd->expected_base;
10021 i < rcd->expected_base + rcd->expected_count; i++)
10022 hfi1_put_tid(dd, i, PT_INVALID, 0, 0);
10025 static const char * const ib_cfg_name_strings[] = {
10026 "HFI1_IB_CFG_LIDLMC",
10027 "HFI1_IB_CFG_LWID_DG_ENB",
10028 "HFI1_IB_CFG_LWID_ENB",
10029 "HFI1_IB_CFG_LWID",
10030 "HFI1_IB_CFG_SPD_ENB",
10032 "HFI1_IB_CFG_RXPOL_ENB",
10033 "HFI1_IB_CFG_LREV_ENB",
10034 "HFI1_IB_CFG_LINKLATENCY",
10035 "HFI1_IB_CFG_HRTBT",
10036 "HFI1_IB_CFG_OP_VLS",
10037 "HFI1_IB_CFG_VL_HIGH_CAP",
10038 "HFI1_IB_CFG_VL_LOW_CAP",
10039 "HFI1_IB_CFG_OVERRUN_THRESH",
10040 "HFI1_IB_CFG_PHYERR_THRESH",
10041 "HFI1_IB_CFG_LINKDEFAULT",
10042 "HFI1_IB_CFG_PKEYS",
10044 "HFI1_IB_CFG_LSTATE",
10045 "HFI1_IB_CFG_VL_HIGH_LIMIT",
10046 "HFI1_IB_CFG_PMA_TICKS",
10050 static const char *ib_cfg_name(int which)
10052 if (which < 0 || which >= ARRAY_SIZE(ib_cfg_name_strings))
10054 return ib_cfg_name_strings[which];
10057 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which)
10059 struct hfi1_devdata *dd = ppd->dd;
10063 case HFI1_IB_CFG_LWID_ENB: /* allowed Link-width */
10064 val = ppd->link_width_enabled;
10066 case HFI1_IB_CFG_LWID: /* currently active Link-width */
10067 val = ppd->link_width_active;
10069 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
10070 val = ppd->link_speed_enabled;
10072 case HFI1_IB_CFG_SPD: /* current Link speed */
10073 val = ppd->link_speed_active;
10076 case HFI1_IB_CFG_RXPOL_ENB: /* Auto-RX-polarity enable */
10077 case HFI1_IB_CFG_LREV_ENB: /* Auto-Lane-reversal enable */
10078 case HFI1_IB_CFG_LINKLATENCY:
10079 goto unimplemented;
10081 case HFI1_IB_CFG_OP_VLS:
10082 val = ppd->actual_vls_operational;
10084 case HFI1_IB_CFG_VL_HIGH_CAP: /* VL arb high priority table size */
10085 val = VL_ARB_HIGH_PRIO_TABLE_SIZE;
10087 case HFI1_IB_CFG_VL_LOW_CAP: /* VL arb low priority table size */
10088 val = VL_ARB_LOW_PRIO_TABLE_SIZE;
10090 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
10091 val = ppd->overrun_threshold;
10093 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
10094 val = ppd->phy_error_threshold;
10096 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
10100 case HFI1_IB_CFG_HRTBT: /* Heartbeat off/enable/auto */
10101 case HFI1_IB_CFG_PMA_TICKS:
10104 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
10107 "%s: which %s: not implemented\n",
10109 ib_cfg_name(which));
10117 * The largest MAD packet size.
10119 #define MAX_MAD_PACKET 2048
10122 * Return the maximum header bytes that can go on the _wire_
10123 * for this device. This count includes the ICRC which is
10124 * not part of the packet held in memory but it is appended
10126 * This is dependent on the device's receive header entry size.
10127 * HFI allows this to be set per-receive context, but the
10128 * driver presently enforces a global value.
10130 u32 lrh_max_header_bytes(struct hfi1_devdata *dd)
10133 * The maximum non-payload (MTU) bytes in LRH.PktLen are
10134 * the Receive Header Entry Size minus the PBC (or RHF) size
10135 * plus one DW for the ICRC appended by HW.
10137 * dd->rcd[0].rcvhdrqentsize is in DW.
10138 * We use rcd[0] as all context will have the same value. Also,
10139 * the first kernel context would have been allocated by now so
10140 * we are guaranteed a valid value.
10142 return (get_hdrqentsize(dd->rcd[0]) - 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
10147 * @ppd - per port data
10149 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
10150 * registers compare against LRH.PktLen, so use the max bytes included
10153 * This routine changes all VL values except VL15, which it maintains at
10156 static void set_send_length(struct hfi1_pportdata *ppd)
10158 struct hfi1_devdata *dd = ppd->dd;
10159 u32 max_hb = lrh_max_header_bytes(dd), dcmtu;
10160 u32 maxvlmtu = dd->vld[15].mtu;
10161 u64 len1 = 0, len2 = (((dd->vld[15].mtu + max_hb) >> 2)
10162 & SEND_LEN_CHECK1_LEN_VL15_MASK) <<
10163 SEND_LEN_CHECK1_LEN_VL15_SHIFT;
10167 for (i = 0; i < ppd->vls_supported; i++) {
10168 if (dd->vld[i].mtu > maxvlmtu)
10169 maxvlmtu = dd->vld[i].mtu;
10171 len1 |= (((dd->vld[i].mtu + max_hb) >> 2)
10172 & SEND_LEN_CHECK0_LEN_VL0_MASK) <<
10173 ((i % 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT);
10175 len2 |= (((dd->vld[i].mtu + max_hb) >> 2)
10176 & SEND_LEN_CHECK1_LEN_VL4_MASK) <<
10177 ((i % 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT);
10179 write_csr(dd, SEND_LEN_CHECK0, len1);
10180 write_csr(dd, SEND_LEN_CHECK1, len2);
10181 /* adjust kernel credit return thresholds based on new MTUs */
10182 /* all kernel receive contexts have the same hdrqentsize */
10183 for (i = 0; i < ppd->vls_supported; i++) {
10184 thres = min(sc_percent_to_threshold(dd->vld[i].sc, 50),
10185 sc_mtu_to_threshold(dd->vld[i].sc,
10187 get_hdrqentsize(dd->rcd[0])));
10188 for (j = 0; j < INIT_SC_PER_VL; j++)
10189 sc_set_cr_threshold(
10190 pio_select_send_context_vl(dd, j, i),
10193 thres = min(sc_percent_to_threshold(dd->vld[15].sc, 50),
10194 sc_mtu_to_threshold(dd->vld[15].sc,
10196 dd->rcd[0]->rcvhdrqentsize));
10197 sc_set_cr_threshold(dd->vld[15].sc, thres);
10199 /* Adjust maximum MTU for the port in DC */
10200 dcmtu = maxvlmtu == 10240 ? DCC_CFG_PORT_MTU_CAP_10240 :
10201 (ilog2(maxvlmtu >> 8) + 1);
10202 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
10203 len1 &= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK;
10204 len1 |= ((u64)dcmtu & DCC_CFG_PORT_CONFIG_MTU_CAP_MASK) <<
10205 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT;
10206 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1);
10209 static void set_lidlmc(struct hfi1_pportdata *ppd)
10213 struct hfi1_devdata *dd = ppd->dd;
10214 u32 mask = ~((1U << ppd->lmc) - 1);
10215 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
10219 * Program 0 in CSR if port lid is extended. This prevents
10220 * 9B packets being sent out for large lids.
10222 lid = (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ? 0 : ppd->lid;
10223 c1 &= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
10224 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK);
10225 c1 |= ((lid & DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK)
10226 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT) |
10227 ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK)
10228 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT);
10229 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1);
10232 * Iterate over all the send contexts and set their SLID check
10234 sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) <<
10235 SEND_CTXT_CHECK_SLID_MASK_SHIFT) |
10236 (((lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) <<
10237 SEND_CTXT_CHECK_SLID_VALUE_SHIFT);
10239 for (i = 0; i < chip_send_contexts(dd); i++) {
10240 hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
10242 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, sreg);
10245 /* Now we have to do the same thing for the sdma engines */
10246 sdma_update_lmc(dd, mask, lid);
10249 static const char *state_completed_string(u32 completed)
10251 static const char * const state_completed[] = {
10257 if (completed < ARRAY_SIZE(state_completed))
10258 return state_completed[completed];
10263 static const char all_lanes_dead_timeout_expired[] =
10264 "All lanes were inactive – was the interconnect media removed?";
10265 static const char tx_out_of_policy[] =
10266 "Passing lanes on local port do not meet the local link width policy";
10267 static const char no_state_complete[] =
10268 "State timeout occurred before link partner completed the state";
10269 static const char * const state_complete_reasons[] = {
10270 [0x00] = "Reason unknown",
10271 [0x01] = "Link was halted by driver, refer to LinkDownReason",
10272 [0x02] = "Link partner reported failure",
10273 [0x10] = "Unable to achieve frame sync on any lane",
10275 "Unable to find a common bit rate with the link partner",
10277 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy",
10279 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10280 [0x14] = no_state_complete,
10282 "State timeout occurred before link partner identified equalization presets",
10284 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10285 [0x17] = tx_out_of_policy,
10286 [0x20] = all_lanes_dead_timeout_expired,
10288 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy",
10289 [0x22] = no_state_complete,
10291 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10292 [0x24] = tx_out_of_policy,
10293 [0x30] = all_lanes_dead_timeout_expired,
10295 "State timeout occurred waiting for host to process received frames",
10296 [0x32] = no_state_complete,
10298 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10299 [0x34] = tx_out_of_policy,
10300 [0x35] = "Negotiated link width is mutually exclusive",
10302 "Timed out before receiving verifycap frames in VerifyCap.Exchange",
10303 [0x37] = "Unable to resolve secure data exchange",
10306 static const char *state_complete_reason_code_string(struct hfi1_pportdata *ppd,
10309 const char *str = NULL;
10311 if (code < ARRAY_SIZE(state_complete_reasons))
10312 str = state_complete_reasons[code];
10319 /* describe the given last state complete frame */
10320 static void decode_state_complete(struct hfi1_pportdata *ppd, u32 frame,
10321 const char *prefix)
10323 struct hfi1_devdata *dd = ppd->dd;
10331 * [ 0: 0] - success
10333 * [ 7: 4] - next state timeout
10334 * [15: 8] - reason code
10337 success = frame & 0x1;
10338 state = (frame >> 1) & 0x7;
10339 reason = (frame >> 8) & 0xff;
10340 lanes = (frame >> 16) & 0xffff;
10342 dd_dev_err(dd, "Last %s LNI state complete frame 0x%08x:\n",
10344 dd_dev_err(dd, " last reported state state: %s (0x%x)\n",
10345 state_completed_string(state), state);
10346 dd_dev_err(dd, " state successfully completed: %s\n",
10347 success ? "yes" : "no");
10348 dd_dev_err(dd, " fail reason 0x%x: %s\n",
10349 reason, state_complete_reason_code_string(ppd, reason));
10350 dd_dev_err(dd, " passing lane mask: 0x%x", lanes);
10354 * Read the last state complete frames and explain them. This routine
10355 * expects to be called if the link went down during link negotiation
10356 * and initialization (LNI). That is, anywhere between polling and link up.
10358 static void check_lni_states(struct hfi1_pportdata *ppd)
10360 u32 last_local_state;
10361 u32 last_remote_state;
10363 read_last_local_state(ppd->dd, &last_local_state);
10364 read_last_remote_state(ppd->dd, &last_remote_state);
10367 * Don't report anything if there is nothing to report. A value of
10368 * 0 means the link was taken down while polling and there was no
10369 * training in-process.
10371 if (last_local_state == 0 && last_remote_state == 0)
10374 decode_state_complete(ppd, last_local_state, "transmitted");
10375 decode_state_complete(ppd, last_remote_state, "received");
10378 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10379 static int wait_link_transfer_active(struct hfi1_devdata *dd, int wait_ms)
10382 unsigned long timeout;
10384 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10385 timeout = jiffies + msecs_to_jiffies(wait_ms);
10387 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
10390 if (time_after(jiffies, timeout)) {
10392 "timeout waiting for LINK_TRANSFER_ACTIVE\n");
10400 /* called when the logical link state is not down as it should be */
10401 static void force_logical_link_state_down(struct hfi1_pportdata *ppd)
10403 struct hfi1_devdata *dd = ppd->dd;
10406 * Bring link up in LCB loopback
10408 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10409 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK,
10410 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK);
10412 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0);
10413 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0);
10414 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110);
10415 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2);
10417 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0);
10418 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET);
10420 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1);
10421 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT);
10423 wait_link_transfer_active(dd, 100);
10426 * Bring the link down again.
10428 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1);
10429 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0);
10430 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0);
10432 dd_dev_info(ppd->dd, "logical state forced to LINK_DOWN\n");
10436 * Helper for set_link_state(). Do not call except from that routine.
10437 * Expects ppd->hls_mutex to be held.
10439 * @rem_reason value to be sent to the neighbor
10441 * LinkDownReasons only set if transition succeeds.
10443 static int goto_offline(struct hfi1_pportdata *ppd, u8 rem_reason)
10445 struct hfi1_devdata *dd = ppd->dd;
10446 u32 previous_state;
10447 int offline_state_ret;
10450 update_lcb_cache(dd);
10452 previous_state = ppd->host_link_state;
10453 ppd->host_link_state = HLS_GOING_OFFLINE;
10455 /* start offline transition */
10456 ret = set_physical_link_state(dd, (rem_reason << 8) | PLS_OFFLINE);
10458 if (ret != HCMD_SUCCESS) {
10460 "Failed to transition to Offline link state, return %d\n",
10464 if (ppd->offline_disabled_reason ==
10465 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
10466 ppd->offline_disabled_reason =
10467 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT);
10469 offline_state_ret = wait_phys_link_offline_substates(ppd, 10000);
10470 if (offline_state_ret < 0)
10471 return offline_state_ret;
10473 /* Disabling AOC transmitters */
10474 if (ppd->port_type == PORT_TYPE_QSFP &&
10475 ppd->qsfp_info.limiting_active &&
10476 qsfp_mod_present(ppd)) {
10479 ret = acquire_chip_resource(dd, qsfp_resource(dd), QSFP_WAIT);
10481 set_qsfp_tx(ppd, 0);
10482 release_chip_resource(dd, qsfp_resource(dd));
10484 /* not fatal, but should warn */
10486 "Unable to acquire lock to turn off QSFP TX\n");
10491 * Wait for the offline.Quiet transition if it hasn't happened yet. It
10492 * can take a while for the link to go down.
10494 if (offline_state_ret != PLS_OFFLINE_QUIET) {
10495 ret = wait_physical_linkstate(ppd, PLS_OFFLINE, 30000);
10501 * Now in charge of LCB - must be after the physical state is
10502 * offline.quiet and before host_link_state is changed.
10504 set_host_lcb_access(dd);
10505 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */
10507 /* make sure the logical state is also down */
10508 ret = wait_logical_linkstate(ppd, IB_PORT_DOWN, 1000);
10510 force_logical_link_state_down(ppd);
10512 ppd->host_link_state = HLS_LINK_COOLDOWN; /* LCB access allowed */
10513 update_statusp(ppd, IB_PORT_DOWN);
10516 * The LNI has a mandatory wait time after the physical state
10517 * moves to Offline.Quiet. The wait time may be different
10518 * depending on how the link went down. The 8051 firmware
10519 * will observe the needed wait time and only move to ready
10520 * when that is completed. The largest of the quiet timeouts
10521 * is 6s, so wait that long and then at least 0.5s more for
10522 * other transitions, and another 0.5s for a buffer.
10524 ret = wait_fm_ready(dd, 7000);
10527 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
10528 /* state is really offline, so make it so */
10529 ppd->host_link_state = HLS_DN_OFFLINE;
10534 * The state is now offline and the 8051 is ready to accept host
10536 * - change our state
10537 * - notify others if we were previously in a linkup state
10539 ppd->host_link_state = HLS_DN_OFFLINE;
10540 if (previous_state & HLS_UP) {
10541 /* went down while link was up */
10542 handle_linkup_change(dd, 0);
10543 } else if (previous_state
10544 & (HLS_DN_POLL | HLS_VERIFY_CAP | HLS_GOING_UP)) {
10545 /* went down while attempting link up */
10546 check_lni_states(ppd);
10548 /* The QSFP doesn't need to be reset on LNI failure */
10549 ppd->qsfp_info.reset_needed = 0;
10552 /* the active link width (downgrade) is 0 on link down */
10553 ppd->link_width_active = 0;
10554 ppd->link_width_downgrade_tx_active = 0;
10555 ppd->link_width_downgrade_rx_active = 0;
10556 ppd->current_egress_rate = 0;
10560 /* return the link state name */
10561 static const char *link_state_name(u32 state)
10564 int n = ilog2(state);
10565 static const char * const names[] = {
10566 [__HLS_UP_INIT_BP] = "INIT",
10567 [__HLS_UP_ARMED_BP] = "ARMED",
10568 [__HLS_UP_ACTIVE_BP] = "ACTIVE",
10569 [__HLS_DN_DOWNDEF_BP] = "DOWNDEF",
10570 [__HLS_DN_POLL_BP] = "POLL",
10571 [__HLS_DN_DISABLE_BP] = "DISABLE",
10572 [__HLS_DN_OFFLINE_BP] = "OFFLINE",
10573 [__HLS_VERIFY_CAP_BP] = "VERIFY_CAP",
10574 [__HLS_GOING_UP_BP] = "GOING_UP",
10575 [__HLS_GOING_OFFLINE_BP] = "GOING_OFFLINE",
10576 [__HLS_LINK_COOLDOWN_BP] = "LINK_COOLDOWN"
10579 name = n < ARRAY_SIZE(names) ? names[n] : NULL;
10580 return name ? name : "unknown";
10583 /* return the link state reason name */
10584 static const char *link_state_reason_name(struct hfi1_pportdata *ppd, u32 state)
10586 if (state == HLS_UP_INIT) {
10587 switch (ppd->linkinit_reason) {
10588 case OPA_LINKINIT_REASON_LINKUP:
10590 case OPA_LINKINIT_REASON_FLAPPING:
10591 return "(FLAPPING)";
10592 case OPA_LINKINIT_OUTSIDE_POLICY:
10593 return "(OUTSIDE_POLICY)";
10594 case OPA_LINKINIT_QUARANTINED:
10595 return "(QUARANTINED)";
10596 case OPA_LINKINIT_INSUFIC_CAPABILITY:
10597 return "(INSUFIC_CAPABILITY)";
10606 * driver_pstate - convert the driver's notion of a port's
10607 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10608 * Return -1 (converted to a u32) to indicate error.
10610 u32 driver_pstate(struct hfi1_pportdata *ppd)
10612 switch (ppd->host_link_state) {
10615 case HLS_UP_ACTIVE:
10616 return IB_PORTPHYSSTATE_LINKUP;
10618 return IB_PORTPHYSSTATE_POLLING;
10619 case HLS_DN_DISABLE:
10620 return IB_PORTPHYSSTATE_DISABLED;
10621 case HLS_DN_OFFLINE:
10622 return OPA_PORTPHYSSTATE_OFFLINE;
10623 case HLS_VERIFY_CAP:
10624 return IB_PORTPHYSSTATE_TRAINING;
10626 return IB_PORTPHYSSTATE_TRAINING;
10627 case HLS_GOING_OFFLINE:
10628 return OPA_PORTPHYSSTATE_OFFLINE;
10629 case HLS_LINK_COOLDOWN:
10630 return OPA_PORTPHYSSTATE_OFFLINE;
10631 case HLS_DN_DOWNDEF:
10633 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10634 ppd->host_link_state);
10640 * driver_lstate - convert the driver's notion of a port's
10641 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10642 * (converted to a u32) to indicate error.
10644 u32 driver_lstate(struct hfi1_pportdata *ppd)
10646 if (ppd->host_link_state && (ppd->host_link_state & HLS_DOWN))
10647 return IB_PORT_DOWN;
10649 switch (ppd->host_link_state & HLS_UP) {
10651 return IB_PORT_INIT;
10653 return IB_PORT_ARMED;
10654 case HLS_UP_ACTIVE:
10655 return IB_PORT_ACTIVE;
10657 dd_dev_err(ppd->dd, "invalid host_link_state 0x%x\n",
10658 ppd->host_link_state);
10663 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
10664 u8 neigh_reason, u8 rem_reason)
10666 if (ppd->local_link_down_reason.latest == 0 &&
10667 ppd->neigh_link_down_reason.latest == 0) {
10668 ppd->local_link_down_reason.latest = lcl_reason;
10669 ppd->neigh_link_down_reason.latest = neigh_reason;
10670 ppd->remote_link_down_reason = rem_reason;
10675 * data_vls_operational() - Verify if data VL BCT credits and MTU
10677 * @ppd: pointer to hfi1_pportdata structure
10679 * Return: true - Ok, false -otherwise.
10681 static inline bool data_vls_operational(struct hfi1_pportdata *ppd)
10686 if (!ppd->actual_vls_operational)
10689 for (i = 0; i < ppd->vls_supported; i++) {
10690 reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i));
10691 if ((reg && !ppd->dd->vld[i].mtu) ||
10692 (!reg && ppd->dd->vld[i].mtu))
10700 * Change the physical and/or logical link state.
10702 * Do not call this routine while inside an interrupt. It contains
10703 * calls to routines that can take multiple seconds to finish.
10705 * Returns 0 on success, -errno on failure.
10707 int set_link_state(struct hfi1_pportdata *ppd, u32 state)
10709 struct hfi1_devdata *dd = ppd->dd;
10710 struct ib_event event = {.device = NULL};
10712 int orig_new_state, poll_bounce;
10714 mutex_lock(&ppd->hls_lock);
10716 orig_new_state = state;
10717 if (state == HLS_DN_DOWNDEF)
10718 state = HLS_DEFAULT;
10720 /* interpret poll -> poll as a link bounce */
10721 poll_bounce = ppd->host_link_state == HLS_DN_POLL &&
10722 state == HLS_DN_POLL;
10724 dd_dev_info(dd, "%s: current %s, new %s %s%s\n", __func__,
10725 link_state_name(ppd->host_link_state),
10726 link_state_name(orig_new_state),
10727 poll_bounce ? "(bounce) " : "",
10728 link_state_reason_name(ppd, state));
10731 * If we're going to a (HLS_*) link state that implies the logical
10732 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10733 * reset is_sm_config_started to 0.
10735 if (!(state & (HLS_UP_ARMED | HLS_UP_ACTIVE)))
10736 ppd->is_sm_config_started = 0;
10739 * Do nothing if the states match. Let a poll to poll link bounce
10742 if (ppd->host_link_state == state && !poll_bounce)
10747 if (ppd->host_link_state == HLS_DN_POLL &&
10748 (quick_linkup || dd->icode == ICODE_FUNCTIONAL_SIMULATOR)) {
10750 * Quick link up jumps from polling to here.
10752 * Whether in normal or loopback mode, the
10753 * simulator jumps from polling to link up.
10754 * Accept that here.
10757 } else if (ppd->host_link_state != HLS_GOING_UP) {
10762 * Wait for Link_Up physical state.
10763 * Physical and Logical states should already be
10764 * be transitioned to LinkUp and LinkInit respectively.
10766 ret = wait_physical_linkstate(ppd, PLS_LINKUP, 1000);
10769 "%s: physical state did not change to LINK-UP\n",
10774 ret = wait_logical_linkstate(ppd, IB_PORT_INIT, 1000);
10777 "%s: logical state did not change to INIT\n",
10782 /* clear old transient LINKINIT_REASON code */
10783 if (ppd->linkinit_reason >= OPA_LINKINIT_REASON_CLEAR)
10784 ppd->linkinit_reason =
10785 OPA_LINKINIT_REASON_LINKUP;
10787 /* enable the port */
10788 add_rcvctrl(dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
10790 handle_linkup_change(dd, 1);
10791 pio_kernel_linkup(dd);
10794 * After link up, a new link width will have been set.
10795 * Update the xmit counters with regards to the new
10798 update_xmit_counters(ppd, ppd->link_width_active);
10800 ppd->host_link_state = HLS_UP_INIT;
10801 update_statusp(ppd, IB_PORT_INIT);
10804 if (ppd->host_link_state != HLS_UP_INIT)
10807 if (!data_vls_operational(ppd)) {
10809 "%s: Invalid data VL credits or mtu\n",
10815 set_logical_state(dd, LSTATE_ARMED);
10816 ret = wait_logical_linkstate(ppd, IB_PORT_ARMED, 1000);
10819 "%s: logical state did not change to ARMED\n",
10823 ppd->host_link_state = HLS_UP_ARMED;
10824 update_statusp(ppd, IB_PORT_ARMED);
10826 * The simulator does not currently implement SMA messages,
10827 * so neighbor_normal is not set. Set it here when we first
10830 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
10831 ppd->neighbor_normal = 1;
10833 case HLS_UP_ACTIVE:
10834 if (ppd->host_link_state != HLS_UP_ARMED)
10837 set_logical_state(dd, LSTATE_ACTIVE);
10838 ret = wait_logical_linkstate(ppd, IB_PORT_ACTIVE, 1000);
10841 "%s: logical state did not change to ACTIVE\n",
10844 /* tell all engines to go running */
10845 sdma_all_running(dd);
10846 ppd->host_link_state = HLS_UP_ACTIVE;
10847 update_statusp(ppd, IB_PORT_ACTIVE);
10849 /* Signal the IB layer that the port has went active */
10850 event.device = &dd->verbs_dev.rdi.ibdev;
10851 event.element.port_num = ppd->port;
10852 event.event = IB_EVENT_PORT_ACTIVE;
10856 if ((ppd->host_link_state == HLS_DN_DISABLE ||
10857 ppd->host_link_state == HLS_DN_OFFLINE) &&
10860 /* Hand LED control to the DC */
10861 write_csr(dd, DCC_CFG_LED_CNTRL, 0);
10863 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10864 u8 tmp = ppd->link_enabled;
10866 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10868 ppd->link_enabled = tmp;
10871 ppd->remote_link_down_reason = 0;
10873 if (ppd->driver_link_ready)
10874 ppd->link_enabled = 1;
10877 set_all_slowpath(ppd->dd);
10878 ret = set_local_link_attributes(ppd);
10882 ppd->port_error_action = 0;
10884 if (quick_linkup) {
10885 /* quick linkup does not go into polling */
10886 ret = do_quick_linkup(dd);
10888 ret1 = set_physical_link_state(dd, PLS_POLLING);
10890 ret1 = wait_phys_link_out_of_offline(ppd,
10892 if (ret1 != HCMD_SUCCESS) {
10894 "Failed to transition to Polling link state, return 0x%x\n",
10901 * Change the host link state after requesting DC8051 to
10902 * change its physical state so that we can ignore any
10903 * interrupt with stale LNI(XX) error, which will not be
10904 * cleared until DC8051 transitions to Polling state.
10906 ppd->host_link_state = HLS_DN_POLL;
10907 ppd->offline_disabled_reason =
10908 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
10910 * If an error occurred above, go back to offline. The
10911 * caller may reschedule another attempt.
10914 goto_offline(ppd, 0);
10916 log_physical_state(ppd, PLS_POLLING);
10918 case HLS_DN_DISABLE:
10919 /* link is disabled */
10920 ppd->link_enabled = 0;
10922 /* allow any state to transition to disabled */
10924 /* must transition to offline first */
10925 if (ppd->host_link_state != HLS_DN_OFFLINE) {
10926 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10929 ppd->remote_link_down_reason = 0;
10932 if (!dd->dc_shutdown) {
10933 ret1 = set_physical_link_state(dd, PLS_DISABLED);
10934 if (ret1 != HCMD_SUCCESS) {
10936 "Failed to transition to Disabled link state, return 0x%x\n",
10941 ret = wait_physical_linkstate(ppd, PLS_DISABLED, 10000);
10944 "%s: physical state did not change to DISABLED\n",
10950 ppd->host_link_state = HLS_DN_DISABLE;
10952 case HLS_DN_OFFLINE:
10953 if (ppd->host_link_state == HLS_DN_DISABLE)
10956 /* allow any state to transition to offline */
10957 ret = goto_offline(ppd, ppd->remote_link_down_reason);
10959 ppd->remote_link_down_reason = 0;
10961 case HLS_VERIFY_CAP:
10962 if (ppd->host_link_state != HLS_DN_POLL)
10964 ppd->host_link_state = HLS_VERIFY_CAP;
10965 log_physical_state(ppd, PLS_CONFIGPHY_VERIFYCAP);
10968 if (ppd->host_link_state != HLS_VERIFY_CAP)
10971 ret1 = set_physical_link_state(dd, PLS_LINKUP);
10972 if (ret1 != HCMD_SUCCESS) {
10974 "Failed to transition to link up state, return 0x%x\n",
10979 ppd->host_link_state = HLS_GOING_UP;
10982 case HLS_GOING_OFFLINE: /* transient within goto_offline() */
10983 case HLS_LINK_COOLDOWN: /* transient within goto_offline() */
10985 dd_dev_info(dd, "%s: state 0x%x: not supported\n",
10994 dd_dev_err(dd, "%s: unexpected state transition from %s to %s\n",
10995 __func__, link_state_name(ppd->host_link_state),
10996 link_state_name(state));
11000 mutex_unlock(&ppd->hls_lock);
11003 ib_dispatch_event(&event);
11008 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val)
11014 case HFI1_IB_CFG_LIDLMC:
11017 case HFI1_IB_CFG_VL_HIGH_LIMIT:
11019 * The VL Arbitrator high limit is sent in units of 4k
11020 * bytes, while HFI stores it in units of 64 bytes.
11023 reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK)
11024 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT;
11025 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg);
11027 case HFI1_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
11028 /* HFI only supports POLL as the default link down state */
11029 if (val != HLS_DN_POLL)
11032 case HFI1_IB_CFG_OP_VLS:
11033 if (ppd->vls_operational != val) {
11034 ppd->vls_operational = val;
11040 * For link width, link width downgrade, and speed enable, always AND
11041 * the setting with what is actually supported. This has two benefits.
11042 * First, enabled can't have unsupported values, no matter what the
11043 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
11044 * "fill in with your supported value" have all the bits in the
11045 * field set, so simply ANDing with supported has the desired result.
11047 case HFI1_IB_CFG_LWID_ENB: /* set allowed Link-width */
11048 ppd->link_width_enabled = val & ppd->link_width_supported;
11050 case HFI1_IB_CFG_LWID_DG_ENB: /* set allowed link width downgrade */
11051 ppd->link_width_downgrade_enabled =
11052 val & ppd->link_width_downgrade_supported;
11054 case HFI1_IB_CFG_SPD_ENB: /* allowed Link speeds */
11055 ppd->link_speed_enabled = val & ppd->link_speed_supported;
11057 case HFI1_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
11059 * HFI does not follow IB specs, save this value
11060 * so we can report it, if asked.
11062 ppd->overrun_threshold = val;
11064 case HFI1_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
11066 * HFI does not follow IB specs, save this value
11067 * so we can report it, if asked.
11069 ppd->phy_error_threshold = val;
11072 case HFI1_IB_CFG_MTU:
11073 set_send_length(ppd);
11076 case HFI1_IB_CFG_PKEYS:
11077 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
11078 set_partition_keys(ppd);
11082 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
11083 dd_dev_info(ppd->dd,
11084 "%s: which %s, val 0x%x: not implemented\n",
11085 __func__, ib_cfg_name(which), val);
11091 /* begin functions related to vl arbitration table caching */
11092 static void init_vl_arb_caches(struct hfi1_pportdata *ppd)
11096 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
11097 VL_ARB_LOW_PRIO_TABLE_SIZE);
11098 BUILD_BUG_ON(VL_ARB_TABLE_SIZE !=
11099 VL_ARB_HIGH_PRIO_TABLE_SIZE);
11102 * Note that we always return values directly from the
11103 * 'vl_arb_cache' (and do no CSR reads) in response to a
11104 * 'Get(VLArbTable)'. This is obviously correct after a
11105 * 'Set(VLArbTable)', since the cache will then be up to
11106 * date. But it's also correct prior to any 'Set(VLArbTable)'
11107 * since then both the cache, and the relevant h/w registers
11111 for (i = 0; i < MAX_PRIO_TABLE; i++)
11112 spin_lock_init(&ppd->vl_arb_cache[i].lock);
11116 * vl_arb_lock_cache
11118 * All other vl_arb_* functions should be called only after locking
11121 static inline struct vl_arb_cache *
11122 vl_arb_lock_cache(struct hfi1_pportdata *ppd, int idx)
11124 if (idx != LO_PRIO_TABLE && idx != HI_PRIO_TABLE)
11126 spin_lock(&ppd->vl_arb_cache[idx].lock);
11127 return &ppd->vl_arb_cache[idx];
11130 static inline void vl_arb_unlock_cache(struct hfi1_pportdata *ppd, int idx)
11132 spin_unlock(&ppd->vl_arb_cache[idx].lock);
11135 static void vl_arb_get_cache(struct vl_arb_cache *cache,
11136 struct ib_vl_weight_elem *vl)
11138 memcpy(vl, cache->table, VL_ARB_TABLE_SIZE * sizeof(*vl));
11141 static void vl_arb_set_cache(struct vl_arb_cache *cache,
11142 struct ib_vl_weight_elem *vl)
11144 memcpy(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
11147 static int vl_arb_match_cache(struct vl_arb_cache *cache,
11148 struct ib_vl_weight_elem *vl)
11150 return !memcmp(cache->table, vl, VL_ARB_TABLE_SIZE * sizeof(*vl));
11153 /* end functions related to vl arbitration table caching */
11155 static int set_vl_weights(struct hfi1_pportdata *ppd, u32 target,
11156 u32 size, struct ib_vl_weight_elem *vl)
11158 struct hfi1_devdata *dd = ppd->dd;
11160 unsigned int i, is_up = 0;
11161 int drain, ret = 0;
11163 mutex_lock(&ppd->hls_lock);
11165 if (ppd->host_link_state & HLS_UP)
11168 drain = !is_ax(dd) && is_up;
11172 * Before adjusting VL arbitration weights, empty per-VL
11173 * FIFOs, otherwise a packet whose VL weight is being
11174 * set to 0 could get stuck in a FIFO with no chance to
11177 ret = stop_drain_data_vls(dd);
11182 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
11187 for (i = 0; i < size; i++, vl++) {
11189 * NOTE: The low priority shift and mask are used here, but
11190 * they are the same for both the low and high registers.
11192 reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK)
11193 << SEND_LOW_PRIORITY_LIST_VL_SHIFT)
11194 | (((u64)vl->weight
11195 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK)
11196 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT);
11197 write_csr(dd, target + (i * 8), reg);
11199 pio_send_control(dd, PSC_GLOBAL_VLARB_ENABLE);
11202 open_fill_data_vls(dd); /* reopen all VLs */
11205 mutex_unlock(&ppd->hls_lock);
11211 * Read one credit merge VL register.
11213 static void read_one_cm_vl(struct hfi1_devdata *dd, u32 csr,
11214 struct vl_limit *vll)
11216 u64 reg = read_csr(dd, csr);
11218 vll->dedicated = cpu_to_be16(
11219 (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT)
11220 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK);
11221 vll->shared = cpu_to_be16(
11222 (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT)
11223 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK);
11227 * Read the current credit merge limits.
11229 static int get_buffer_control(struct hfi1_devdata *dd,
11230 struct buffer_control *bc, u16 *overall_limit)
11235 /* not all entries are filled in */
11236 memset(bc, 0, sizeof(*bc));
11238 /* OPA and HFI have a 1-1 mapping */
11239 for (i = 0; i < TXE_NUM_DATA_VL; i++)
11240 read_one_cm_vl(dd, SEND_CM_CREDIT_VL + (8 * i), &bc->vl[i]);
11242 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
11243 read_one_cm_vl(dd, SEND_CM_CREDIT_VL15, &bc->vl[15]);
11245 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11246 bc->overall_shared_limit = cpu_to_be16(
11247 (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT)
11248 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK);
11250 *overall_limit = (reg
11251 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT)
11252 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK;
11253 return sizeof(struct buffer_control);
11256 static int get_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
11261 /* each register contains 16 SC->VLnt mappings, 4 bits each */
11262 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
11263 for (i = 0; i < sizeof(u64); i++) {
11264 u8 byte = *(((u8 *)®) + i);
11266 dp->vlnt[2 * i] = byte & 0xf;
11267 dp->vlnt[(2 * i) + 1] = (byte & 0xf0) >> 4;
11270 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
11271 for (i = 0; i < sizeof(u64); i++) {
11272 u8 byte = *(((u8 *)®) + i);
11274 dp->vlnt[16 + (2 * i)] = byte & 0xf;
11275 dp->vlnt[16 + (2 * i) + 1] = (byte & 0xf0) >> 4;
11277 return sizeof(struct sc2vlnt);
11280 static void get_vlarb_preempt(struct hfi1_devdata *dd, u32 nelems,
11281 struct ib_vl_weight_elem *vl)
11285 for (i = 0; i < nelems; i++, vl++) {
11291 static void set_sc2vlnt(struct hfi1_devdata *dd, struct sc2vlnt *dp)
11293 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0,
11295 0, dp->vlnt[0] & 0xf,
11296 1, dp->vlnt[1] & 0xf,
11297 2, dp->vlnt[2] & 0xf,
11298 3, dp->vlnt[3] & 0xf,
11299 4, dp->vlnt[4] & 0xf,
11300 5, dp->vlnt[5] & 0xf,
11301 6, dp->vlnt[6] & 0xf,
11302 7, dp->vlnt[7] & 0xf,
11303 8, dp->vlnt[8] & 0xf,
11304 9, dp->vlnt[9] & 0xf,
11305 10, dp->vlnt[10] & 0xf,
11306 11, dp->vlnt[11] & 0xf,
11307 12, dp->vlnt[12] & 0xf,
11308 13, dp->vlnt[13] & 0xf,
11309 14, dp->vlnt[14] & 0xf,
11310 15, dp->vlnt[15] & 0xf));
11311 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16,
11312 DC_SC_VL_VAL(31_16,
11313 16, dp->vlnt[16] & 0xf,
11314 17, dp->vlnt[17] & 0xf,
11315 18, dp->vlnt[18] & 0xf,
11316 19, dp->vlnt[19] & 0xf,
11317 20, dp->vlnt[20] & 0xf,
11318 21, dp->vlnt[21] & 0xf,
11319 22, dp->vlnt[22] & 0xf,
11320 23, dp->vlnt[23] & 0xf,
11321 24, dp->vlnt[24] & 0xf,
11322 25, dp->vlnt[25] & 0xf,
11323 26, dp->vlnt[26] & 0xf,
11324 27, dp->vlnt[27] & 0xf,
11325 28, dp->vlnt[28] & 0xf,
11326 29, dp->vlnt[29] & 0xf,
11327 30, dp->vlnt[30] & 0xf,
11328 31, dp->vlnt[31] & 0xf));
11331 static void nonzero_msg(struct hfi1_devdata *dd, int idx, const char *what,
11335 dd_dev_info(dd, "Invalid %s limit %d on VL %d, ignoring\n",
11336 what, (int)limit, idx);
11339 /* change only the shared limit portion of SendCmGLobalCredit */
11340 static void set_global_shared(struct hfi1_devdata *dd, u16 limit)
11344 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11345 reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK;
11346 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT;
11347 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11350 /* change only the total credit limit portion of SendCmGLobalCredit */
11351 static void set_global_limit(struct hfi1_devdata *dd, u16 limit)
11355 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
11356 reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK;
11357 reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT;
11358 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg);
11361 /* set the given per-VL shared limit */
11362 static void set_vl_shared(struct hfi1_devdata *dd, int vl, u16 limit)
11367 if (vl < TXE_NUM_DATA_VL)
11368 addr = SEND_CM_CREDIT_VL + (8 * vl);
11370 addr = SEND_CM_CREDIT_VL15;
11372 reg = read_csr(dd, addr);
11373 reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK;
11374 reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT;
11375 write_csr(dd, addr, reg);
11378 /* set the given per-VL dedicated limit */
11379 static void set_vl_dedicated(struct hfi1_devdata *dd, int vl, u16 limit)
11384 if (vl < TXE_NUM_DATA_VL)
11385 addr = SEND_CM_CREDIT_VL + (8 * vl);
11387 addr = SEND_CM_CREDIT_VL15;
11389 reg = read_csr(dd, addr);
11390 reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK;
11391 reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT;
11392 write_csr(dd, addr, reg);
11395 /* spin until the given per-VL status mask bits clear */
11396 static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask,
11399 unsigned long timeout;
11402 timeout = jiffies + msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT);
11404 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
11407 return; /* success */
11408 if (time_after(jiffies, timeout))
11409 break; /* timed out */
11414 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
11415 which, VL_STATUS_CLEAR_TIMEOUT, mask, reg);
11417 * If this occurs, it is likely there was a credit loss on the link.
11418 * The only recovery from that is a link bounce.
11421 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n");
11425 * The number of credits on the VLs may be changed while everything
11426 * is "live", but the following algorithm must be followed due to
11427 * how the hardware is actually implemented. In particular,
11428 * Return_Credit_Status[] is the only correct status check.
11430 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11431 * set Global_Shared_Credit_Limit = 0
11433 * mask0 = all VLs that are changing either dedicated or shared limits
11434 * set Shared_Limit[mask0] = 0
11435 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11436 * if (changing any dedicated limit)
11437 * mask1 = all VLs that are lowering dedicated limits
11438 * lower Dedicated_Limit[mask1]
11439 * spin until Return_Credit_Status[mask1] == 0
11440 * raise Dedicated_Limits
11441 * raise Shared_Limits
11442 * raise Global_Shared_Credit_Limit
11444 * lower = if the new limit is lower, set the limit to the new value
11445 * raise = if the new limit is higher than the current value (may be changed
11446 * earlier in the algorithm), set the new limit to the new value
11448 int set_buffer_control(struct hfi1_pportdata *ppd,
11449 struct buffer_control *new_bc)
11451 struct hfi1_devdata *dd = ppd->dd;
11452 u64 changing_mask, ld_mask, stat_mask;
11454 int i, use_all_mask;
11455 int this_shared_changing;
11456 int vl_count = 0, ret;
11458 * A0: add the variable any_shared_limit_changing below and in the
11459 * algorithm above. If removing A0 support, it can be removed.
11461 int any_shared_limit_changing;
11462 struct buffer_control cur_bc;
11463 u8 changing[OPA_MAX_VLS];
11464 u8 lowering_dedicated[OPA_MAX_VLS];
11467 const u64 all_mask =
11468 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11469 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11470 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11471 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11472 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11473 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11474 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11475 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11476 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK;
11478 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11479 #define NUM_USABLE_VLS 16 /* look at VL15 and less */
11481 /* find the new total credits, do sanity check on unused VLs */
11482 for (i = 0; i < OPA_MAX_VLS; i++) {
11484 new_total += be16_to_cpu(new_bc->vl[i].dedicated);
11487 nonzero_msg(dd, i, "dedicated",
11488 be16_to_cpu(new_bc->vl[i].dedicated));
11489 nonzero_msg(dd, i, "shared",
11490 be16_to_cpu(new_bc->vl[i].shared));
11491 new_bc->vl[i].dedicated = 0;
11492 new_bc->vl[i].shared = 0;
11494 new_total += be16_to_cpu(new_bc->overall_shared_limit);
11496 /* fetch the current values */
11497 get_buffer_control(dd, &cur_bc, &cur_total);
11500 * Create the masks we will use.
11502 memset(changing, 0, sizeof(changing));
11503 memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
11505 * NOTE: Assumes that the individual VL bits are adjacent and in
11509 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
11513 any_shared_limit_changing = 0;
11514 for (i = 0; i < NUM_USABLE_VLS; i++, stat_mask <<= 1) {
11517 this_shared_changing = new_bc->vl[i].shared
11518 != cur_bc.vl[i].shared;
11519 if (this_shared_changing)
11520 any_shared_limit_changing = 1;
11521 if (new_bc->vl[i].dedicated != cur_bc.vl[i].dedicated ||
11522 this_shared_changing) {
11524 changing_mask |= stat_mask;
11527 if (be16_to_cpu(new_bc->vl[i].dedicated) <
11528 be16_to_cpu(cur_bc.vl[i].dedicated)) {
11529 lowering_dedicated[i] = 1;
11530 ld_mask |= stat_mask;
11534 /* bracket the credit change with a total adjustment */
11535 if (new_total > cur_total)
11536 set_global_limit(dd, new_total);
11539 * Start the credit change algorithm.
11542 if ((be16_to_cpu(new_bc->overall_shared_limit) <
11543 be16_to_cpu(cur_bc.overall_shared_limit)) ||
11544 (is_ax(dd) && any_shared_limit_changing)) {
11545 set_global_shared(dd, 0);
11546 cur_bc.overall_shared_limit = 0;
11550 for (i = 0; i < NUM_USABLE_VLS; i++) {
11555 set_vl_shared(dd, i, 0);
11556 cur_bc.vl[i].shared = 0;
11560 wait_for_vl_status_clear(dd, use_all_mask ? all_mask : changing_mask,
11563 if (change_count > 0) {
11564 for (i = 0; i < NUM_USABLE_VLS; i++) {
11568 if (lowering_dedicated[i]) {
11569 set_vl_dedicated(dd, i,
11570 be16_to_cpu(new_bc->
11572 cur_bc.vl[i].dedicated =
11573 new_bc->vl[i].dedicated;
11577 wait_for_vl_status_clear(dd, ld_mask, "dedicated");
11579 /* now raise all dedicated that are going up */
11580 for (i = 0; i < NUM_USABLE_VLS; i++) {
11584 if (be16_to_cpu(new_bc->vl[i].dedicated) >
11585 be16_to_cpu(cur_bc.vl[i].dedicated))
11586 set_vl_dedicated(dd, i,
11587 be16_to_cpu(new_bc->
11592 /* next raise all shared that are going up */
11593 for (i = 0; i < NUM_USABLE_VLS; i++) {
11597 if (be16_to_cpu(new_bc->vl[i].shared) >
11598 be16_to_cpu(cur_bc.vl[i].shared))
11599 set_vl_shared(dd, i, be16_to_cpu(new_bc->vl[i].shared));
11602 /* finally raise the global shared */
11603 if (be16_to_cpu(new_bc->overall_shared_limit) >
11604 be16_to_cpu(cur_bc.overall_shared_limit))
11605 set_global_shared(dd,
11606 be16_to_cpu(new_bc->overall_shared_limit));
11608 /* bracket the credit change with a total adjustment */
11609 if (new_total < cur_total)
11610 set_global_limit(dd, new_total);
11613 * Determine the actual number of operational VLS using the number of
11614 * dedicated and shared credits for each VL.
11616 if (change_count > 0) {
11617 for (i = 0; i < TXE_NUM_DATA_VL; i++)
11618 if (be16_to_cpu(new_bc->vl[i].dedicated) > 0 ||
11619 be16_to_cpu(new_bc->vl[i].shared) > 0)
11621 ppd->actual_vls_operational = vl_count;
11622 ret = sdma_map_init(dd, ppd->port - 1, vl_count ?
11623 ppd->actual_vls_operational :
11624 ppd->vls_operational,
11627 ret = pio_map_init(dd, ppd->port - 1, vl_count ?
11628 ppd->actual_vls_operational :
11629 ppd->vls_operational, NULL);
11637 * Read the given fabric manager table. Return the size of the
11638 * table (in bytes) on success, and a negative error code on
11641 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t)
11645 struct vl_arb_cache *vlc;
11648 case FM_TBL_VL_HIGH_ARB:
11651 * OPA specifies 128 elements (of 2 bytes each), though
11652 * HFI supports only 16 elements in h/w.
11654 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11655 vl_arb_get_cache(vlc, t);
11656 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11658 case FM_TBL_VL_LOW_ARB:
11661 * OPA specifies 128 elements (of 2 bytes each), though
11662 * HFI supports only 16 elements in h/w.
11664 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11665 vl_arb_get_cache(vlc, t);
11666 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11668 case FM_TBL_BUFFER_CONTROL:
11669 size = get_buffer_control(ppd->dd, t, NULL);
11671 case FM_TBL_SC2VLNT:
11672 size = get_sc2vlnt(ppd->dd, t);
11674 case FM_TBL_VL_PREEMPT_ELEMS:
11676 /* OPA specifies 128 elements, of 2 bytes each */
11677 get_vlarb_preempt(ppd->dd, OPA_MAX_VLS, t);
11679 case FM_TBL_VL_PREEMPT_MATRIX:
11682 * OPA specifies that this is the same size as the VL
11683 * arbitration tables (i.e., 256 bytes).
11693 * Write the given fabric manager table.
11695 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
11698 struct vl_arb_cache *vlc;
11701 case FM_TBL_VL_HIGH_ARB:
11702 vlc = vl_arb_lock_cache(ppd, HI_PRIO_TABLE);
11703 if (vl_arb_match_cache(vlc, t)) {
11704 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11707 vl_arb_set_cache(vlc, t);
11708 vl_arb_unlock_cache(ppd, HI_PRIO_TABLE);
11709 ret = set_vl_weights(ppd, SEND_HIGH_PRIORITY_LIST,
11710 VL_ARB_HIGH_PRIO_TABLE_SIZE, t);
11712 case FM_TBL_VL_LOW_ARB:
11713 vlc = vl_arb_lock_cache(ppd, LO_PRIO_TABLE);
11714 if (vl_arb_match_cache(vlc, t)) {
11715 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11718 vl_arb_set_cache(vlc, t);
11719 vl_arb_unlock_cache(ppd, LO_PRIO_TABLE);
11720 ret = set_vl_weights(ppd, SEND_LOW_PRIORITY_LIST,
11721 VL_ARB_LOW_PRIO_TABLE_SIZE, t);
11723 case FM_TBL_BUFFER_CONTROL:
11724 ret = set_buffer_control(ppd, t);
11726 case FM_TBL_SC2VLNT:
11727 set_sc2vlnt(ppd->dd, t);
11736 * Disable all data VLs.
11738 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11740 static int disable_data_vls(struct hfi1_devdata *dd)
11745 pio_send_control(dd, PSC_DATA_VL_DISABLE);
11751 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11752 * Just re-enables all data VLs (the "fill" part happens
11753 * automatically - the name was chosen for symmetry with
11754 * stop_drain_data_vls()).
11756 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11758 int open_fill_data_vls(struct hfi1_devdata *dd)
11763 pio_send_control(dd, PSC_DATA_VL_ENABLE);
11769 * drain_data_vls() - assumes that disable_data_vls() has been called,
11770 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11771 * engines to drop to 0.
11773 static void drain_data_vls(struct hfi1_devdata *dd)
11777 pause_for_credit_return(dd);
11781 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11783 * Use open_fill_data_vls() to resume using data VLs. This pair is
11784 * meant to be used like this:
11786 * stop_drain_data_vls(dd);
11787 * // do things with per-VL resources
11788 * open_fill_data_vls(dd);
11790 int stop_drain_data_vls(struct hfi1_devdata *dd)
11794 ret = disable_data_vls(dd);
11796 drain_data_vls(dd);
11802 * Convert a nanosecond time to a cclock count. No matter how slow
11803 * the cclock, a non-zero ns will always have a non-zero result.
11805 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns)
11809 if (dd->icode == ICODE_FPGA_EMULATION)
11810 cclocks = (ns * 1000) / FPGA_CCLOCK_PS;
11811 else /* simulation pretends to be ASIC */
11812 cclocks = (ns * 1000) / ASIC_CCLOCK_PS;
11813 if (ns && !cclocks) /* if ns nonzero, must be at least 1 */
11819 * Convert a cclock count to nanoseconds. Not matter how slow
11820 * the cclock, a non-zero cclocks will always have a non-zero result.
11822 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclocks)
11826 if (dd->icode == ICODE_FPGA_EMULATION)
11827 ns = (cclocks * FPGA_CCLOCK_PS) / 1000;
11828 else /* simulation pretends to be ASIC */
11829 ns = (cclocks * ASIC_CCLOCK_PS) / 1000;
11830 if (cclocks && !ns)
11836 * Dynamically adjust the receive interrupt timeout for a context based on
11837 * incoming packet rate.
11839 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11841 static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
11843 struct hfi1_devdata *dd = rcd->dd;
11844 u32 timeout = rcd->rcvavail_timeout;
11847 * This algorithm doubles or halves the timeout depending on whether
11848 * the number of packets received in this interrupt were less than or
11849 * greater equal the interrupt count.
11851 * The calculations below do not allow a steady state to be achieved.
11852 * Only at the endpoints it is possible to have an unchanging
11855 if (npkts < rcv_intr_count) {
11857 * Not enough packets arrived before the timeout, adjust
11858 * timeout downward.
11860 if (timeout < 2) /* already at minimum? */
11865 * More than enough packets arrived before the timeout, adjust
11868 if (timeout >= dd->rcv_intr_timeout_csr) /* already at max? */
11870 timeout = min(timeout << 1, dd->rcv_intr_timeout_csr);
11873 rcd->rcvavail_timeout = timeout;
11875 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11876 * been verified to be in range
11878 write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
11880 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
11883 void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd,
11884 u32 intr_adjust, u32 npkts)
11886 struct hfi1_devdata *dd = rcd->dd;
11888 u32 ctxt = rcd->ctxt;
11891 * Need to write timeout register before updating RcvHdrHead to ensure
11892 * that a new value is used when the HW decides to restart counting.
11895 adjust_rcv_timeout(rcd, npkts);
11897 reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK)
11898 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT;
11899 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg);
11901 reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) |
11902 (((u64)hd & RCV_HDR_HEAD_HEAD_MASK)
11903 << RCV_HDR_HEAD_HEAD_SHIFT);
11904 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
11907 u32 hdrqempty(struct hfi1_ctxtdata *rcd)
11911 head = (read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_HEAD)
11912 & RCV_HDR_HEAD_HEAD_SMASK) >> RCV_HDR_HEAD_HEAD_SHIFT;
11914 if (hfi1_rcvhdrtail_kvaddr(rcd))
11915 tail = get_rcvhdrtail(rcd);
11917 tail = read_uctxt_csr(rcd->dd, rcd->ctxt, RCV_HDR_TAIL);
11919 return head == tail;
11923 * Context Control and Receive Array encoding for buffer size:
11932 * 0x8 512 KB (Receive Array only)
11933 * 0x9 1 MB (Receive Array only)
11934 * 0xa 2 MB (Receive Array only)
11936 * 0xB-0xF - reserved (Receive Array only)
11939 * This routine assumes that the value has already been sanity checked.
11941 static u32 encoded_size(u32 size)
11944 case 4 * 1024: return 0x1;
11945 case 8 * 1024: return 0x2;
11946 case 16 * 1024: return 0x3;
11947 case 32 * 1024: return 0x4;
11948 case 64 * 1024: return 0x5;
11949 case 128 * 1024: return 0x6;
11950 case 256 * 1024: return 0x7;
11951 case 512 * 1024: return 0x8;
11952 case 1 * 1024 * 1024: return 0x9;
11953 case 2 * 1024 * 1024: return 0xa;
11955 return 0x1; /* if invalid, go with the minimum size */
11959 * encode_rcv_header_entry_size - return chip specific encoding for size
11960 * @size: size in dwords
11962 * Convert a receive header entry size that to the encoding used in the CSR.
11964 * Return a zero if the given size is invalid, otherwise the encoding.
11966 u8 encode_rcv_header_entry_size(u8 size)
11968 /* there are only 3 valid receive header entry sizes */
11975 return 0; /* invalid */
11979 * hfi1_validate_rcvhdrcnt - validate hdrcnt
11980 * @dd: the device data
11981 * @thecnt: the header count
11983 int hfi1_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt)
11985 if (thecnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) {
11986 dd_dev_err(dd, "Receive header queue count too small\n");
11990 if (thecnt > HFI1_MAX_HDRQ_EGRBUF_CNT) {
11992 "Receive header queue count cannot be greater than %u\n",
11993 HFI1_MAX_HDRQ_EGRBUF_CNT);
11997 if (thecnt % HDRQ_INCREMENT) {
11998 dd_dev_err(dd, "Receive header queue count %d must be divisible by %lu\n",
11999 thecnt, HDRQ_INCREMENT);
12007 * set_hdrq_regs - set header queue registers for context
12008 * @dd: the device data
12009 * @ctxt: the context
12010 * @entsize: the dword entry size
12011 * @hdrcnt: the number of header entries
12013 void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt)
12017 reg = (((u64)hdrcnt >> HDRQ_SIZE_SHIFT) & RCV_HDR_CNT_CNT_MASK) <<
12018 RCV_HDR_CNT_CNT_SHIFT;
12019 write_kctxt_csr(dd, ctxt, RCV_HDR_CNT, reg);
12020 reg = ((u64)encode_rcv_header_entry_size(entsize) &
12021 RCV_HDR_ENT_SIZE_ENT_SIZE_MASK) <<
12022 RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT;
12023 write_kctxt_csr(dd, ctxt, RCV_HDR_ENT_SIZE, reg);
12024 reg = ((u64)DEFAULT_RCVHDRSIZE & RCV_HDR_SIZE_HDR_SIZE_MASK) <<
12025 RCV_HDR_SIZE_HDR_SIZE_SHIFT;
12026 write_kctxt_csr(dd, ctxt, RCV_HDR_SIZE, reg);
12029 * Program dummy tail address for every receive context
12030 * before enabling any receive context
12032 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12033 dd->rcvhdrtail_dummy_dma);
12036 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op,
12037 struct hfi1_ctxtdata *rcd)
12040 int did_enable = 0;
12048 hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
12050 rcvctrl = read_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL);
12051 /* if the context already enabled, don't do the extra steps */
12052 if ((op & HFI1_RCVCTRL_CTXT_ENB) &&
12053 !(rcvctrl & RCV_CTXT_CTRL_ENABLE_SMASK)) {
12054 /* reset the tail and hdr addresses, and sequence count */
12055 write_kctxt_csr(dd, ctxt, RCV_HDR_ADDR,
12057 if (hfi1_rcvhdrtail_kvaddr(rcd))
12058 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12059 rcd->rcvhdrqtailaddr_dma);
12060 hfi1_set_seq_cnt(rcd, 1);
12062 /* reset the cached receive header queue head value */
12063 hfi1_set_rcd_head(rcd, 0);
12066 * Zero the receive header queue so we don't get false
12067 * positives when checking the sequence number. The
12068 * sequence numbers could land exactly on the same spot.
12069 * E.g. a rcd restart before the receive header wrapped.
12071 memset(rcd->rcvhdrq, 0, rcvhdrq_size(rcd));
12073 /* starting timeout */
12074 rcd->rcvavail_timeout = dd->rcv_intr_timeout_csr;
12076 /* enable the context */
12077 rcvctrl |= RCV_CTXT_CTRL_ENABLE_SMASK;
12079 /* clean the egr buffer size first */
12080 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
12081 rcvctrl |= ((u64)encoded_size(rcd->egrbufs.rcvtid_size)
12082 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK)
12083 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT;
12085 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
12086 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0);
12089 /* zero RcvEgrIndexHead */
12090 write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, 0);
12092 /* set eager count and base index */
12093 reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT)
12094 & RCV_EGR_CTRL_EGR_CNT_MASK)
12095 << RCV_EGR_CTRL_EGR_CNT_SHIFT) |
12096 (((rcd->eager_base >> RCV_SHIFT)
12097 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK)
12098 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT);
12099 write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg);
12102 * Set TID (expected) count and base index.
12103 * rcd->expected_count is set to individual RcvArray entries,
12104 * not pairs, and the CSR takes a pair-count in groups of
12105 * four, so divide by 8.
12107 reg = (((rcd->expected_count >> RCV_SHIFT)
12108 & RCV_TID_CTRL_TID_PAIR_CNT_MASK)
12109 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT) |
12110 (((rcd->expected_base >> RCV_SHIFT)
12111 & RCV_TID_CTRL_TID_BASE_INDEX_MASK)
12112 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT);
12113 write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg);
12114 if (ctxt == HFI1_CTRL_CTXT)
12115 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT);
12117 if (op & HFI1_RCVCTRL_CTXT_DIS) {
12118 write_csr(dd, RCV_VL15, 0);
12120 * When receive context is being disabled turn on tail
12121 * update with a dummy tail address and then disable
12124 if (dd->rcvhdrtail_dummy_dma) {
12125 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12126 dd->rcvhdrtail_dummy_dma);
12127 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
12128 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
12131 rcvctrl &= ~RCV_CTXT_CTRL_ENABLE_SMASK;
12133 if (op & HFI1_RCVCTRL_INTRAVAIL_ENB) {
12134 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12135 IS_RCVAVAIL_START + rcd->ctxt, true);
12136 rcvctrl |= RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
12138 if (op & HFI1_RCVCTRL_INTRAVAIL_DIS) {
12139 set_intr_bits(dd, IS_RCVAVAIL_START + rcd->ctxt,
12140 IS_RCVAVAIL_START + rcd->ctxt, false);
12141 rcvctrl &= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK;
12143 if ((op & HFI1_RCVCTRL_TAILUPD_ENB) && hfi1_rcvhdrtail_kvaddr(rcd))
12144 rcvctrl |= RCV_CTXT_CTRL_TAIL_UPD_SMASK;
12145 if (op & HFI1_RCVCTRL_TAILUPD_DIS) {
12146 /* See comment on RcvCtxtCtrl.TailUpd above */
12147 if (!(op & HFI1_RCVCTRL_CTXT_DIS))
12148 rcvctrl &= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK;
12150 if (op & HFI1_RCVCTRL_TIDFLOW_ENB)
12151 rcvctrl |= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
12152 if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
12153 rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
12154 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
12156 * In one-packet-per-eager mode, the size comes from
12157 * the RcvArray entry.
12159 rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
12160 rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
12162 if (op & HFI1_RCVCTRL_ONE_PKT_EGR_DIS)
12163 rcvctrl &= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
12164 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_ENB)
12165 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
12166 if (op & HFI1_RCVCTRL_NO_RHQ_DROP_DIS)
12167 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK;
12168 if (op & HFI1_RCVCTRL_NO_EGR_DROP_ENB)
12169 rcvctrl |= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
12170 if (op & HFI1_RCVCTRL_NO_EGR_DROP_DIS)
12171 rcvctrl &= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK;
12172 if (op & HFI1_RCVCTRL_URGENT_ENB)
12173 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12174 IS_RCVURGENT_START + rcd->ctxt, true);
12175 if (op & HFI1_RCVCTRL_URGENT_DIS)
12176 set_intr_bits(dd, IS_RCVURGENT_START + rcd->ctxt,
12177 IS_RCVURGENT_START + rcd->ctxt, false);
12179 hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx\n", ctxt, rcvctrl);
12180 write_kctxt_csr(dd, ctxt, RCV_CTXT_CTRL, rcvctrl);
12182 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
12184 (rcvctrl & RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK)) {
12185 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
12187 dd_dev_info(dd, "ctxt %d status %lld (blocked)\n",
12189 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
12190 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x10);
12191 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, 0x00);
12192 read_uctxt_csr(dd, ctxt, RCV_HDR_HEAD);
12193 reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS);
12194 dd_dev_info(dd, "ctxt %d status %lld (%s blocked)\n",
12195 ctxt, reg, reg == 0 ? "not" : "still");
12201 * The interrupt timeout and count must be set after
12202 * the context is enabled to take effect.
12204 /* set interrupt timeout */
12205 write_kctxt_csr(dd, ctxt, RCV_AVAIL_TIME_OUT,
12206 (u64)rcd->rcvavail_timeout <<
12207 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
12209 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
12210 reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT;
12211 write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg);
12214 if (op & (HFI1_RCVCTRL_TAILUPD_DIS | HFI1_RCVCTRL_CTXT_DIS))
12216 * If the context has been disabled and the Tail Update has
12217 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
12218 * so it doesn't contain an address that is invalid.
12220 write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,
12221 dd->rcvhdrtail_dummy_dma);
12224 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp)
12230 ret = dd->cntrnameslen;
12231 *namep = dd->cntrnames;
12233 const struct cntr_entry *entry;
12236 ret = (dd->ndevcntrs) * sizeof(u64);
12238 /* Get the start of the block of counters */
12239 *cntrp = dd->cntrs;
12242 * Now go and fill in each counter in the block.
12244 for (i = 0; i < DEV_CNTR_LAST; i++) {
12245 entry = &dev_cntrs[i];
12246 hfi1_cdbg(CNTR, "reading %s", entry->name);
12247 if (entry->flags & CNTR_DISABLED) {
12249 hfi1_cdbg(CNTR, "\tDisabled\n");
12251 if (entry->flags & CNTR_VL) {
12252 hfi1_cdbg(CNTR, "\tPer VL\n");
12253 for (j = 0; j < C_VL_COUNT; j++) {
12254 val = entry->rw_cntr(entry,
12260 "\t\tRead 0x%llx for %d\n",
12262 dd->cntrs[entry->offset + j] =
12265 } else if (entry->flags & CNTR_SDMA) {
12267 "\t Per SDMA Engine\n");
12268 for (j = 0; j < chip_sdma_engines(dd);
12271 entry->rw_cntr(entry, dd, j,
12274 "\t\tRead 0x%llx for %d\n",
12276 dd->cntrs[entry->offset + j] =
12280 val = entry->rw_cntr(entry, dd,
12283 dd->cntrs[entry->offset] = val;
12284 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
12293 * Used by sysfs to create files for hfi stats to read
12295 u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp)
12301 ret = ppd->dd->portcntrnameslen;
12302 *namep = ppd->dd->portcntrnames;
12304 const struct cntr_entry *entry;
12307 ret = ppd->dd->nportcntrs * sizeof(u64);
12308 *cntrp = ppd->cntrs;
12310 for (i = 0; i < PORT_CNTR_LAST; i++) {
12311 entry = &port_cntrs[i];
12312 hfi1_cdbg(CNTR, "reading %s", entry->name);
12313 if (entry->flags & CNTR_DISABLED) {
12315 hfi1_cdbg(CNTR, "\tDisabled\n");
12319 if (entry->flags & CNTR_VL) {
12320 hfi1_cdbg(CNTR, "\tPer VL");
12321 for (j = 0; j < C_VL_COUNT; j++) {
12322 val = entry->rw_cntr(entry, ppd, j,
12327 "\t\tRead 0x%llx for %d",
12329 ppd->cntrs[entry->offset + j] = val;
12332 val = entry->rw_cntr(entry, ppd,
12336 ppd->cntrs[entry->offset] = val;
12337 hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
12344 static void free_cntrs(struct hfi1_devdata *dd)
12346 struct hfi1_pportdata *ppd;
12349 if (dd->synth_stats_timer.function)
12350 del_timer_sync(&dd->synth_stats_timer);
12351 cancel_work_sync(&dd->update_cntr_work);
12352 ppd = (struct hfi1_pportdata *)(dd + 1);
12353 for (i = 0; i < dd->num_pports; i++, ppd++) {
12355 kfree(ppd->scntrs);
12356 free_percpu(ppd->ibport_data.rvp.rc_acks);
12357 free_percpu(ppd->ibport_data.rvp.rc_qacks);
12358 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
12360 ppd->scntrs = NULL;
12361 ppd->ibport_data.rvp.rc_acks = NULL;
12362 ppd->ibport_data.rvp.rc_qacks = NULL;
12363 ppd->ibport_data.rvp.rc_delayed_comp = NULL;
12365 kfree(dd->portcntrnames);
12366 dd->portcntrnames = NULL;
12371 kfree(dd->cntrnames);
12372 dd->cntrnames = NULL;
12373 if (dd->update_cntr_wq) {
12374 destroy_workqueue(dd->update_cntr_wq);
12375 dd->update_cntr_wq = NULL;
12379 static u64 read_dev_port_cntr(struct hfi1_devdata *dd, struct cntr_entry *entry,
12380 u64 *psval, void *context, int vl)
12385 if (entry->flags & CNTR_DISABLED) {
12386 dd_dev_err(dd, "Counter %s not enabled", entry->name);
12390 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
12392 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_R, 0);
12394 /* If its a synthetic counter there is more work we need to do */
12395 if (entry->flags & CNTR_SYNTH) {
12396 if (sval == CNTR_MAX) {
12397 /* No need to read already saturated */
12401 if (entry->flags & CNTR_32BIT) {
12402 /* 32bit counters can wrap multiple times */
12403 u64 upper = sval >> 32;
12404 u64 lower = (sval << 32) >> 32;
12406 if (lower > val) { /* hw wrapped */
12407 if (upper == CNTR_32BIT_MAX)
12413 if (val != CNTR_MAX)
12414 val = (upper << 32) | val;
12417 /* If we rolled we are saturated */
12418 if ((val < sval) || (val > CNTR_MAX))
12425 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12430 static u64 write_dev_port_cntr(struct hfi1_devdata *dd,
12431 struct cntr_entry *entry,
12432 u64 *psval, void *context, int vl, u64 data)
12436 if (entry->flags & CNTR_DISABLED) {
12437 dd_dev_err(dd, "Counter %s not enabled", entry->name);
12441 hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
12443 if (entry->flags & CNTR_SYNTH) {
12445 if (entry->flags & CNTR_32BIT) {
12446 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12447 (data << 32) >> 32);
12448 val = data; /* return the full 64bit value */
12450 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W,
12454 val = entry->rw_cntr(entry, context, vl, CNTR_MODE_W, data);
12459 hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
12464 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl)
12466 struct cntr_entry *entry;
12469 entry = &dev_cntrs[index];
12470 sval = dd->scntrs + entry->offset;
12472 if (vl != CNTR_INVALID_VL)
12475 return read_dev_port_cntr(dd, entry, sval, dd, vl);
12478 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data)
12480 struct cntr_entry *entry;
12483 entry = &dev_cntrs[index];
12484 sval = dd->scntrs + entry->offset;
12486 if (vl != CNTR_INVALID_VL)
12489 return write_dev_port_cntr(dd, entry, sval, dd, vl, data);
12492 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl)
12494 struct cntr_entry *entry;
12497 entry = &port_cntrs[index];
12498 sval = ppd->scntrs + entry->offset;
12500 if (vl != CNTR_INVALID_VL)
12503 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12504 (index <= C_RCV_HDR_OVF_LAST)) {
12505 /* We do not want to bother for disabled contexts */
12509 return read_dev_port_cntr(ppd->dd, entry, sval, ppd, vl);
12512 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data)
12514 struct cntr_entry *entry;
12517 entry = &port_cntrs[index];
12518 sval = ppd->scntrs + entry->offset;
12520 if (vl != CNTR_INVALID_VL)
12523 if ((index >= C_RCV_HDR_OVF_FIRST + ppd->dd->num_rcv_contexts) &&
12524 (index <= C_RCV_HDR_OVF_LAST)) {
12525 /* We do not want to bother for disabled contexts */
12529 return write_dev_port_cntr(ppd->dd, entry, sval, ppd, vl, data);
12532 static void do_update_synth_timer(struct work_struct *work)
12539 struct hfi1_pportdata *ppd;
12540 struct cntr_entry *entry;
12541 struct hfi1_devdata *dd = container_of(work, struct hfi1_devdata,
12545 * Rather than keep beating on the CSRs pick a minimal set that we can
12546 * check to watch for potential roll over. We can do this by looking at
12547 * the number of flits sent/recv. If the total flits exceeds 32bits then
12548 * we have to iterate all the counters and update.
12550 entry = &dev_cntrs[C_DC_RCV_FLITS];
12551 cur_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12553 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12554 cur_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL, CNTR_MODE_R, 0);
12558 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
12559 dd->unit, cur_tx, cur_rx, dd->last_tx, dd->last_rx);
12561 if ((cur_tx < dd->last_tx) || (cur_rx < dd->last_rx)) {
12563 * May not be strictly necessary to update but it won't hurt and
12564 * simplifies the logic here.
12567 hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
12570 total_flits = (cur_tx - dd->last_tx) + (cur_rx - dd->last_rx);
12572 "[%d] total flits 0x%llx limit 0x%llx\n", dd->unit,
12573 total_flits, (u64)CNTR_32BIT_MAX);
12574 if (total_flits >= CNTR_32BIT_MAX) {
12575 hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
12582 hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
12583 for (i = 0; i < DEV_CNTR_LAST; i++) {
12584 entry = &dev_cntrs[i];
12585 if (entry->flags & CNTR_VL) {
12586 for (vl = 0; vl < C_VL_COUNT; vl++)
12587 read_dev_cntr(dd, i, vl);
12589 read_dev_cntr(dd, i, CNTR_INVALID_VL);
12592 ppd = (struct hfi1_pportdata *)(dd + 1);
12593 for (i = 0; i < dd->num_pports; i++, ppd++) {
12594 for (j = 0; j < PORT_CNTR_LAST; j++) {
12595 entry = &port_cntrs[j];
12596 if (entry->flags & CNTR_VL) {
12597 for (vl = 0; vl < C_VL_COUNT; vl++)
12598 read_port_cntr(ppd, j, vl);
12600 read_port_cntr(ppd, j, CNTR_INVALID_VL);
12606 * We want the value in the register. The goal is to keep track
12607 * of the number of "ticks" not the counter value. In other
12608 * words if the register rolls we want to notice it and go ahead
12609 * and force an update.
12611 entry = &dev_cntrs[C_DC_XMIT_FLITS];
12612 dd->last_tx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12615 entry = &dev_cntrs[C_DC_RCV_FLITS];
12616 dd->last_rx = entry->rw_cntr(entry, dd, CNTR_INVALID_VL,
12619 hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
12620 dd->unit, dd->last_tx, dd->last_rx);
12623 hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
12627 static void update_synth_timer(struct timer_list *t)
12629 struct hfi1_devdata *dd = from_timer(dd, t, synth_stats_timer);
12631 queue_work(dd->update_cntr_wq, &dd->update_cntr_work);
12632 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12635 #define C_MAX_NAME 16 /* 15 chars + one for /0 */
12636 static int init_cntrs(struct hfi1_devdata *dd)
12638 int i, rcv_ctxts, j;
12641 char name[C_MAX_NAME];
12642 struct hfi1_pportdata *ppd;
12643 const char *bit_type_32 = ",32";
12644 const int bit_type_32_sz = strlen(bit_type_32);
12645 u32 sdma_engines = chip_sdma_engines(dd);
12647 /* set up the stats timer; the add_timer is done at the end */
12648 timer_setup(&dd->synth_stats_timer, update_synth_timer, 0);
12650 /***********************/
12651 /* per device counters */
12652 /***********************/
12654 /* size names and determine how many we have*/
12658 for (i = 0; i < DEV_CNTR_LAST; i++) {
12659 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12660 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs[i].name);
12664 if (dev_cntrs[i].flags & CNTR_VL) {
12665 dev_cntrs[i].offset = dd->ndevcntrs;
12666 for (j = 0; j < C_VL_COUNT; j++) {
12667 snprintf(name, C_MAX_NAME, "%s%d",
12668 dev_cntrs[i].name, vl_from_idx(j));
12669 sz += strlen(name);
12670 /* Add ",32" for 32-bit counters */
12671 if (dev_cntrs[i].flags & CNTR_32BIT)
12672 sz += bit_type_32_sz;
12676 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12677 dev_cntrs[i].offset = dd->ndevcntrs;
12678 for (j = 0; j < sdma_engines; j++) {
12679 snprintf(name, C_MAX_NAME, "%s%d",
12680 dev_cntrs[i].name, j);
12681 sz += strlen(name);
12682 /* Add ",32" for 32-bit counters */
12683 if (dev_cntrs[i].flags & CNTR_32BIT)
12684 sz += bit_type_32_sz;
12689 /* +1 for newline. */
12690 sz += strlen(dev_cntrs[i].name) + 1;
12691 /* Add ",32" for 32-bit counters */
12692 if (dev_cntrs[i].flags & CNTR_32BIT)
12693 sz += bit_type_32_sz;
12694 dev_cntrs[i].offset = dd->ndevcntrs;
12699 /* allocate space for the counter values */
12700 dd->cntrs = kcalloc(dd->ndevcntrs + num_driver_cntrs, sizeof(u64),
12705 dd->scntrs = kcalloc(dd->ndevcntrs, sizeof(u64), GFP_KERNEL);
12709 /* allocate space for the counter names */
12710 dd->cntrnameslen = sz;
12711 dd->cntrnames = kmalloc(sz, GFP_KERNEL);
12712 if (!dd->cntrnames)
12715 /* fill in the names */
12716 for (p = dd->cntrnames, i = 0; i < DEV_CNTR_LAST; i++) {
12717 if (dev_cntrs[i].flags & CNTR_DISABLED) {
12719 } else if (dev_cntrs[i].flags & CNTR_VL) {
12720 for (j = 0; j < C_VL_COUNT; j++) {
12721 snprintf(name, C_MAX_NAME, "%s%d",
12724 memcpy(p, name, strlen(name));
12727 /* Counter is 32 bits */
12728 if (dev_cntrs[i].flags & CNTR_32BIT) {
12729 memcpy(p, bit_type_32, bit_type_32_sz);
12730 p += bit_type_32_sz;
12735 } else if (dev_cntrs[i].flags & CNTR_SDMA) {
12736 for (j = 0; j < sdma_engines; j++) {
12737 snprintf(name, C_MAX_NAME, "%s%d",
12738 dev_cntrs[i].name, j);
12739 memcpy(p, name, strlen(name));
12742 /* Counter is 32 bits */
12743 if (dev_cntrs[i].flags & CNTR_32BIT) {
12744 memcpy(p, bit_type_32, bit_type_32_sz);
12745 p += bit_type_32_sz;
12751 memcpy(p, dev_cntrs[i].name, strlen(dev_cntrs[i].name));
12752 p += strlen(dev_cntrs[i].name);
12754 /* Counter is 32 bits */
12755 if (dev_cntrs[i].flags & CNTR_32BIT) {
12756 memcpy(p, bit_type_32, bit_type_32_sz);
12757 p += bit_type_32_sz;
12764 /*********************/
12765 /* per port counters */
12766 /*********************/
12769 * Go through the counters for the overflows and disable the ones we
12770 * don't need. This varies based on platform so we need to do it
12771 * dynamically here.
12773 rcv_ctxts = dd->num_rcv_contexts;
12774 for (i = C_RCV_HDR_OVF_FIRST + rcv_ctxts;
12775 i <= C_RCV_HDR_OVF_LAST; i++) {
12776 port_cntrs[i].flags |= CNTR_DISABLED;
12779 /* size port counter names and determine how many we have*/
12781 dd->nportcntrs = 0;
12782 for (i = 0; i < PORT_CNTR_LAST; i++) {
12783 if (port_cntrs[i].flags & CNTR_DISABLED) {
12784 hfi1_dbg_early("\tSkipping %s\n", port_cntrs[i].name);
12788 if (port_cntrs[i].flags & CNTR_VL) {
12789 port_cntrs[i].offset = dd->nportcntrs;
12790 for (j = 0; j < C_VL_COUNT; j++) {
12791 snprintf(name, C_MAX_NAME, "%s%d",
12792 port_cntrs[i].name, vl_from_idx(j));
12793 sz += strlen(name);
12794 /* Add ",32" for 32-bit counters */
12795 if (port_cntrs[i].flags & CNTR_32BIT)
12796 sz += bit_type_32_sz;
12801 /* +1 for newline */
12802 sz += strlen(port_cntrs[i].name) + 1;
12803 /* Add ",32" for 32-bit counters */
12804 if (port_cntrs[i].flags & CNTR_32BIT)
12805 sz += bit_type_32_sz;
12806 port_cntrs[i].offset = dd->nportcntrs;
12811 /* allocate space for the counter names */
12812 dd->portcntrnameslen = sz;
12813 dd->portcntrnames = kmalloc(sz, GFP_KERNEL);
12814 if (!dd->portcntrnames)
12817 /* fill in port cntr names */
12818 for (p = dd->portcntrnames, i = 0; i < PORT_CNTR_LAST; i++) {
12819 if (port_cntrs[i].flags & CNTR_DISABLED)
12822 if (port_cntrs[i].flags & CNTR_VL) {
12823 for (j = 0; j < C_VL_COUNT; j++) {
12824 snprintf(name, C_MAX_NAME, "%s%d",
12825 port_cntrs[i].name, vl_from_idx(j));
12826 memcpy(p, name, strlen(name));
12829 /* Counter is 32 bits */
12830 if (port_cntrs[i].flags & CNTR_32BIT) {
12831 memcpy(p, bit_type_32, bit_type_32_sz);
12832 p += bit_type_32_sz;
12838 memcpy(p, port_cntrs[i].name,
12839 strlen(port_cntrs[i].name));
12840 p += strlen(port_cntrs[i].name);
12842 /* Counter is 32 bits */
12843 if (port_cntrs[i].flags & CNTR_32BIT) {
12844 memcpy(p, bit_type_32, bit_type_32_sz);
12845 p += bit_type_32_sz;
12852 /* allocate per port storage for counter values */
12853 ppd = (struct hfi1_pportdata *)(dd + 1);
12854 for (i = 0; i < dd->num_pports; i++, ppd++) {
12855 ppd->cntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12859 ppd->scntrs = kcalloc(dd->nportcntrs, sizeof(u64), GFP_KERNEL);
12864 /* CPU counters need to be allocated and zeroed */
12865 if (init_cpu_counters(dd))
12868 dd->update_cntr_wq = alloc_ordered_workqueue("hfi1_update_cntr_%d",
12869 WQ_MEM_RECLAIM, dd->unit);
12870 if (!dd->update_cntr_wq)
12873 INIT_WORK(&dd->update_cntr_work, do_update_synth_timer);
12875 mod_timer(&dd->synth_stats_timer, jiffies + HZ * SYNTH_CNT_TIME);
12882 static u32 chip_to_opa_lstate(struct hfi1_devdata *dd, u32 chip_lstate)
12884 switch (chip_lstate) {
12886 return IB_PORT_DOWN;
12888 return IB_PORT_INIT;
12890 return IB_PORT_ARMED;
12891 case LSTATE_ACTIVE:
12892 return IB_PORT_ACTIVE;
12895 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12897 return IB_PORT_DOWN;
12901 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate)
12903 /* look at the HFI meta-states only */
12904 switch (chip_pstate & 0xf0) {
12906 return IB_PORTPHYSSTATE_DISABLED;
12908 return OPA_PORTPHYSSTATE_OFFLINE;
12910 return IB_PORTPHYSSTATE_POLLING;
12911 case PLS_CONFIGPHY:
12912 return IB_PORTPHYSSTATE_TRAINING;
12914 return IB_PORTPHYSSTATE_LINKUP;
12916 return IB_PORTPHYSSTATE_PHY_TEST;
12918 dd_dev_err(dd, "Unexpected chip physical state of 0x%x\n",
12920 return IB_PORTPHYSSTATE_DISABLED;
12924 /* return the OPA port logical state name */
12925 const char *opa_lstate_name(u32 lstate)
12927 static const char * const port_logical_names[] = {
12933 "PORT_ACTIVE_DEFER",
12935 if (lstate < ARRAY_SIZE(port_logical_names))
12936 return port_logical_names[lstate];
12940 /* return the OPA port physical state name */
12941 const char *opa_pstate_name(u32 pstate)
12943 static const char * const port_physical_names[] = {
12950 "PHYS_LINK_ERR_RECOVER",
12957 if (pstate < ARRAY_SIZE(port_physical_names))
12958 return port_physical_names[pstate];
12963 * update_statusp - Update userspace status flag
12964 * @ppd: Port data structure
12965 * @state: port state information
12967 * Actual port status is determined by the host_link_state value
12970 * host_link_state MUST be updated before updating the user space
12973 static void update_statusp(struct hfi1_pportdata *ppd, u32 state)
12976 * Set port status flags in the page mapped into userspace
12977 * memory. Do it here to ensure a reliable state - this is
12978 * the only function called by all state handling code.
12979 * Always set the flags due to the fact that the cache value
12980 * might have been changed explicitly outside of this
12983 if (ppd->statusp) {
12987 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
12988 HFI1_STATUS_IB_READY);
12990 case IB_PORT_ARMED:
12991 *ppd->statusp |= HFI1_STATUS_IB_CONF;
12993 case IB_PORT_ACTIVE:
12994 *ppd->statusp |= HFI1_STATUS_IB_READY;
12998 dd_dev_info(ppd->dd, "logical state changed to %s (0x%x)\n",
12999 opa_lstate_name(state), state);
13003 * wait_logical_linkstate - wait for an IB link state change to occur
13004 * @ppd: port device
13005 * @state: the state to wait for
13006 * @msecs: the number of milliseconds to wait
13008 * Wait up to msecs milliseconds for IB link state change to occur.
13009 * For now, take the easy polling route.
13010 * Returns 0 if state reached, otherwise -ETIMEDOUT.
13012 static int wait_logical_linkstate(struct hfi1_pportdata *ppd, u32 state,
13015 unsigned long timeout;
13018 timeout = jiffies + msecs_to_jiffies(msecs);
13020 new_state = chip_to_opa_lstate(ppd->dd,
13021 read_logical_state(ppd->dd));
13022 if (new_state == state)
13024 if (time_after(jiffies, timeout)) {
13025 dd_dev_err(ppd->dd,
13026 "timeout waiting for link state 0x%x\n",
13036 static void log_state_transition(struct hfi1_pportdata *ppd, u32 state)
13038 u32 ib_pstate = chip_to_opa_pstate(ppd->dd, state);
13040 dd_dev_info(ppd->dd,
13041 "physical state changed to %s (0x%x), phy 0x%x\n",
13042 opa_pstate_name(ib_pstate), ib_pstate, state);
13046 * Read the physical hardware link state and check if it matches host
13047 * drivers anticipated state.
13049 static void log_physical_state(struct hfi1_pportdata *ppd, u32 state)
13051 u32 read_state = read_physical_state(ppd->dd);
13053 if (read_state == state) {
13054 log_state_transition(ppd, state);
13056 dd_dev_err(ppd->dd,
13057 "anticipated phy link state 0x%x, read 0x%x\n",
13058 state, read_state);
13063 * wait_physical_linkstate - wait for an physical link state change to occur
13064 * @ppd: port device
13065 * @state: the state to wait for
13066 * @msecs: the number of milliseconds to wait
13068 * Wait up to msecs milliseconds for physical link state change to occur.
13069 * Returns 0 if state reached, otherwise -ETIMEDOUT.
13071 static int wait_physical_linkstate(struct hfi1_pportdata *ppd, u32 state,
13075 unsigned long timeout;
13077 timeout = jiffies + msecs_to_jiffies(msecs);
13079 read_state = read_physical_state(ppd->dd);
13080 if (read_state == state)
13082 if (time_after(jiffies, timeout)) {
13083 dd_dev_err(ppd->dd,
13084 "timeout waiting for phy link state 0x%x\n",
13088 usleep_range(1950, 2050); /* sleep 2ms-ish */
13091 log_state_transition(ppd, state);
13096 * wait_phys_link_offline_quiet_substates - wait for any offline substate
13097 * @ppd: port device
13098 * @msecs: the number of milliseconds to wait
13100 * Wait up to msecs milliseconds for any offline physical link
13101 * state change to occur.
13102 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
13104 static int wait_phys_link_offline_substates(struct hfi1_pportdata *ppd,
13108 unsigned long timeout;
13110 timeout = jiffies + msecs_to_jiffies(msecs);
13112 read_state = read_physical_state(ppd->dd);
13113 if ((read_state & 0xF0) == PLS_OFFLINE)
13115 if (time_after(jiffies, timeout)) {
13116 dd_dev_err(ppd->dd,
13117 "timeout waiting for phy link offline.quiet substates. Read state 0x%x, %dms\n",
13118 read_state, msecs);
13121 usleep_range(1950, 2050); /* sleep 2ms-ish */
13124 log_state_transition(ppd, read_state);
13129 * wait_phys_link_out_of_offline - wait for any out of offline state
13130 * @ppd: port device
13131 * @msecs: the number of milliseconds to wait
13133 * Wait up to msecs milliseconds for any out of offline physical link
13134 * state change to occur.
13135 * Returns 0 if at least one state is reached, otherwise -ETIMEDOUT.
13137 static int wait_phys_link_out_of_offline(struct hfi1_pportdata *ppd,
13141 unsigned long timeout;
13143 timeout = jiffies + msecs_to_jiffies(msecs);
13145 read_state = read_physical_state(ppd->dd);
13146 if ((read_state & 0xF0) != PLS_OFFLINE)
13148 if (time_after(jiffies, timeout)) {
13149 dd_dev_err(ppd->dd,
13150 "timeout waiting for phy link out of offline. Read state 0x%x, %dms\n",
13151 read_state, msecs);
13154 usleep_range(1950, 2050); /* sleep 2ms-ish */
13157 log_state_transition(ppd, read_state);
13161 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
13162 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
13164 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
13165 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
13167 void hfi1_init_ctxt(struct send_context *sc)
13170 struct hfi1_devdata *dd = sc->dd;
13172 u8 set = (sc->type == SC_USER ?
13173 HFI1_CAP_IS_USET(STATIC_RATE_CTRL) :
13174 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL));
13175 reg = read_kctxt_csr(dd, sc->hw_context,
13176 SEND_CTXT_CHECK_ENABLE);
13178 CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
13180 SET_STATIC_RATE_CONTROL_SMASK(reg);
13181 write_kctxt_csr(dd, sc->hw_context,
13182 SEND_CTXT_CHECK_ENABLE, reg);
13186 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
13191 if (dd->icode != ICODE_RTL_SILICON) {
13192 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL))
13193 dd_dev_info(dd, "%s: tempsense not supported by HW\n",
13197 reg = read_csr(dd, ASIC_STS_THERM);
13198 temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) &
13199 ASIC_STS_THERM_CURR_TEMP_MASK);
13200 temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) &
13201 ASIC_STS_THERM_LO_TEMP_MASK);
13202 temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) &
13203 ASIC_STS_THERM_HI_TEMP_MASK);
13204 temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) &
13205 ASIC_STS_THERM_CRIT_TEMP_MASK);
13206 /* triggers is a 3-bit value - 1 bit per trigger. */
13207 temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7);
13212 /* ========================================================================= */
13215 * read_mod_write() - Calculate the IRQ register index and set/clear the bits
13216 * @dd: valid devdata
13217 * @src: IRQ source to determine register index from
13218 * @bits: the bits to set or clear
13219 * @set: true == set the bits, false == clear the bits
13222 static void read_mod_write(struct hfi1_devdata *dd, u16 src, u64 bits,
13226 u16 idx = src / BITS_PER_REGISTER;
13228 spin_lock(&dd->irq_src_lock);
13229 reg = read_csr(dd, CCE_INT_MASK + (8 * idx));
13234 write_csr(dd, CCE_INT_MASK + (8 * idx), reg);
13235 spin_unlock(&dd->irq_src_lock);
13239 * set_intr_bits() - Enable/disable a range (one or more) IRQ sources
13240 * @dd: valid devdata
13241 * @first: first IRQ source to set/clear
13242 * @last: last IRQ source (inclusive) to set/clear
13243 * @set: true == set the bits, false == clear the bits
13245 * If first == last, set the exact source.
13247 int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set)
13253 if (first > NUM_INTERRUPT_SOURCES || last > NUM_INTERRUPT_SOURCES)
13259 for (src = first; src <= last; src++) {
13260 bit = src % BITS_PER_REGISTER;
13261 /* wrapped to next register? */
13262 if (!bit && bits) {
13263 read_mod_write(dd, src - 1, bits, set);
13266 bits |= BIT_ULL(bit);
13268 read_mod_write(dd, last, bits, set);
13274 * Clear all interrupt sources on the chip.
13276 void clear_all_interrupts(struct hfi1_devdata *dd)
13280 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
13281 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0);
13283 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0);
13284 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0);
13285 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0);
13286 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0);
13287 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0);
13288 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0);
13289 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0);
13290 for (i = 0; i < chip_send_contexts(dd); i++)
13291 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~(u64)0);
13292 for (i = 0; i < chip_sdma_engines(dd); i++)
13293 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~(u64)0);
13295 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0);
13296 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0);
13297 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0);
13301 * Remap the interrupt source from the general handler to the given MSI-X
13304 void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr)
13309 /* clear from the handled mask of the general interrupt */
13312 if (likely(m < CCE_NUM_INT_CSRS)) {
13313 dd->gi_mask[m] &= ~((u64)1 << n);
13315 dd_dev_err(dd, "remap interrupt err\n");
13319 /* direct the chip source to the given MSI-X interrupt */
13322 reg = read_csr(dd, CCE_INT_MAP + (8 * m));
13323 reg &= ~((u64)0xff << (8 * n));
13324 reg |= ((u64)msix_intr & 0xff) << (8 * n);
13325 write_csr(dd, CCE_INT_MAP + (8 * m), reg);
13328 void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr)
13331 * SDMA engine interrupt sources grouped by type, rather than
13332 * engine. Per-engine interrupts are as follows:
13337 remap_intr(dd, IS_SDMA_START + engine, msix_intr);
13338 remap_intr(dd, IS_SDMA_PROGRESS_START + engine, msix_intr);
13339 remap_intr(dd, IS_SDMA_IDLE_START + engine, msix_intr);
13343 * Set the general handler to accept all interrupts, remap all
13344 * chip interrupts back to MSI-X 0.
13346 void reset_interrupts(struct hfi1_devdata *dd)
13350 /* all interrupts handled by the general handler */
13351 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
13352 dd->gi_mask[i] = ~(u64)0;
13354 /* all chip interrupts map to MSI-X 0 */
13355 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13356 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13360 * set_up_interrupts() - Initialize the IRQ resources and state
13361 * @dd: valid devdata
13364 static int set_up_interrupts(struct hfi1_devdata *dd)
13368 /* mask all interrupts */
13369 set_intr_bits(dd, IS_FIRST_SOURCE, IS_LAST_SOURCE, false);
13371 /* clear all pending interrupts */
13372 clear_all_interrupts(dd);
13374 /* reset general handler mask, chip MSI-X mappings */
13375 reset_interrupts(dd);
13377 /* ask for MSI-X interrupts */
13378 ret = msix_initialize(dd);
13382 ret = msix_request_irqs(dd);
13384 msix_clean_up_interrupts(dd);
13390 * Set up context values in dd. Sets:
13392 * num_rcv_contexts - number of contexts being used
13393 * n_krcv_queues - number of kernel contexts
13394 * first_dyn_alloc_ctxt - first dynamically allocated context
13395 * in array of contexts
13396 * freectxts - number of free user contexts
13397 * num_send_contexts - number of PIO send contexts being used
13398 * num_netdev_contexts - number of contexts reserved for netdev
13400 static int set_up_context_variables(struct hfi1_devdata *dd)
13402 unsigned long num_kernel_contexts;
13403 u16 num_netdev_contexts;
13408 u32 send_contexts = chip_send_contexts(dd);
13409 u32 rcv_contexts = chip_rcv_contexts(dd);
13412 * Kernel receive contexts:
13413 * - Context 0 - control context (VL15/multicast/error)
13414 * - Context 1 - first kernel context
13415 * - Context 2 - second kernel context
13420 * n_krcvqs is the sum of module parameter kernel receive
13421 * contexts, krcvqs[]. It does not include the control
13422 * context, so add that.
13424 num_kernel_contexts = n_krcvqs + 1;
13426 num_kernel_contexts = DEFAULT_KRCVQS + 1;
13428 * Every kernel receive context needs an ACK send context.
13429 * one send context is allocated for each VL{0-7} and VL15
13431 if (num_kernel_contexts > (send_contexts - num_vls - 1)) {
13433 "Reducing # kernel rcv contexts to: %d, from %lu\n",
13434 send_contexts - num_vls - 1,
13435 num_kernel_contexts);
13436 num_kernel_contexts = send_contexts - num_vls - 1;
13441 * - default to 1 user context per real (non-HT) CPU core if
13442 * num_user_contexts is negative
13444 if (num_user_contexts < 0)
13445 n_usr_ctxts = cpumask_weight(&node_affinity.real_cpu_mask);
13447 n_usr_ctxts = num_user_contexts;
13449 * Adjust the counts given a global max.
13451 if (num_kernel_contexts + n_usr_ctxts > rcv_contexts) {
13453 "Reducing # user receive contexts to: %u, from %u\n",
13454 (u32)(rcv_contexts - num_kernel_contexts),
13457 n_usr_ctxts = rcv_contexts - num_kernel_contexts;
13460 num_netdev_contexts =
13461 hfi1_num_netdev_contexts(dd, rcv_contexts -
13462 (num_kernel_contexts + n_usr_ctxts),
13463 &node_affinity.real_cpu_mask);
13465 * RMT entries are allocated as follows:
13466 * 1. QOS (0 to 128 entries)
13467 * 2. FECN (num_kernel_context - 1 [a] + num_user_contexts +
13468 * num_netdev_contexts [b])
13469 * 3. netdev (NUM_NETDEV_MAP_ENTRIES)
13472 * [a] Kernel contexts (except control) are included in FECN if kernel
13473 * TID_RDMA is active.
13474 * [b] Netdev and user contexts are randomly allocated from the same
13475 * context pool, so FECN must cover all contexts in the pool.
13477 rmt_count = qos_rmt_entries(num_kernel_contexts - 1, NULL, NULL)
13478 + (HFI1_CAP_IS_KSET(TID_RDMA) ? num_kernel_contexts - 1
13481 + num_netdev_contexts
13482 + NUM_NETDEV_MAP_ENTRIES;
13483 if (rmt_count > NUM_MAP_ENTRIES) {
13484 int over = rmt_count - NUM_MAP_ENTRIES;
13485 /* try to squish user contexts, minimum of 1 */
13486 if (over >= n_usr_ctxts) {
13487 dd_dev_err(dd, "RMT overflow: reduce the requested number of contexts\n");
13490 dd_dev_err(dd, "RMT overflow: reducing # user contexts from %u to %u\n",
13491 n_usr_ctxts, n_usr_ctxts - over);
13492 n_usr_ctxts -= over;
13495 /* the first N are kernel contexts, the rest are user/netdev contexts */
13496 dd->num_rcv_contexts =
13497 num_kernel_contexts + n_usr_ctxts + num_netdev_contexts;
13498 dd->n_krcv_queues = num_kernel_contexts;
13499 dd->first_dyn_alloc_ctxt = num_kernel_contexts;
13500 dd->num_netdev_contexts = num_netdev_contexts;
13501 dd->num_user_contexts = n_usr_ctxts;
13502 dd->freectxts = n_usr_ctxts;
13504 "rcv contexts: chip %d, used %d (kernel %d, netdev %u, user %u)\n",
13506 (int)dd->num_rcv_contexts,
13507 (int)dd->n_krcv_queues,
13508 dd->num_netdev_contexts,
13509 dd->num_user_contexts);
13512 * Receive array allocation:
13513 * All RcvArray entries are divided into groups of 8. This
13514 * is required by the hardware and will speed up writes to
13515 * consecutive entries by using write-combining of the entire
13518 * The number of groups are evenly divided among all contexts.
13519 * any left over groups will be given to the first N user
13522 dd->rcv_entries.group_size = RCV_INCREMENT;
13523 ngroups = chip_rcv_array_count(dd) / dd->rcv_entries.group_size;
13524 dd->rcv_entries.ngroups = ngroups / dd->num_rcv_contexts;
13525 dd->rcv_entries.nctxt_extra = ngroups -
13526 (dd->num_rcv_contexts * dd->rcv_entries.ngroups);
13527 dd_dev_info(dd, "RcvArray groups %u, ctxts extra %u\n",
13528 dd->rcv_entries.ngroups,
13529 dd->rcv_entries.nctxt_extra);
13530 if (dd->rcv_entries.ngroups * dd->rcv_entries.group_size >
13531 MAX_EAGER_ENTRIES * 2) {
13532 dd->rcv_entries.ngroups = (MAX_EAGER_ENTRIES * 2) /
13533 dd->rcv_entries.group_size;
13535 "RcvArray group count too high, change to %u\n",
13536 dd->rcv_entries.ngroups);
13537 dd->rcv_entries.nctxt_extra = 0;
13540 * PIO send contexts
13542 ret = init_sc_pools_and_sizes(dd);
13543 if (ret >= 0) { /* success */
13544 dd->num_send_contexts = ret;
13547 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
13549 dd->num_send_contexts,
13550 dd->sc_sizes[SC_KERNEL].count,
13551 dd->sc_sizes[SC_ACK].count,
13552 dd->sc_sizes[SC_USER].count,
13553 dd->sc_sizes[SC_VL15].count);
13554 ret = 0; /* success */
13561 * Set the device/port partition key table. The MAD code
13562 * will ensure that, at least, the partial management
13563 * partition key is present in the table.
13565 static void set_partition_keys(struct hfi1_pportdata *ppd)
13567 struct hfi1_devdata *dd = ppd->dd;
13571 dd_dev_info(dd, "Setting partition keys\n");
13572 for (i = 0; i < hfi1_get_npkeys(dd); i++) {
13573 reg |= (ppd->pkeys[i] &
13574 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK) <<
13576 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT);
13577 /* Each register holds 4 PKey values. */
13578 if ((i % 4) == 3) {
13579 write_csr(dd, RCV_PARTITION_KEY +
13580 ((i - 3) * 2), reg);
13585 /* Always enable HW pkeys check when pkeys table is set */
13586 add_rcvctrl(dd, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK);
13590 * These CSRs and memories are uninitialized on reset and must be
13591 * written before reading to set the ECC/parity bits.
13593 * NOTE: All user context CSRs that are not mmaped write-only
13594 * (e.g. the TID flows) must be initialized even if the driver never
13597 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
13602 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13603 write_csr(dd, CCE_INT_MAP + (8 * i), 0);
13605 /* SendCtxtCreditReturnAddr */
13606 for (i = 0; i < chip_send_contexts(dd); i++)
13607 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13609 /* PIO Send buffers */
13610 /* SDMA Send buffers */
13612 * These are not normally read, and (presently) have no method
13613 * to be read, so are not pre-initialized
13617 /* RcvHdrTailAddr */
13618 /* RcvTidFlowTable */
13619 for (i = 0; i < chip_rcv_contexts(dd); i++) {
13620 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13621 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13622 for (j = 0; j < RXE_NUM_TID_FLOWS; j++)
13623 write_uctxt_csr(dd, i, RCV_TID_FLOW_TABLE + (8 * j), 0);
13627 for (i = 0; i < chip_rcv_array_count(dd); i++)
13628 hfi1_put_tid(dd, i, PT_INVALID_FLUSH, 0, 0);
13630 /* RcvQPMapTable */
13631 for (i = 0; i < 32; i++)
13632 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13636 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13638 static void clear_cce_status(struct hfi1_devdata *dd, u64 status_bits,
13641 unsigned long timeout;
13644 /* is the condition present? */
13645 reg = read_csr(dd, CCE_STATUS);
13646 if ((reg & status_bits) == 0)
13649 /* clear the condition */
13650 write_csr(dd, CCE_CTRL, ctrl_bits);
13652 /* wait for the condition to clear */
13653 timeout = jiffies + msecs_to_jiffies(CCE_STATUS_TIMEOUT);
13655 reg = read_csr(dd, CCE_STATUS);
13656 if ((reg & status_bits) == 0)
13658 if (time_after(jiffies, timeout)) {
13660 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13661 status_bits, reg & status_bits);
13668 /* set CCE CSRs to chip reset defaults */
13669 static void reset_cce_csrs(struct hfi1_devdata *dd)
13673 /* CCE_REVISION read-only */
13674 /* CCE_REVISION2 read-only */
13675 /* CCE_CTRL - bits clear automatically */
13676 /* CCE_STATUS read-only, use CceCtrl to clear */
13677 clear_cce_status(dd, ALL_FROZE, CCE_CTRL_SPC_UNFREEZE_SMASK);
13678 clear_cce_status(dd, ALL_TXE_PAUSE, CCE_CTRL_TXE_RESUME_SMASK);
13679 clear_cce_status(dd, ALL_RXE_PAUSE, CCE_CTRL_RXE_RESUME_SMASK);
13680 for (i = 0; i < CCE_NUM_SCRATCH; i++)
13681 write_csr(dd, CCE_SCRATCH + (8 * i), 0);
13682 /* CCE_ERR_STATUS read-only */
13683 write_csr(dd, CCE_ERR_MASK, 0);
13684 write_csr(dd, CCE_ERR_CLEAR, ~0ull);
13685 /* CCE_ERR_FORCE leave alone */
13686 for (i = 0; i < CCE_NUM_32_BIT_COUNTERS; i++)
13687 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0);
13688 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR);
13689 /* CCE_PCIE_CTRL leave alone */
13690 for (i = 0; i < CCE_NUM_MSIX_VECTORS; i++) {
13691 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0);
13692 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i),
13693 CCE_MSIX_TABLE_UPPER_RESETCSR);
13695 for (i = 0; i < CCE_NUM_MSIX_PBAS; i++) {
13696 /* CCE_MSIX_PBA read-only */
13697 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull);
13698 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull);
13700 for (i = 0; i < CCE_NUM_INT_MAP_CSRS; i++)
13701 write_csr(dd, CCE_INT_MAP, 0);
13702 for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
13703 /* CCE_INT_STATUS read-only */
13704 write_csr(dd, CCE_INT_MASK + (8 * i), 0);
13705 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull);
13706 /* CCE_INT_FORCE leave alone */
13707 /* CCE_INT_BLOCKED read-only */
13709 for (i = 0; i < CCE_NUM_32_BIT_INT_COUNTERS; i++)
13710 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0);
13713 /* set MISC CSRs to chip reset defaults */
13714 static void reset_misc_csrs(struct hfi1_devdata *dd)
13718 for (i = 0; i < 32; i++) {
13719 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0);
13720 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
13721 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
13724 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13725 * only be written 128-byte chunks
13727 /* init RSA engine to clear lingering errors */
13728 write_csr(dd, MISC_CFG_RSA_CMD, 1);
13729 write_csr(dd, MISC_CFG_RSA_MU, 0);
13730 write_csr(dd, MISC_CFG_FW_CTRL, 0);
13731 /* MISC_STS_8051_DIGEST read-only */
13732 /* MISC_STS_SBM_DIGEST read-only */
13733 /* MISC_STS_PCIE_DIGEST read-only */
13734 /* MISC_STS_FAB_DIGEST read-only */
13735 /* MISC_ERR_STATUS read-only */
13736 write_csr(dd, MISC_ERR_MASK, 0);
13737 write_csr(dd, MISC_ERR_CLEAR, ~0ull);
13738 /* MISC_ERR_FORCE leave alone */
13741 /* set TXE CSRs to chip reset defaults */
13742 static void reset_txe_csrs(struct hfi1_devdata *dd)
13749 write_csr(dd, SEND_CTRL, 0);
13750 __cm_reset(dd, 0); /* reset CM internal state */
13751 /* SEND_CONTEXTS read-only */
13752 /* SEND_DMA_ENGINES read-only */
13753 /* SEND_PIO_MEM_SIZE read-only */
13754 /* SEND_DMA_MEM_SIZE read-only */
13755 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0);
13756 pio_reset_all(dd); /* SEND_PIO_INIT_CTXT */
13757 /* SEND_PIO_ERR_STATUS read-only */
13758 write_csr(dd, SEND_PIO_ERR_MASK, 0);
13759 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull);
13760 /* SEND_PIO_ERR_FORCE leave alone */
13761 /* SEND_DMA_ERR_STATUS read-only */
13762 write_csr(dd, SEND_DMA_ERR_MASK, 0);
13763 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull);
13764 /* SEND_DMA_ERR_FORCE leave alone */
13765 /* SEND_EGRESS_ERR_STATUS read-only */
13766 write_csr(dd, SEND_EGRESS_ERR_MASK, 0);
13767 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull);
13768 /* SEND_EGRESS_ERR_FORCE leave alone */
13769 write_csr(dd, SEND_BTH_QP, 0);
13770 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0);
13771 write_csr(dd, SEND_SC2VLT0, 0);
13772 write_csr(dd, SEND_SC2VLT1, 0);
13773 write_csr(dd, SEND_SC2VLT2, 0);
13774 write_csr(dd, SEND_SC2VLT3, 0);
13775 write_csr(dd, SEND_LEN_CHECK0, 0);
13776 write_csr(dd, SEND_LEN_CHECK1, 0);
13777 /* SEND_ERR_STATUS read-only */
13778 write_csr(dd, SEND_ERR_MASK, 0);
13779 write_csr(dd, SEND_ERR_CLEAR, ~0ull);
13780 /* SEND_ERR_FORCE read-only */
13781 for (i = 0; i < VL_ARB_LOW_PRIO_TABLE_SIZE; i++)
13782 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0);
13783 for (i = 0; i < VL_ARB_HIGH_PRIO_TABLE_SIZE; i++)
13784 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0);
13785 for (i = 0; i < chip_send_contexts(dd) / NUM_CONTEXTS_PER_SET; i++)
13786 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0);
13787 for (i = 0; i < TXE_NUM_32_BIT_COUNTER; i++)
13788 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0);
13789 for (i = 0; i < TXE_NUM_64_BIT_COUNTER; i++)
13790 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0);
13791 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR);
13792 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR);
13793 /* SEND_CM_CREDIT_USED_STATUS read-only */
13794 write_csr(dd, SEND_CM_TIMER_CTRL, 0);
13795 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0);
13796 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0);
13797 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0);
13798 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0);
13799 for (i = 0; i < TXE_NUM_DATA_VL; i++)
13800 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0);
13801 write_csr(dd, SEND_CM_CREDIT_VL15, 0);
13802 /* SEND_CM_CREDIT_USED_VL read-only */
13803 /* SEND_CM_CREDIT_USED_VL15 read-only */
13804 /* SEND_EGRESS_CTXT_STATUS read-only */
13805 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13806 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull);
13807 /* SEND_EGRESS_ERR_INFO read-only */
13808 /* SEND_EGRESS_ERR_SOURCE read-only */
13811 * TXE Per-Context CSRs
13813 for (i = 0; i < chip_send_contexts(dd); i++) {
13814 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
13815 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_CTRL, 0);
13816 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_RETURN_ADDR, 0);
13817 write_kctxt_csr(dd, i, SEND_CTXT_CREDIT_FORCE, 0);
13818 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, 0);
13819 write_kctxt_csr(dd, i, SEND_CTXT_ERR_CLEAR, ~0ull);
13820 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_ENABLE, 0);
13821 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_VL, 0);
13822 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_JOB_KEY, 0);
13823 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_PARTITION_KEY, 0);
13824 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_SLID, 0);
13825 write_kctxt_csr(dd, i, SEND_CTXT_CHECK_OPCODE, 0);
13829 * TXE Per-SDMA CSRs
13831 for (i = 0; i < chip_sdma_engines(dd); i++) {
13832 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
13833 /* SEND_DMA_STATUS read-only */
13834 write_kctxt_csr(dd, i, SEND_DMA_BASE_ADDR, 0);
13835 write_kctxt_csr(dd, i, SEND_DMA_LEN_GEN, 0);
13836 write_kctxt_csr(dd, i, SEND_DMA_TAIL, 0);
13837 /* SEND_DMA_HEAD read-only */
13838 write_kctxt_csr(dd, i, SEND_DMA_HEAD_ADDR, 0);
13839 write_kctxt_csr(dd, i, SEND_DMA_PRIORITY_THLD, 0);
13840 /* SEND_DMA_IDLE_CNT read-only */
13841 write_kctxt_csr(dd, i, SEND_DMA_RELOAD_CNT, 0);
13842 write_kctxt_csr(dd, i, SEND_DMA_DESC_CNT, 0);
13843 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13844 /* SEND_DMA_ENG_ERR_STATUS read-only */
13845 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, 0);
13846 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_CLEAR, ~0ull);
13847 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13848 write_kctxt_csr(dd, i, SEND_DMA_CHECK_ENABLE, 0);
13849 write_kctxt_csr(dd, i, SEND_DMA_CHECK_VL, 0);
13850 write_kctxt_csr(dd, i, SEND_DMA_CHECK_JOB_KEY, 0);
13851 write_kctxt_csr(dd, i, SEND_DMA_CHECK_PARTITION_KEY, 0);
13852 write_kctxt_csr(dd, i, SEND_DMA_CHECK_SLID, 0);
13853 write_kctxt_csr(dd, i, SEND_DMA_CHECK_OPCODE, 0);
13854 write_kctxt_csr(dd, i, SEND_DMA_MEMORY, 0);
13860 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13862 static void init_rbufs(struct hfi1_devdata *dd)
13868 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13873 reg = read_csr(dd, RCV_STATUS);
13874 if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13875 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK)) == 0)
13878 * Give up after 1ms - maximum wait time.
13880 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at
13881 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
13882 * 136 KB / (66% * 250MB/s) = 844us
13884 if (count++ > 500) {
13886 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13890 udelay(2); /* do not busy-wait the CSR */
13893 /* start the init - expect RcvCtrl to be 0 */
13894 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK);
13897 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13898 * period after the write before RcvStatus.RxRbufInitDone is valid.
13899 * The delay in the first run through the loop below is sufficient and
13900 * required before the first read of RcvStatus.RxRbufInintDone.
13902 read_csr(dd, RCV_CTRL);
13904 /* wait for the init to finish */
13907 /* delay is required first time through - see above */
13908 udelay(2); /* do not busy-wait the CSR */
13909 reg = read_csr(dd, RCV_STATUS);
13910 if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK))
13913 /* give up after 100us - slowest possible at 33MHz is 73us */
13914 if (count++ > 50) {
13916 "%s: RcvStatus.RxRbufInit not set, continuing\n",
13923 /* set RXE CSRs to chip reset defaults */
13924 static void reset_rxe_csrs(struct hfi1_devdata *dd)
13931 write_csr(dd, RCV_CTRL, 0);
13933 /* RCV_STATUS read-only */
13934 /* RCV_CONTEXTS read-only */
13935 /* RCV_ARRAY_CNT read-only */
13936 /* RCV_BUF_SIZE read-only */
13937 write_csr(dd, RCV_BTH_QP, 0);
13938 write_csr(dd, RCV_MULTICAST, 0);
13939 write_csr(dd, RCV_BYPASS, 0);
13940 write_csr(dd, RCV_VL15, 0);
13941 /* this is a clear-down */
13942 write_csr(dd, RCV_ERR_INFO,
13943 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
13944 /* RCV_ERR_STATUS read-only */
13945 write_csr(dd, RCV_ERR_MASK, 0);
13946 write_csr(dd, RCV_ERR_CLEAR, ~0ull);
13947 /* RCV_ERR_FORCE leave alone */
13948 for (i = 0; i < 32; i++)
13949 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0);
13950 for (i = 0; i < 4; i++)
13951 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0);
13952 for (i = 0; i < RXE_NUM_32_BIT_COUNTERS; i++)
13953 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0);
13954 for (i = 0; i < RXE_NUM_64_BIT_COUNTERS; i++)
13955 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0);
13956 for (i = 0; i < RXE_NUM_RSM_INSTANCES; i++)
13957 clear_rsm_rule(dd, i);
13958 for (i = 0; i < 32; i++)
13959 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0);
13962 * RXE Kernel and User Per-Context CSRs
13964 for (i = 0; i < chip_rcv_contexts(dd); i++) {
13966 write_kctxt_csr(dd, i, RCV_CTXT_CTRL, 0);
13967 /* RCV_CTXT_STATUS read-only */
13968 write_kctxt_csr(dd, i, RCV_EGR_CTRL, 0);
13969 write_kctxt_csr(dd, i, RCV_TID_CTRL, 0);
13970 write_kctxt_csr(dd, i, RCV_KEY_CTRL, 0);
13971 write_kctxt_csr(dd, i, RCV_HDR_ADDR, 0);
13972 write_kctxt_csr(dd, i, RCV_HDR_CNT, 0);
13973 write_kctxt_csr(dd, i, RCV_HDR_ENT_SIZE, 0);
13974 write_kctxt_csr(dd, i, RCV_HDR_SIZE, 0);
13975 write_kctxt_csr(dd, i, RCV_HDR_TAIL_ADDR, 0);
13976 write_kctxt_csr(dd, i, RCV_AVAIL_TIME_OUT, 0);
13977 write_kctxt_csr(dd, i, RCV_HDR_OVFL_CNT, 0);
13980 /* RCV_HDR_TAIL read-only */
13981 write_uctxt_csr(dd, i, RCV_HDR_HEAD, 0);
13982 /* RCV_EGR_INDEX_TAIL read-only */
13983 write_uctxt_csr(dd, i, RCV_EGR_INDEX_HEAD, 0);
13984 /* RCV_EGR_OFFSET_TAIL read-only */
13985 for (j = 0; j < RXE_NUM_TID_FLOWS; j++) {
13986 write_uctxt_csr(dd, i,
13987 RCV_TID_FLOW_TABLE + (8 * j), 0);
13993 * Set sc2vl tables.
13995 * They power on to zeros, so to avoid send context errors
13996 * they need to be set:
13998 * SC 0-7 -> VL 0-7 (respectively)
14003 static void init_sc2vl_tables(struct hfi1_devdata *dd)
14006 /* init per architecture spec, constrained by hardware capability */
14008 /* HFI maps sent packets */
14009 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL(
14015 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL(
14021 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL(
14027 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL(
14034 /* DC maps received packets */
14035 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL(
14037 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
14038 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
14039 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL(
14041 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
14042 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
14044 /* initialize the cached sc2vl values consistently with h/w */
14045 for (i = 0; i < 32; i++) {
14046 if (i < 8 || i == 15)
14047 *((u8 *)(dd->sc2vl) + i) = (u8)i;
14049 *((u8 *)(dd->sc2vl) + i) = 0;
14054 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
14055 * depend on the chip going through a power-on reset - a driver may be loaded
14056 * and unloaded many times.
14058 * Do not write any CSR values to the chip in this routine - there may be
14059 * a reset following the (possible) FLR in this routine.
14062 static int init_chip(struct hfi1_devdata *dd)
14068 * Put the HFI CSRs in a known state.
14069 * Combine this with a DC reset.
14071 * Stop the device from doing anything while we do a
14072 * reset. We know there are no other active users of
14073 * the device since we are now in charge. Turn off
14074 * off all outbound and inbound traffic and make sure
14075 * the device does not generate any interrupts.
14078 /* disable send contexts and SDMA engines */
14079 write_csr(dd, SEND_CTRL, 0);
14080 for (i = 0; i < chip_send_contexts(dd); i++)
14081 write_kctxt_csr(dd, i, SEND_CTXT_CTRL, 0);
14082 for (i = 0; i < chip_sdma_engines(dd); i++)
14083 write_kctxt_csr(dd, i, SEND_DMA_CTRL, 0);
14084 /* disable port (turn off RXE inbound traffic) and contexts */
14085 write_csr(dd, RCV_CTRL, 0);
14086 for (i = 0; i < chip_rcv_contexts(dd); i++)
14087 write_csr(dd, RCV_CTXT_CTRL, 0);
14088 /* mask all interrupt sources */
14089 for (i = 0; i < CCE_NUM_INT_CSRS; i++)
14090 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull);
14093 * DC Reset: do a full DC reset before the register clear.
14094 * A recommended length of time to hold is one CSR read,
14095 * so reread the CceDcCtrl. Then, hold the DC in reset
14096 * across the clear.
14098 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
14099 (void)read_csr(dd, CCE_DC_CTRL);
14103 * A FLR will reset the SPC core and part of the PCIe.
14104 * The parts that need to be restored have already been
14107 dd_dev_info(dd, "Resetting CSRs with FLR\n");
14109 /* do the FLR, the DC reset will remain */
14110 pcie_flr(dd->pcidev);
14112 /* restore command and BARs */
14113 ret = restore_pci_variables(dd);
14115 dd_dev_err(dd, "%s: Could not restore PCI variables\n",
14121 dd_dev_info(dd, "Resetting CSRs with FLR\n");
14122 pcie_flr(dd->pcidev);
14123 ret = restore_pci_variables(dd);
14125 dd_dev_err(dd, "%s: Could not restore PCI variables\n",
14131 dd_dev_info(dd, "Resetting CSRs with writes\n");
14132 reset_cce_csrs(dd);
14133 reset_txe_csrs(dd);
14134 reset_rxe_csrs(dd);
14135 reset_misc_csrs(dd);
14137 /* clear the DC reset */
14138 write_csr(dd, CCE_DC_CTRL, 0);
14140 /* Set the LED off */
14144 * Clear the QSFP reset.
14145 * An FLR enforces a 0 on all out pins. The driver does not touch
14146 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
14147 * anything plugged constantly in reset, if it pays attention
14149 * Prime examples of this are optical cables. Set all pins high.
14150 * I2CCLK and I2CDAT will change per direction, and INT_N and
14151 * MODPRS_N are input only and their value is ignored.
14153 write_csr(dd, ASIC_QSFP1_OUT, 0x1f);
14154 write_csr(dd, ASIC_QSFP2_OUT, 0x1f);
14155 init_chip_resources(dd);
14159 static void init_early_variables(struct hfi1_devdata *dd)
14163 /* assign link credit variables */
14165 dd->link_credits = CM_GLOBAL_CREDITS;
14167 dd->link_credits--;
14168 dd->vcu = cu_to_vcu(hfi1_cu);
14169 /* enough room for 8 MAD packets plus header - 17K */
14170 dd->vl15_init = (8 * (2048 + 128)) / vau_to_au(dd->vau);
14171 if (dd->vl15_init > dd->link_credits)
14172 dd->vl15_init = dd->link_credits;
14174 write_uninitialized_csrs_and_memories(dd);
14176 if (HFI1_CAP_IS_KSET(PKEY_CHECK))
14177 for (i = 0; i < dd->num_pports; i++) {
14178 struct hfi1_pportdata *ppd = &dd->pport[i];
14180 set_partition_keys(ppd);
14182 init_sc2vl_tables(dd);
14185 static void init_kdeth_qp(struct hfi1_devdata *dd)
14187 write_csr(dd, SEND_BTH_QP,
14188 (RVT_KDETH_QP_PREFIX & SEND_BTH_QP_KDETH_QP_MASK) <<
14189 SEND_BTH_QP_KDETH_QP_SHIFT);
14191 write_csr(dd, RCV_BTH_QP,
14192 (RVT_KDETH_QP_PREFIX & RCV_BTH_QP_KDETH_QP_MASK) <<
14193 RCV_BTH_QP_KDETH_QP_SHIFT);
14199 * @idx: index to read
14201 u8 hfi1_get_qp_map(struct hfi1_devdata *dd, u8 idx)
14203 u64 reg = read_csr(dd, RCV_QP_MAP_TABLE + (idx / 8) * 8);
14205 reg >>= (idx % 8) * 8;
14211 * @dd - device data
14212 * @first_ctxt - first context
14213 * @last_ctxt - first context
14215 * This return sets the qpn mapping table that
14216 * is indexed by qpn[8:1].
14218 * The routine will round robin the 256 settings
14219 * from first_ctxt to last_ctxt.
14221 * The first/last looks ahead to having specialized
14222 * receive contexts for mgmt and bypass. Normal
14223 * verbs traffic will assumed to be on a range
14224 * of receive contexts.
14226 static void init_qpmap_table(struct hfi1_devdata *dd,
14231 u64 regno = RCV_QP_MAP_TABLE;
14233 u64 ctxt = first_ctxt;
14235 for (i = 0; i < 256; i++) {
14236 reg |= ctxt << (8 * (i % 8));
14238 if (ctxt > last_ctxt)
14241 write_csr(dd, regno, reg);
14247 add_rcvctrl(dd, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
14248 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK);
14251 struct rsm_map_table {
14252 u64 map[NUM_MAP_REGS];
14256 struct rsm_rule_data {
14272 * Return an initialized RMT map table for users to fill in. OK if it
14273 * returns NULL, indicating no table.
14275 static struct rsm_map_table *alloc_rsm_map_table(struct hfi1_devdata *dd)
14277 struct rsm_map_table *rmt;
14278 u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */
14280 rmt = kmalloc(sizeof(*rmt), GFP_KERNEL);
14282 memset(rmt->map, rxcontext, sizeof(rmt->map));
14290 * Write the final RMT map table to the chip and free the table. OK if
14293 static void complete_rsm_map_table(struct hfi1_devdata *dd,
14294 struct rsm_map_table *rmt)
14299 /* write table to chip */
14300 for (i = 0; i < NUM_MAP_REGS; i++)
14301 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]);
14304 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14308 /* Is a receive side mapping rule */
14309 static bool has_rsm_rule(struct hfi1_devdata *dd, u8 rule_index)
14311 return read_csr(dd, RCV_RSM_CFG + (8 * rule_index)) != 0;
14315 * Add a receive side mapping rule.
14317 static void add_rsm_rule(struct hfi1_devdata *dd, u8 rule_index,
14318 struct rsm_rule_data *rrd)
14320 write_csr(dd, RCV_RSM_CFG + (8 * rule_index),
14321 (u64)rrd->offset << RCV_RSM_CFG_OFFSET_SHIFT |
14322 1ull << rule_index | /* enable bit */
14323 (u64)rrd->pkt_type << RCV_RSM_CFG_PACKET_TYPE_SHIFT);
14324 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index),
14325 (u64)rrd->field1_off << RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT |
14326 (u64)rrd->field2_off << RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT |
14327 (u64)rrd->index1_off << RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT |
14328 (u64)rrd->index1_width << RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT |
14329 (u64)rrd->index2_off << RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT |
14330 (u64)rrd->index2_width << RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT);
14331 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index),
14332 (u64)rrd->mask1 << RCV_RSM_MATCH_MASK1_SHIFT |
14333 (u64)rrd->value1 << RCV_RSM_MATCH_VALUE1_SHIFT |
14334 (u64)rrd->mask2 << RCV_RSM_MATCH_MASK2_SHIFT |
14335 (u64)rrd->value2 << RCV_RSM_MATCH_VALUE2_SHIFT);
14339 * Clear a receive side mapping rule.
14341 static void clear_rsm_rule(struct hfi1_devdata *dd, u8 rule_index)
14343 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0);
14344 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0);
14345 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0);
14348 /* return the number of RSM map table entries that will be used for QOS */
14349 static int qos_rmt_entries(unsigned int n_krcv_queues, unsigned int *mp,
14354 uint max_by_vl = 0;
14356 /* is QOS active at all? */
14357 if (n_krcv_queues < MIN_KERNEL_KCTXTS ||
14362 /* determine bits for qpn */
14363 for (i = 0; i < min_t(unsigned int, num_vls, krcvqsset); i++)
14364 if (krcvqs[i] > max_by_vl)
14365 max_by_vl = krcvqs[i];
14366 if (max_by_vl > 32)
14368 m = ilog2(__roundup_pow_of_two(max_by_vl));
14370 /* determine bits for vl */
14371 n = ilog2(__roundup_pow_of_two(num_vls));
14373 /* reject if too much is used */
14382 return 1 << (m + n);
14393 * init_qos - init RX qos
14394 * @dd - device data
14395 * @rmt - RSM map table
14397 * This routine initializes Rule 0 and the RSM map table to implement
14398 * quality of service (qos).
14400 * If all of the limit tests succeed, qos is applied based on the array
14401 * interpretation of krcvqs where entry 0 is VL0.
14403 * The number of vl bits (n) and the number of qpn bits (m) are computed to
14404 * feed both the RSM map table and the single rule.
14406 static void init_qos(struct hfi1_devdata *dd, struct rsm_map_table *rmt)
14408 struct rsm_rule_data rrd;
14409 unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
14410 unsigned int rmt_entries;
14415 rmt_entries = qos_rmt_entries(dd->n_krcv_queues - 1, &m, &n);
14416 if (rmt_entries == 0)
14418 qpns_per_vl = 1 << m;
14420 /* enough room in the map table? */
14421 rmt_entries = 1 << (m + n);
14422 if (rmt->used + rmt_entries >= NUM_MAP_ENTRIES)
14425 /* add qos entries to the the RSM map table */
14426 for (i = 0, ctxt = FIRST_KERNEL_KCTXT; i < num_vls; i++) {
14429 for (qpn = 0, tctxt = ctxt;
14430 krcvqs[i] && qpn < qpns_per_vl; qpn++) {
14431 unsigned idx, regoff, regidx;
14433 /* generate the index the hardware will produce */
14434 idx = rmt->used + ((qpn << n) ^ i);
14435 regoff = (idx % 8) * 8;
14437 /* replace default with context number */
14438 reg = rmt->map[regidx];
14439 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14441 reg |= (u64)(tctxt++) << regoff;
14442 rmt->map[regidx] = reg;
14443 if (tctxt == ctxt + krcvqs[i])
14449 rrd.offset = rmt->used;
14451 rrd.field1_off = LRH_BTH_MATCH_OFFSET;
14452 rrd.field2_off = LRH_SC_MATCH_OFFSET;
14453 rrd.index1_off = LRH_SC_SELECT_OFFSET;
14454 rrd.index1_width = n;
14455 rrd.index2_off = QPN_SELECT_OFFSET;
14456 rrd.index2_width = m + n;
14457 rrd.mask1 = LRH_BTH_MASK;
14458 rrd.value1 = LRH_BTH_VALUE;
14459 rrd.mask2 = LRH_SC_MASK;
14460 rrd.value2 = LRH_SC_VALUE;
14463 add_rsm_rule(dd, RSM_INS_VERBS, &rrd);
14465 /* mark RSM map entries as used */
14466 rmt->used += rmt_entries;
14467 /* map everything else to the mcast/err/vl15 context */
14468 init_qpmap_table(dd, HFI1_CTRL_CTXT, HFI1_CTRL_CTXT);
14469 dd->qos_shift = n + 1;
14473 init_qpmap_table(dd, FIRST_KERNEL_KCTXT, dd->n_krcv_queues - 1);
14476 static void init_fecn_handling(struct hfi1_devdata *dd,
14477 struct rsm_map_table *rmt)
14479 struct rsm_rule_data rrd;
14481 int i, idx, regoff, regidx, start;
14485 if (HFI1_CAP_IS_KSET(TID_RDMA))
14486 /* Exclude context 0 */
14489 start = dd->first_dyn_alloc_ctxt;
14491 total_cnt = dd->num_rcv_contexts - start;
14493 /* there needs to be enough room in the map table */
14494 if (rmt->used + total_cnt >= NUM_MAP_ENTRIES) {
14495 dd_dev_err(dd, "FECN handling disabled - too many contexts allocated\n");
14500 * RSM will extract the destination context as an index into the
14501 * map table. The destination contexts are a sequential block
14502 * in the range start...num_rcv_contexts-1 (inclusive).
14503 * Map entries are accessed as offset + extracted value. Adjust
14504 * the added offset so this sequence can be placed anywhere in
14505 * the table - as long as the entries themselves do not wrap.
14506 * There are only enough bits in offset for the table size, so
14507 * start with that to allow for a "negative" offset.
14509 offset = (u8)(NUM_MAP_ENTRIES + rmt->used - start);
14511 for (i = start, idx = rmt->used; i < dd->num_rcv_contexts;
14513 /* replace with identity mapping */
14514 regoff = (idx % 8) * 8;
14516 reg = rmt->map[regidx];
14517 reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff);
14518 reg |= (u64)i << regoff;
14519 rmt->map[regidx] = reg;
14523 * For RSM intercept of Expected FECN packets:
14524 * o packet type 0 - expected
14525 * o match on F (bit 95), using select/match 1, and
14526 * o match on SH (bit 133), using select/match 2.
14528 * Use index 1 to extract the 8-bit receive context from DestQP
14529 * (start at bit 64). Use that as the RSM map table index.
14531 rrd.offset = offset;
14533 rrd.field1_off = 95;
14534 rrd.field2_off = 133;
14535 rrd.index1_off = 64;
14536 rrd.index1_width = 8;
14537 rrd.index2_off = 0;
14538 rrd.index2_width = 0;
14545 add_rsm_rule(dd, RSM_INS_FECN, &rrd);
14547 rmt->used += total_cnt;
14550 static inline bool hfi1_is_rmt_full(int start, int spare)
14552 return (start + spare) > NUM_MAP_ENTRIES;
14555 static bool hfi1_netdev_update_rmt(struct hfi1_devdata *dd)
14561 int rmt_start = hfi1_netdev_get_free_rmt_idx(dd);
14562 int ctxt_count = hfi1_netdev_ctxt_count(dd);
14564 /* We already have contexts mapped in RMT */
14565 if (has_rsm_rule(dd, RSM_INS_VNIC) || has_rsm_rule(dd, RSM_INS_AIP)) {
14566 dd_dev_info(dd, "Contexts are already mapped in RMT\n");
14570 if (hfi1_is_rmt_full(rmt_start, NUM_NETDEV_MAP_ENTRIES)) {
14571 dd_dev_err(dd, "Not enough RMT entries used = %d\n",
14576 dev_dbg(&(dd)->pcidev->dev, "RMT start = %d, end %d\n",
14578 rmt_start + NUM_NETDEV_MAP_ENTRIES);
14580 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
14581 regoff = RCV_RSM_MAP_TABLE + (rmt_start / 8) * 8;
14582 reg = read_csr(dd, regoff);
14583 for (i = 0; i < NUM_NETDEV_MAP_ENTRIES; i++) {
14584 /* Update map register with netdev context */
14585 j = (rmt_start + i) % 8;
14586 reg &= ~(0xffllu << (j * 8));
14587 reg |= (u64)hfi1_netdev_get_ctxt(dd, ctx_id++)->ctxt << (j * 8);
14588 /* Wrap up netdev ctx index */
14589 ctx_id %= ctxt_count;
14590 /* Write back map register */
14591 if (j == 7 || ((i + 1) == NUM_NETDEV_MAP_ENTRIES)) {
14592 dev_dbg(&(dd)->pcidev->dev,
14593 "RMT[%d] =0x%llx\n",
14594 regoff - RCV_RSM_MAP_TABLE, reg);
14596 write_csr(dd, regoff, reg);
14598 if (i < (NUM_NETDEV_MAP_ENTRIES - 1))
14599 reg = read_csr(dd, regoff);
14606 static void hfi1_enable_rsm_rule(struct hfi1_devdata *dd,
14607 int rule, struct rsm_rule_data *rrd)
14609 if (!hfi1_netdev_update_rmt(dd)) {
14610 dd_dev_err(dd, "Failed to update RMT for RSM%d rule\n", rule);
14614 add_rsm_rule(dd, rule, rrd);
14615 add_rcvctrl(dd, RCV_CTRL_RCV_RSM_ENABLE_SMASK);
14618 void hfi1_init_aip_rsm(struct hfi1_devdata *dd)
14621 * go through with the initialisation only if this rule actually doesn't
14624 if (atomic_fetch_inc(&dd->ipoib_rsm_usr_num) == 0) {
14625 int rmt_start = hfi1_netdev_get_free_rmt_idx(dd);
14626 struct rsm_rule_data rrd = {
14627 .offset = rmt_start,
14628 .pkt_type = IB_PACKET_TYPE,
14629 .field1_off = LRH_BTH_MATCH_OFFSET,
14630 .mask1 = LRH_BTH_MASK,
14631 .value1 = LRH_BTH_VALUE,
14632 .field2_off = BTH_DESTQP_MATCH_OFFSET,
14633 .mask2 = BTH_DESTQP_MASK,
14634 .value2 = BTH_DESTQP_VALUE,
14635 .index1_off = DETH_AIP_SQPN_SELECT_OFFSET +
14636 ilog2(NUM_NETDEV_MAP_ENTRIES),
14637 .index1_width = ilog2(NUM_NETDEV_MAP_ENTRIES),
14638 .index2_off = DETH_AIP_SQPN_SELECT_OFFSET,
14639 .index2_width = ilog2(NUM_NETDEV_MAP_ENTRIES)
14642 hfi1_enable_rsm_rule(dd, RSM_INS_AIP, &rrd);
14646 /* Initialize RSM for VNIC */
14647 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd)
14649 int rmt_start = hfi1_netdev_get_free_rmt_idx(dd);
14650 struct rsm_rule_data rrd = {
14651 /* Add rule for vnic */
14652 .offset = rmt_start,
14654 /* Match 16B packets */
14655 .field1_off = L2_TYPE_MATCH_OFFSET,
14656 .mask1 = L2_TYPE_MASK,
14657 .value1 = L2_16B_VALUE,
14658 /* Match ETH L4 packets */
14659 .field2_off = L4_TYPE_MATCH_OFFSET,
14660 .mask2 = L4_16B_TYPE_MASK,
14661 .value2 = L4_16B_ETH_VALUE,
14662 /* Calc context from veswid and entropy */
14663 .index1_off = L4_16B_HDR_VESWID_OFFSET,
14664 .index1_width = ilog2(NUM_NETDEV_MAP_ENTRIES),
14665 .index2_off = L2_16B_ENTROPY_OFFSET,
14666 .index2_width = ilog2(NUM_NETDEV_MAP_ENTRIES)
14669 hfi1_enable_rsm_rule(dd, RSM_INS_VNIC, &rrd);
14672 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd)
14674 clear_rsm_rule(dd, RSM_INS_VNIC);
14677 void hfi1_deinit_aip_rsm(struct hfi1_devdata *dd)
14679 /* only actually clear the rule if it's the last user asking to do so */
14680 if (atomic_fetch_add_unless(&dd->ipoib_rsm_usr_num, -1, 0) == 1)
14681 clear_rsm_rule(dd, RSM_INS_AIP);
14684 static int init_rxe(struct hfi1_devdata *dd)
14686 struct rsm_map_table *rmt;
14689 /* enable all receive errors */
14690 write_csr(dd, RCV_ERR_MASK, ~0ull);
14692 rmt = alloc_rsm_map_table(dd);
14696 /* set up QOS, including the QPN map table */
14698 init_fecn_handling(dd, rmt);
14699 complete_rsm_map_table(dd, rmt);
14700 /* record number of used rsm map entries for netdev */
14701 hfi1_netdev_set_free_rmt_idx(dd, rmt->used);
14705 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14706 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14707 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
14708 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14709 * Max_PayLoad_Size set to its minimum of 128.
14711 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14712 * (64 bytes). Max_Payload_Size is possibly modified upward in
14713 * tune_pcie_caps() which is called after this routine.
14716 /* Have 16 bytes (4DW) of bypass header available in header queue */
14717 val = read_csr(dd, RCV_BYPASS);
14718 val &= ~RCV_BYPASS_HDR_SIZE_SMASK;
14719 val |= ((4ull & RCV_BYPASS_HDR_SIZE_MASK) <<
14720 RCV_BYPASS_HDR_SIZE_SHIFT);
14721 write_csr(dd, RCV_BYPASS, val);
14725 static void init_other(struct hfi1_devdata *dd)
14727 /* enable all CCE errors */
14728 write_csr(dd, CCE_ERR_MASK, ~0ull);
14729 /* enable *some* Misc errors */
14730 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK);
14731 /* enable all DC errors, except LCB */
14732 write_csr(dd, DCC_ERR_FLG_EN, ~0ull);
14733 write_csr(dd, DC_DC8051_ERR_EN, ~0ull);
14737 * Fill out the given AU table using the given CU. A CU is defined in terms
14738 * AUs. The table is a an encoding: given the index, how many AUs does that
14741 * NOTE: Assumes that the register layout is the same for the
14742 * local and remote tables.
14744 static void assign_cm_au_table(struct hfi1_devdata *dd, u32 cu,
14745 u32 csr0to3, u32 csr4to7)
14747 write_csr(dd, csr0to3,
14748 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT |
14749 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT |
14751 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT |
14753 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT);
14754 write_csr(dd, csr4to7,
14756 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT |
14758 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT |
14760 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT |
14762 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT);
14765 static void assign_local_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14767 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_LOCAL_AU_TABLE0_TO3,
14768 SEND_CM_LOCAL_AU_TABLE4_TO7);
14771 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu)
14773 assign_cm_au_table(dd, vcu_to_cu(vcu), SEND_CM_REMOTE_AU_TABLE0_TO3,
14774 SEND_CM_REMOTE_AU_TABLE4_TO7);
14777 static void init_txe(struct hfi1_devdata *dd)
14781 /* enable all PIO, SDMA, general, and Egress errors */
14782 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull);
14783 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull);
14784 write_csr(dd, SEND_ERR_MASK, ~0ull);
14785 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull);
14787 /* enable all per-context and per-SDMA engine errors */
14788 for (i = 0; i < chip_send_contexts(dd); i++)
14789 write_kctxt_csr(dd, i, SEND_CTXT_ERR_MASK, ~0ull);
14790 for (i = 0; i < chip_sdma_engines(dd); i++)
14791 write_kctxt_csr(dd, i, SEND_DMA_ENG_ERR_MASK, ~0ull);
14793 /* set the local CU to AU mapping */
14794 assign_local_cm_au_table(dd, dd->vcu);
14797 * Set reasonable default for Credit Return Timer
14798 * Don't set on Simulator - causes it to choke.
14800 if (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
14801 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE);
14804 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
14810 if (!rcd || !rcd->sc)
14813 hw_ctxt = rcd->sc->hw_context;
14814 reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */
14815 ((jkey & SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK) <<
14816 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT);
14817 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14818 if (HFI1_CAP_KGET_MASK(rcd->flags, ALLOW_PERM_JKEY))
14819 reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK;
14820 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, reg);
14822 * Enable send-side J_KEY integrity check, unless this is A0 h/w
14825 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
14826 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14827 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14830 /* Enable J_KEY check on receive context. */
14831 reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK |
14832 ((jkey & RCV_KEY_CTRL_JOB_KEY_VALUE_MASK) <<
14833 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT);
14834 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg);
14839 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
14844 if (!rcd || !rcd->sc)
14847 hw_ctxt = rcd->sc->hw_context;
14848 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, 0);
14850 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14851 * This check would not have been enabled for A0 h/w, see
14855 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
14856 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
14857 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14859 /* Turn off the J_KEY on the receive side */
14860 write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, 0);
14865 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd,
14871 if (!rcd || !rcd->sc)
14874 hw_ctxt = rcd->sc->hw_context;
14875 reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) <<
14876 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT;
14877 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg);
14878 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
14879 reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14880 reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK;
14881 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14886 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt)
14891 if (!ctxt || !ctxt->sc)
14894 hw_ctxt = ctxt->sc->hw_context;
14895 reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE);
14896 reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK;
14897 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg);
14898 write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, 0);
14904 * Start doing the clean up the the chip. Our clean up happens in multiple
14905 * stages and this is just the first.
14907 void hfi1_start_cleanup(struct hfi1_devdata *dd)
14912 finish_chip_resources(dd);
14915 #define HFI_BASE_GUID(dev) \
14916 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14919 * Information can be shared between the two HFIs on the same ASIC
14920 * in the same OS. This function finds the peer device and sets
14921 * up a shared structure.
14923 static int init_asic_data(struct hfi1_devdata *dd)
14925 unsigned long index;
14926 struct hfi1_devdata *peer;
14927 struct hfi1_asic_data *asic_data;
14930 /* pre-allocate the asic structure in case we are the first device */
14931 asic_data = kzalloc(sizeof(*dd->asic_data), GFP_KERNEL);
14935 xa_lock_irq(&hfi1_dev_table);
14936 /* Find our peer device */
14937 xa_for_each(&hfi1_dev_table, index, peer) {
14938 if ((HFI_BASE_GUID(dd) == HFI_BASE_GUID(peer)) &&
14939 dd->unit != peer->unit)
14944 /* use already allocated structure */
14945 dd->asic_data = peer->asic_data;
14948 dd->asic_data = asic_data;
14949 mutex_init(&dd->asic_data->asic_resource_mutex);
14951 dd->asic_data->dds[dd->hfi1_id] = dd; /* self back-pointer */
14952 xa_unlock_irq(&hfi1_dev_table);
14954 /* first one through - set up i2c devices */
14956 ret = set_up_i2c(dd, dd->asic_data);
14962 * Set dd->boardname. Use a generic name if a name is not returned from
14963 * EFI variable space.
14965 * Return 0 on success, -ENOMEM if space could not be allocated.
14967 static int obtain_boardname(struct hfi1_devdata *dd)
14969 /* generic board description */
14970 const char generic[] =
14971 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
14972 unsigned long size;
14975 ret = read_hfi1_efi_var(dd, "description", &size,
14976 (void **)&dd->boardname);
14978 dd_dev_info(dd, "Board description not found\n");
14979 /* use generic description */
14980 dd->boardname = kstrdup(generic, GFP_KERNEL);
14981 if (!dd->boardname)
14988 * Check the interrupt registers to make sure that they are mapped correctly.
14989 * It is intended to help user identify any mismapping by VMM when the driver
14990 * is running in a VM. This function should only be called before interrupt
14991 * is set up properly.
14993 * Return 0 on success, -EINVAL on failure.
14995 static int check_int_registers(struct hfi1_devdata *dd)
14998 u64 all_bits = ~(u64)0;
15001 /* Clear CceIntMask[0] to avoid raising any interrupts */
15002 mask = read_csr(dd, CCE_INT_MASK);
15003 write_csr(dd, CCE_INT_MASK, 0ull);
15004 reg = read_csr(dd, CCE_INT_MASK);
15008 /* Clear all interrupt status bits */
15009 write_csr(dd, CCE_INT_CLEAR, all_bits);
15010 reg = read_csr(dd, CCE_INT_STATUS);
15014 /* Set all interrupt status bits */
15015 write_csr(dd, CCE_INT_FORCE, all_bits);
15016 reg = read_csr(dd, CCE_INT_STATUS);
15017 if (reg != all_bits)
15020 /* Restore the interrupt mask */
15021 write_csr(dd, CCE_INT_CLEAR, all_bits);
15022 write_csr(dd, CCE_INT_MASK, mask);
15026 write_csr(dd, CCE_INT_MASK, mask);
15027 dd_dev_err(dd, "Interrupt registers not properly mapped by VMM\n");
15032 * hfi1_init_dd() - Initialize most of the dd structure.
15033 * @dev: the pci_dev for hfi1_ib device
15034 * @ent: pci_device_id struct for this dev
15036 * This is global, and is called directly at init to set up the
15037 * chip-specific function pointers for later use.
15039 int hfi1_init_dd(struct hfi1_devdata *dd)
15041 struct pci_dev *pdev = dd->pcidev;
15042 struct hfi1_pportdata *ppd;
15045 static const char * const inames[] = { /* implementation names */
15047 "RTL VCS simulation",
15048 "RTL FPGA emulation",
15049 "Functional simulator"
15051 struct pci_dev *parent = pdev->bus->self;
15052 u32 sdma_engines = chip_sdma_engines(dd);
15055 for (i = 0; i < dd->num_pports; i++, ppd++) {
15057 /* init common fields */
15058 hfi1_init_pportdata(pdev, ppd, dd, 0, 1);
15059 /* DC supports 4 link widths */
15060 ppd->link_width_supported =
15061 OPA_LINK_WIDTH_1X | OPA_LINK_WIDTH_2X |
15062 OPA_LINK_WIDTH_3X | OPA_LINK_WIDTH_4X;
15063 ppd->link_width_downgrade_supported =
15064 ppd->link_width_supported;
15065 /* start out enabling only 4X */
15066 ppd->link_width_enabled = OPA_LINK_WIDTH_4X;
15067 ppd->link_width_downgrade_enabled =
15068 ppd->link_width_downgrade_supported;
15069 /* link width active is 0 when link is down */
15070 /* link width downgrade active is 0 when link is down */
15072 if (num_vls < HFI1_MIN_VLS_SUPPORTED ||
15073 num_vls > HFI1_MAX_VLS_SUPPORTED) {
15074 dd_dev_err(dd, "Invalid num_vls %u, using %u VLs\n",
15075 num_vls, HFI1_MAX_VLS_SUPPORTED);
15076 num_vls = HFI1_MAX_VLS_SUPPORTED;
15078 ppd->vls_supported = num_vls;
15079 ppd->vls_operational = ppd->vls_supported;
15080 /* Set the default MTU. */
15081 for (vl = 0; vl < num_vls; vl++)
15082 dd->vld[vl].mtu = hfi1_max_mtu;
15083 dd->vld[15].mtu = MAX_MAD_PACKET;
15085 * Set the initial values to reasonable default, will be set
15086 * for real when link is up.
15088 ppd->overrun_threshold = 0x4;
15089 ppd->phy_error_threshold = 0xf;
15090 ppd->port_crc_mode_enabled = link_crc_mask;
15091 /* initialize supported LTP CRC mode */
15092 ppd->port_ltp_crc_mode = cap_to_port_ltp(link_crc_mask) << 8;
15093 /* initialize enabled LTP CRC mode */
15094 ppd->port_ltp_crc_mode |= cap_to_port_ltp(link_crc_mask) << 4;
15095 /* start in offline */
15096 ppd->host_link_state = HLS_DN_OFFLINE;
15097 init_vl_arb_caches(ppd);
15101 * Do remaining PCIe setup and save PCIe values in dd.
15102 * Any error printing is already done by the init code.
15103 * On return, we have the chip mapped.
15105 ret = hfi1_pcie_ddinit(dd, pdev);
15109 /* Save PCI space registers to rewrite after device reset */
15110 ret = save_pci_variables(dd);
15114 dd->majrev = (dd->revision >> CCE_REVISION_CHIP_REV_MAJOR_SHIFT)
15115 & CCE_REVISION_CHIP_REV_MAJOR_MASK;
15116 dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
15117 & CCE_REVISION_CHIP_REV_MINOR_MASK;
15120 * Check interrupt registers mapping if the driver has no access to
15121 * the upstream component. In this case, it is likely that the driver
15122 * is running in a VM.
15125 ret = check_int_registers(dd);
15131 * obtain the hardware ID - NOT related to unit, which is a
15132 * software enumeration
15134 reg = read_csr(dd, CCE_REVISION2);
15135 dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
15136 & CCE_REVISION2_HFI_ID_MASK;
15137 /* the variable size will remove unwanted bits */
15138 dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT;
15139 dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT;
15140 dd_dev_info(dd, "Implementation: %s, revision 0x%x\n",
15141 dd->icode < ARRAY_SIZE(inames) ?
15142 inames[dd->icode] : "unknown", (int)dd->irev);
15144 /* speeds the hardware can support */
15145 dd->pport->link_speed_supported = OPA_LINK_SPEED_25G;
15146 /* speeds allowed to run at */
15147 dd->pport->link_speed_enabled = dd->pport->link_speed_supported;
15148 /* give a reasonable active value, will be set on link up */
15149 dd->pport->link_speed_active = OPA_LINK_SPEED_25G;
15151 /* fix up link widths for emulation _p */
15153 if (dd->icode == ICODE_FPGA_EMULATION && is_emulator_p(dd)) {
15154 ppd->link_width_supported =
15155 ppd->link_width_enabled =
15156 ppd->link_width_downgrade_supported =
15157 ppd->link_width_downgrade_enabled =
15160 /* insure num_vls isn't larger than number of sdma engines */
15161 if (HFI1_CAP_IS_KSET(SDMA) && num_vls > sdma_engines) {
15162 dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
15163 num_vls, sdma_engines);
15164 num_vls = sdma_engines;
15165 ppd->vls_supported = sdma_engines;
15166 ppd->vls_operational = ppd->vls_supported;
15170 * Convert the ns parameter to the 64 * cclocks used in the CSR.
15171 * Limit the max if larger than the field holds. If timeout is
15172 * non-zero, then the calculated field will be at least 1.
15174 * Must be after icode is set up - the cclock rate depends
15175 * on knowing the hardware being used.
15177 dd->rcv_intr_timeout_csr = ns_to_cclock(dd, rcv_intr_timeout) / 64;
15178 if (dd->rcv_intr_timeout_csr >
15179 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK)
15180 dd->rcv_intr_timeout_csr =
15181 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK;
15182 else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout)
15183 dd->rcv_intr_timeout_csr = 1;
15185 /* needs to be done before we look for the peer device */
15188 /* set up shared ASIC data with peer device */
15189 ret = init_asic_data(dd);
15193 /* obtain chip sizes, reset chip CSRs */
15194 ret = init_chip(dd);
15198 /* read in the PCIe link speed information */
15199 ret = pcie_speeds(dd);
15203 /* call before get_platform_config(), after init_chip_resources() */
15204 ret = eprom_init(dd);
15206 goto bail_free_rcverr;
15208 /* Needs to be called before hfi1_firmware_init */
15209 get_platform_config(dd);
15211 /* read in firmware */
15212 ret = hfi1_firmware_init(dd);
15217 * In general, the PCIe Gen3 transition must occur after the
15218 * chip has been idled (so it won't initiate any PCIe transactions
15219 * e.g. an interrupt) and before the driver changes any registers
15220 * (the transition will reset the registers).
15222 * In particular, place this call after:
15223 * - init_chip() - the chip will not initiate any PCIe transactions
15224 * - pcie_speeds() - reads the current link speed
15225 * - hfi1_firmware_init() - the needed firmware is ready to be
15228 ret = do_pcie_gen3_transition(dd);
15233 * This should probably occur in hfi1_pcie_init(), but historically
15234 * occurs after the do_pcie_gen3_transition() code.
15236 tune_pcie_caps(dd);
15238 /* start setting dd values and adjusting CSRs */
15239 init_early_variables(dd);
15241 parse_platform_config(dd);
15243 ret = obtain_boardname(dd);
15247 snprintf(dd->boardversion, BOARD_VERS_MAX,
15248 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
15249 HFI1_CHIP_VERS_MAJ, HFI1_CHIP_VERS_MIN,
15252 (dd->revision >> CCE_REVISION_SW_SHIFT)
15253 & CCE_REVISION_SW_MASK);
15255 /* alloc netdev data */
15256 ret = hfi1_netdev_alloc(dd);
15260 ret = set_up_context_variables(dd);
15264 /* set initial RXE CSRs */
15265 ret = init_rxe(dd);
15269 /* set initial TXE CSRs */
15271 /* set initial non-RXE, non-TXE CSRs */
15273 /* set up KDETH QP prefix in both RX and TX CSRs */
15276 ret = hfi1_dev_affinity_init(dd);
15280 /* send contexts must be set up before receive contexts */
15281 ret = init_send_contexts(dd);
15285 ret = hfi1_create_kctxts(dd);
15290 * Initialize aspm, to be done after gen3 transition and setting up
15291 * contexts and before enabling interrupts
15295 ret = init_pervl_scs(dd);
15300 for (i = 0; i < dd->num_pports; ++i) {
15301 ret = sdma_init(dd, i);
15306 /* use contexts created by hfi1_create_kctxts */
15307 ret = set_up_interrupts(dd);
15311 ret = hfi1_comp_vectors_set_up(dd);
15313 goto bail_clear_intr;
15315 /* set up LCB access - must be after set_up_interrupts() */
15316 init_lcb_access(dd);
15319 * Serial number is created from the base guid:
15320 * [27:24] = base guid [38:35]
15321 * [23: 0] = base guid [23: 0]
15323 snprintf(dd->serial, SERIAL_MAX, "0x%08llx\n",
15324 (dd->base_guid & 0xFFFFFF) |
15325 ((dd->base_guid >> 11) & 0xF000000));
15327 dd->oui1 = dd->base_guid >> 56 & 0xFF;
15328 dd->oui2 = dd->base_guid >> 48 & 0xFF;
15329 dd->oui3 = dd->base_guid >> 40 & 0xFF;
15331 ret = load_firmware(dd); /* asymmetric with dispose_firmware() */
15333 goto bail_clear_intr;
15337 ret = init_cntrs(dd);
15339 goto bail_clear_intr;
15341 ret = init_rcverr(dd);
15343 goto bail_free_cntrs;
15345 init_completion(&dd->user_comp);
15347 /* The user refcount starts with one to inidicate an active device */
15348 atomic_set(&dd->user_refcount, 1);
15357 hfi1_comp_vectors_clean_up(dd);
15358 msix_clean_up_interrupts(dd);
15360 hfi1_netdev_free(dd);
15361 hfi1_pcie_ddcleanup(dd);
15363 hfi1_free_devdata(dd);
15368 static u16 delay_cycles(struct hfi1_pportdata *ppd, u32 desired_egress_rate,
15372 u32 current_egress_rate = ppd->current_egress_rate;
15373 /* rates here are in units of 10^6 bits/sec */
15375 if (desired_egress_rate == -1)
15376 return 0; /* shouldn't happen */
15378 if (desired_egress_rate >= current_egress_rate)
15379 return 0; /* we can't help go faster, only slower */
15381 delta_cycles = egress_cycles(dw_len * 4, desired_egress_rate) -
15382 egress_cycles(dw_len * 4, current_egress_rate);
15384 return (u16)delta_cycles;
15388 * create_pbc - build a pbc for transmission
15389 * @flags: special case flags or-ed in built pbc
15390 * @srate: static rate
15392 * @dwlen: dword length (header words + data words + pbc words)
15394 * Create a PBC with the given flags, rate, VL, and length.
15396 * NOTE: The PBC created will not insert any HCRC - all callers but one are
15397 * for verbs, which does not use this PSM feature. The lone other caller
15398 * is for the diagnostic interface which calls this if the user does not
15399 * supply their own PBC.
15401 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
15404 u64 pbc, delay = 0;
15406 if (unlikely(srate_mbs))
15407 delay = delay_cycles(ppd, srate_mbs, dw_len);
15410 | (delay << PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
15411 | ((u64)PBC_IHCRC_NONE << PBC_INSERT_HCRC_SHIFT)
15412 | (vl & PBC_VL_MASK) << PBC_VL_SHIFT
15413 | (dw_len & PBC_LENGTH_DWS_MASK)
15414 << PBC_LENGTH_DWS_SHIFT;
15419 #define SBUS_THERMAL 0x4f
15420 #define SBUS_THERM_MONITOR_MODE 0x1
15422 #define THERM_FAILURE(dev, ret, reason) \
15424 "Thermal sensor initialization failed: %s (%d)\n", \
15428 * Initialize the thermal sensor.
15430 * After initialization, enable polling of thermal sensor through
15431 * SBus interface. In order for this to work, the SBus Master
15432 * firmware has to be loaded due to the fact that the HW polling
15433 * logic uses SBus interrupts, which are not supported with
15434 * default firmware. Otherwise, no data will be returned through
15435 * the ASIC_STS_THERM CSR.
15437 static int thermal_init(struct hfi1_devdata *dd)
15441 if (dd->icode != ICODE_RTL_SILICON ||
15442 check_chip_resource(dd, CR_THERM_INIT, NULL))
15445 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
15447 THERM_FAILURE(dd, ret, "Acquire SBus");
15451 dd_dev_info(dd, "Initializing thermal sensor\n");
15452 /* Disable polling of thermal readings */
15453 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
15455 /* Thermal Sensor Initialization */
15456 /* Step 1: Reset the Thermal SBus Receiver */
15457 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15458 RESET_SBUS_RECEIVER, 0);
15460 THERM_FAILURE(dd, ret, "Bus Reset");
15463 /* Step 2: Set Reset bit in Thermal block */
15464 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15465 WRITE_SBUS_RECEIVER, 0x1);
15467 THERM_FAILURE(dd, ret, "Therm Block Reset");
15470 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
15471 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x1,
15472 WRITE_SBUS_RECEIVER, 0x32);
15474 THERM_FAILURE(dd, ret, "Write Clock Div");
15477 /* Step 4: Select temperature mode */
15478 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x3,
15479 WRITE_SBUS_RECEIVER,
15480 SBUS_THERM_MONITOR_MODE);
15482 THERM_FAILURE(dd, ret, "Write Mode Sel");
15485 /* Step 5: De-assert block reset and start conversion */
15486 ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0,
15487 WRITE_SBUS_RECEIVER, 0x2);
15489 THERM_FAILURE(dd, ret, "Write Reset Deassert");
15492 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
15495 /* Enable polling of thermal readings */
15496 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
15498 /* Set initialized flag */
15499 ret = acquire_chip_resource(dd, CR_THERM_INIT, 0);
15501 THERM_FAILURE(dd, ret, "Unable to set thermal init flag");
15504 release_chip_resource(dd, CR_SBUS);
15508 static void handle_temp_err(struct hfi1_devdata *dd)
15510 struct hfi1_pportdata *ppd = &dd->pport[0];
15512 * Thermal Critical Interrupt
15513 * Put the device into forced freeze mode, take link down to
15514 * offline, and put DC into reset.
15517 "Critical temperature reached! Forcing device into freeze mode!\n");
15518 dd->flags |= HFI1_FORCED_FREEZE;
15519 start_freeze_handling(ppd, FREEZE_SELF | FREEZE_ABORT);
15521 * Shut DC down as much and as quickly as possible.
15523 * Step 1: Take the link down to OFFLINE. This will cause the
15524 * 8051 to put the Serdes in reset. However, we don't want to
15525 * go through the entire link state machine since we want to
15526 * shutdown ASAP. Furthermore, this is not a graceful shutdown
15527 * but rather an attempt to save the chip.
15528 * Code below is almost the same as quiet_serdes() but avoids
15529 * all the extra work and the sleeps.
15531 ppd->driver_link_ready = 0;
15532 ppd->link_enabled = 0;
15533 set_physical_link_state(dd, (OPA_LINKDOWN_REASON_SMA_DISABLED << 8) |
15536 * Step 2: Shutdown LCB and 8051
15537 * After shutdown, do not restore DC_CFG_RESET value.