1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cell Broadband Engine Performance Monitor
5 * (C) Copyright IBM Corporation 2001,2006
8 * David Erb (djerb@us.ibm.com)
9 * Kevin Corry (kevcorry@us.ibm.com)
12 #include <linux/interrupt.h>
13 #include <linux/irqdomain.h>
14 #include <linux/types.h>
15 #include <linux/export.h>
17 #include <asm/irq_regs.h>
18 #include <asm/machdep.h>
22 #include <asm/cell-regs.h>
24 #include "interrupt.h"
27 * When writing to write-only mmio addresses, save a shadow copy. All of the
28 * registers are 32-bit, but stored in the upper-half of a 64-bit field in
32 #define WRITE_WO_MMIO(reg, x) \
35 struct cbe_pmd_regs __iomem *pmd_regs; \
36 struct cbe_pmd_shadow_regs *shadow_regs; \
37 pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
38 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
39 out_be64(&(pmd_regs->reg), (((u64)_x) << 32)); \
40 shadow_regs->reg = _x; \
43 #define READ_SHADOW_REG(val, reg) \
45 struct cbe_pmd_shadow_regs *shadow_regs; \
46 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \
47 (val) = shadow_regs->reg; \
50 #define READ_MMIO_UPPER32(val, reg) \
52 struct cbe_pmd_regs __iomem *pmd_regs; \
53 pmd_regs = cbe_get_cpu_pmd_regs(cpu); \
54 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \
58 * Physical counter registers.
59 * Each physical counter can act as one 32-bit counter or two 16-bit counters.
62 u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr)
64 u32 val_in_latch, val = 0;
66 if (phys_ctr < NR_PHYS_CTRS) {
67 READ_SHADOW_REG(val_in_latch, counter_value_in_latch);
69 /* Read the latch or the actual counter, whichever is newer. */
70 if (val_in_latch & (1 << phys_ctr)) {
71 READ_SHADOW_REG(val, pm_ctr[phys_ctr]);
73 READ_MMIO_UPPER32(val, pm_ctr[phys_ctr]);
79 EXPORT_SYMBOL_GPL(cbe_read_phys_ctr);
81 void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
83 struct cbe_pmd_shadow_regs *shadow_regs;
86 if (phys_ctr < NR_PHYS_CTRS) {
87 /* Writing to a counter only writes to a hardware latch.
88 * The new value is not propagated to the actual counter
89 * until the performance monitor is enabled.
91 WRITE_WO_MMIO(pm_ctr[phys_ctr], val);
93 pm_ctrl = cbe_read_pm(cpu, pm_control);
94 if (pm_ctrl & CBE_PM_ENABLE_PERF_MON) {
95 /* The counters are already active, so we need to
96 * rewrite the pm_control register to "re-enable"
99 cbe_write_pm(cpu, pm_control, pm_ctrl);
101 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
102 shadow_regs->counter_value_in_latch |= (1 << phys_ctr);
106 EXPORT_SYMBOL_GPL(cbe_write_phys_ctr);
109 * "Logical" counter registers.
110 * These will read/write 16-bits or 32-bits depending on the
111 * current size of the counter. Counters 4 - 7 are always 16-bit.
114 u32 cbe_read_ctr(u32 cpu, u32 ctr)
117 u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
119 val = cbe_read_phys_ctr(cpu, phys_ctr);
121 if (cbe_get_ctr_size(cpu, phys_ctr) == 16)
122 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
126 EXPORT_SYMBOL_GPL(cbe_read_ctr);
128 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val)
133 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
135 if (cbe_get_ctr_size(cpu, phys_ctr) == 16) {
136 phys_val = cbe_read_phys_ctr(cpu, phys_ctr);
138 if (ctr < NR_PHYS_CTRS)
139 val = (val << 16) | (phys_val & 0xffff);
141 val = (val & 0xffff) | (phys_val & 0xffff0000);
144 cbe_write_phys_ctr(cpu, phys_ctr, val);
146 EXPORT_SYMBOL_GPL(cbe_write_ctr);
149 * Counter-control registers.
150 * Each "logical" counter has a corresponding control register.
153 u32 cbe_read_pm07_control(u32 cpu, u32 ctr)
155 u32 pm07_control = 0;
158 READ_SHADOW_REG(pm07_control, pm07_control[ctr]);
162 EXPORT_SYMBOL_GPL(cbe_read_pm07_control);
164 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val)
167 WRITE_WO_MMIO(pm07_control[ctr], val);
169 EXPORT_SYMBOL_GPL(cbe_write_pm07_control);
172 * Other PMU control registers. Most of these are write-only.
175 u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg)
181 READ_SHADOW_REG(val, group_control);
184 case debug_bus_control:
185 READ_SHADOW_REG(val, debug_bus_control);
189 READ_MMIO_UPPER32(val, trace_address);
193 READ_SHADOW_REG(val, ext_tr_timer);
197 READ_MMIO_UPPER32(val, pm_status);
201 READ_SHADOW_REG(val, pm_control);
205 READ_MMIO_UPPER32(val, pm_interval);
209 READ_SHADOW_REG(val, pm_start_stop);
215 EXPORT_SYMBOL_GPL(cbe_read_pm);
217 void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
221 WRITE_WO_MMIO(group_control, val);
224 case debug_bus_control:
225 WRITE_WO_MMIO(debug_bus_control, val);
229 WRITE_WO_MMIO(trace_address, val);
233 WRITE_WO_MMIO(ext_tr_timer, val);
237 WRITE_WO_MMIO(pm_status, val);
241 WRITE_WO_MMIO(pm_control, val);
245 WRITE_WO_MMIO(pm_interval, val);
249 WRITE_WO_MMIO(pm_start_stop, val);
253 EXPORT_SYMBOL_GPL(cbe_write_pm);
256 * Get/set the size of a physical counter to either 16 or 32 bits.
259 u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr)
261 u32 pm_ctrl, size = 0;
263 if (phys_ctr < NR_PHYS_CTRS) {
264 pm_ctrl = cbe_read_pm(cpu, pm_control);
265 size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
270 EXPORT_SYMBOL_GPL(cbe_get_ctr_size);
272 void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
276 if (phys_ctr < NR_PHYS_CTRS) {
277 pm_ctrl = cbe_read_pm(cpu, pm_control);
280 pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
284 pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
287 cbe_write_pm(cpu, pm_control, pm_ctrl);
290 EXPORT_SYMBOL_GPL(cbe_set_ctr_size);
293 * Enable/disable the entire performance monitoring unit.
294 * When we enable the PMU, all pending writes to counters get committed.
297 void cbe_enable_pm(u32 cpu)
299 struct cbe_pmd_shadow_regs *shadow_regs;
302 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu);
303 shadow_regs->counter_value_in_latch = 0;
305 pm_ctrl = cbe_read_pm(cpu, pm_control) | CBE_PM_ENABLE_PERF_MON;
306 cbe_write_pm(cpu, pm_control, pm_ctrl);
308 EXPORT_SYMBOL_GPL(cbe_enable_pm);
310 void cbe_disable_pm(u32 cpu)
313 pm_ctrl = cbe_read_pm(cpu, pm_control) & ~CBE_PM_ENABLE_PERF_MON;
314 cbe_write_pm(cpu, pm_control, pm_ctrl);
316 EXPORT_SYMBOL_GPL(cbe_disable_pm);
319 * Reading from the trace_buffer.
320 * The trace buffer is two 64-bit registers. Reading from
321 * the second half automatically increments the trace_address.
324 void cbe_read_trace_buffer(u32 cpu, u64 *buf)
326 struct cbe_pmd_regs __iomem *pmd_regs = cbe_get_cpu_pmd_regs(cpu);
328 *buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
329 *buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
331 EXPORT_SYMBOL_GPL(cbe_read_trace_buffer);
334 * Enabling/disabling interrupts for the entire performance monitoring unit.
337 u32 cbe_get_and_clear_pm_interrupts(u32 cpu)
339 /* Reading pm_status clears the interrupt bits. */
340 return cbe_read_pm(cpu, pm_status);
342 EXPORT_SYMBOL_GPL(cbe_get_and_clear_pm_interrupts);
344 void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
346 /* Set which node and thread will handle the next interrupt. */
347 iic_set_interrupt_routing(cpu, thread, 0);
349 /* Enable the interrupt bits in the pm_status register. */
351 cbe_write_pm(cpu, pm_status, mask);
353 EXPORT_SYMBOL_GPL(cbe_enable_pm_interrupts);
355 void cbe_disable_pm_interrupts(u32 cpu)
357 cbe_get_and_clear_pm_interrupts(cpu);
358 cbe_write_pm(cpu, pm_status, 0);
360 EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);
362 static irqreturn_t cbe_pm_irq(int irq, void *dev_id)
364 perf_irq(get_irq_regs());
368 static int __init cbe_init_pm_irq(void)
373 for_each_online_node(node) {
374 irq = irq_create_mapping(NULL, IIC_IRQ_IOEX_PMI |
375 (node << IIC_IRQ_NODE_SHIFT));
377 printk("ERROR: Unable to allocate irq for node %d\n",
382 rc = request_irq(irq, cbe_pm_irq,
383 0, "cbe-pmu-0", NULL);
385 printk("ERROR: Request for irq on node %d failed\n",
393 machine_arch_initcall(cell, cbe_init_pm_irq);
395 void cbe_sync_irq(int node)
399 irq = irq_find_mapping(NULL,
401 | (node << IIC_IRQ_NODE_SHIFT));
404 printk(KERN_WARNING "ERROR, unable to get existing irq %d " \
405 "for node %d\n", irq, node);
409 synchronize_irq(irq);
411 EXPORT_SYMBOL_GPL(cbe_sync_irq);