1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
5 * Copyright (C) 2023 Cadence.
7 * Author: Pawel Laszczak <pawell@cadence.com>
10 #ifndef __LINUX_CDNS2_GADGET
11 #define __LINUX_CDNS2_GADGET
13 #include <linux/usb/gadget.h>
14 #include <linux/dma-direction.h>
17 * USBHS register interface.
18 * This corresponds to the USBHS Device Controller Interface.
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
23 * @rxbc: receive (OUT) 0 endpoint byte count register.
24 * @txbc: transmit (IN) 0 endpoint byte count register.
25 * @cs: 0 endpoint control and status register.
26 * @reserved1: reserved.
27 * @fifo: 0 endpoint fifo register.
28 * @reserved2: reserved.
29 * @setupdat: SETUP data register.
30 * @reserved4: reserved.
31 * @maxpack: 0 endpoint max packet size.
33 struct cdns2_ep0_regs {
43 } __packed __aligned(4);
45 /* EP0CS - bitmasks. */
46 /* Endpoint 0 stall bit for status stage. */
47 #define EP0CS_STALL BIT(0)
49 #define EP0CS_HSNAK BIT(1)
50 /* IN 0 endpoint busy bit. */
51 #define EP0CS_TXBSY_MSK BIT(2)
52 /* OUT 0 endpoint busy bit. */
53 #define EP0CS_RXBSY_MSK BIT(3)
54 /* Send STALL in the data stage phase. */
55 #define EP0CS_DSTALL BIT(4)
56 /* SETUP buffer content was changed. */
57 #define EP0CS_CHGSET BIT(7)
59 /* EP0FIFO - bitmasks. */
61 #define EP0_FIFO_IO_TX BIT(4)
63 #define EP0_FIFO_AUTO BIT(5)
64 /* FIFO commit bit. */
65 #define EP0_FIFO_COMMIT BIT(6)
66 /* FIFO access bit. */
67 #define EP0_FIFO_ACCES BIT(7)
70 * struct cdns2_epx_base - base endpoint registers.
71 * @rxbc: OUT endpoint byte count register.
72 * @rxcon: OUT endpoint control register.
73 * @rxcs: OUT endpoint control and status register.
74 * @txbc: IN endpoint byte count register.
75 * @txcon: IN endpoint control register.
76 * @txcs: IN endpoint control and status register.
78 struct cdns2_epx_base {
85 } __packed __aligned(4);
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
89 #define EPX_CON_BUF GENMASK(1, 0)
91 #define EPX_CON_TYPE GENMASK(3, 2)
92 /* Endpoint type: isochronous. */
93 #define EPX_CON_TYPE_ISOC 0x4
94 /* Endpoint type: bulk. */
95 #define EPX_CON_TYPE_BULK 0x8
96 /* Endpoint type: interrupt. */
97 #define EPX_CON_TYPE_INT 0xC
98 /* Number of packets per microframe. */
99 #define EPX_CON_ISOD GENMASK(5, 4)
100 #define EPX_CON_ISOD_SHIFT 0x4
101 /* Endpoint stall bit. */
102 #define EPX_CON_STALL BIT(6)
103 /* Endpoint enable bit.*/
104 #define EPX_CON_VAL BIT(7)
106 /* rxcs/txcs - endpoint control and status bitmasks. */
107 /* Data sequence error for the ISO endpoint. */
108 #define EPX_CS_ERR(p) ((p) & BIT(0))
111 * struct cdns2_epx_regs - endpoint 1..15 related registers.
112 * @reserved: reserved.
113 * @ep: none control endpoints array.
114 * @reserved2: reserved.
115 * @endprst: endpoint reset register.
116 * @reserved3: reserved.
117 * @isoautoarm: ISO auto-arm register.
118 * @reserved4: reserved.
119 * @isodctrl: ISO control register.
120 * @reserved5: reserved.
121 * @isoautodump: ISO auto dump enable register.
122 * @reserved6: reserved.
123 * @rxmaxpack: receive (OUT) Max packet size register.
124 * @reserved7: reserved.
125 * @rxstaddr: receive (OUT) start address endpoint buffer register.
126 * @reserved8: reserved.
127 * @txstaddr: transmit (IN) start address endpoint buffer register.
128 * @reserved9: reserved.
129 * @txmaxpack: transmit (IN) Max packet size register.
131 struct cdns2_epx_regs {
133 struct cdns2_epx_base ep[15];
143 __le16 rxmaxpack[15];
144 __le32 reserved7[65];
149 __le16 txmaxpack[15];
150 } __packed __aligned(4);
152 /* ENDPRST - bitmasks. */
153 /* Endpoint number. */
154 #define ENDPRST_EP GENMASK(3, 0)
155 /* IN direction bit. */
156 #define ENDPRST_IO_TX BIT(4)
157 /* Toggle reset bit. */
158 #define ENDPRST_TOGRST BIT(5)
159 /* FIFO reset bit. */
160 #define ENDPRST_FIFORST BIT(6)
161 /* Toggle status and reset bit. */
162 #define ENDPRST_TOGSETQ BIT(7)
165 * struct cdns2_interrupt_regs - USB interrupt related registers.
166 * @reserved: reserved.
167 * @usbirq: USB interrupt request register.
168 * @extirq: external interrupt request register.
169 * @rxpngirq: external interrupt request register.
170 * @reserved1: reserved.
171 * @usbien: USB interrupt enable register.
172 * @extien: external interrupt enable register.
173 * @reserved2: reserved.
174 * @usbivect: USB interrupt vector register.
176 struct cdns2_interrupt_regs {
186 } __packed __aligned(4);
188 /* EXTIRQ and EXTIEN - bitmasks. */
189 /* VBUS fault fall interrupt. */
190 #define EXTIRQ_VBUSFAULT_FALL BIT(0)
191 /* VBUS fault fall interrupt. */
192 #define EXTIRQ_VBUSFAULT_RISE BIT(1)
193 /* Wake up interrupt bit. */
194 #define EXTIRQ_WAKEUP BIT(7)
196 /* USBIEN and USBIRQ - bitmasks. */
197 /* SETUP data valid interrupt bit.*/
198 #define USBIRQ_SUDAV BIT(0)
199 /* Start-of-frame interrupt bit. */
200 #define USBIRQ_SOF BIT(1)
201 /* SETUP token interrupt bit. */
202 #define USBIRQ_SUTOK BIT(2)
203 /* USB suspend interrupt bit. */
204 #define USBIRQ_SUSPEND BIT(3)
205 /* USB reset interrupt bit. */
206 #define USBIRQ_URESET BIT(4)
207 /* USB high-speed mode interrupt bit. */
208 #define USBIRQ_HSPEED BIT(5)
209 /* Link Power Management interrupt bit. */
210 #define USBIRQ_LPM BIT(7)
212 #define USB_IEN_INIT (USBIRQ_SUDAV | USBIRQ_SUSPEND | USBIRQ_URESET \
213 | USBIRQ_HSPEED | USBIRQ_LPM)
215 * struct cdns2_usb_regs - USB controller registers.
216 * @reserved: reserved.
217 * @lpmctrl: LPM control register.
218 * @lpmclock: LPM clock register.
219 * @reserved2: reserved.
220 * @endprst: endpoint reset register.
221 * @usbcs: USB control and status register.
222 * @frmnr: USB frame counter register.
223 * @fnaddr: function Address register.
224 * @clkgate: clock gate register.
225 * @fifoctrl: FIFO control register.
226 * @speedctrl: speed Control register.
227 * @sleep_clkgate: sleep Clock Gate register.
228 * @reserved3: reserved.
229 * @cpuctrl: microprocessor control register.
231 struct cdns2_usb_regs {
246 } __packed __aligned(4);
248 /* LPMCTRL - bitmasks. */
249 /* BESL (Best Effort Service Latency). */
250 #define LPMCTRLLL_HIRD GENMASK(7, 4)
251 /* Last received Remote Wakeup field from LPM Extended Token packet. */
252 #define LPMCTRLLH_BREMOTEWAKEUP BIT(8)
253 /* Reflects value of the lpmnyet bit located in the usbcs[1] register. */
254 #define LPMCTRLLH_LPMNYET BIT(16)
256 /* LPMCLOCK - bitmasks. */
258 * If bit is 1 the controller automatically turns off clock
259 * (utmisleepm goes to low), else the microprocessor should use
260 * sleep clock gate register to turn off clock.
262 #define LPMCLOCK_SLEEP_ENTRY BIT(7)
264 /* USBCS - bitmasks. */
265 /* Send NYET handshake for the LPM transaction. */
266 #define USBCS_LPMNYET BIT(2)
267 /* Remote wake-up bit. */
268 #define USBCS_SIGRSUME BIT(5)
269 /* Software disconnect bit. */
270 #define USBCS_DISCON BIT(6)
271 /* Indicates that a wakeup pin resumed the controller. */
272 #define USBCS_WAKESRC BIT(7)
274 /* FIFOCTRL - bitmasks. */
275 /* Endpoint number. */
276 #define FIFOCTRL_EP GENMASK(3, 0)
278 #define FIFOCTRL_IO_TX BIT(4)
280 #define FIFOCTRL_FIFOAUTO BIT(5)
281 /* FIFO commit bit. */
282 #define FIFOCTRL_FIFOCMIT BIT(6)
283 /* FIFO access bit. */
284 #define FIFOCTRL_FIFOACC BIT(7)
286 /* SPEEDCTRL - bitmasks. */
287 /* Device works in Full Speed. */
288 #define SPEEDCTRL_FS BIT(1)
289 /* Device works in High Speed. */
290 #define SPEEDCTRL_HS BIT(2)
292 #define SPEEDCTRL_HSDISABLE BIT(7)
294 /* CPUCTRL- bitmasks. */
295 /* Controller reset bit. */
296 #define CPUCTRL_SW_RST BIT(1)
299 * struct cdns2_adma_regs - ADMA controller registers.
300 * @conf: DMA global configuration register.
301 * @sts: DMA global Status register.
302 * @reserved1: reserved.
303 * @ep_sel: DMA endpoint select register.
304 * @ep_traddr: DMA endpoint transfer ring address register.
305 * @ep_cfg: DMA endpoint configuration register.
306 * @ep_cmd: DMA endpoint command register.
307 * @ep_sts: DMA endpoint status register.
308 * @reserved2: reserved.
309 * @ep_sts_en: DMA endpoint status enable register.
310 * @drbl: DMA doorbell register.
311 * @ep_ien: DMA endpoint interrupt enable register.
312 * @ep_ists: DMA endpoint interrupt status register.
313 * @axim_ctrl: AXI Master Control register.
314 * @axim_id: AXI Master ID register.
315 * @reserved3: reserved.
316 * @axim_cap: AXI Master Wrapper Extended Capability.
317 * @reserved4: reserved.
318 * @axim_ctrl0: AXI Master Wrapper Extended Capability Control Register 0.
319 * @axim_ctrl1: AXI Master Wrapper Extended Capability Control Register 1.
321 struct cdns2_adma_regs {
344 #define CDNS2_ADMA_REGS_OFFSET 0x400
346 /* DMA_CONF - bitmasks. */
347 /* Reset USB device configuration. */
348 #define DMA_CONF_CFGRST BIT(0)
349 /* Singular DMA transfer mode.*/
350 #define DMA_CONF_DSING BIT(8)
351 /* Multiple DMA transfers mode.*/
352 #define DMA_CONF_DMULT BIT(9)
354 /* DMA_EP_CFG - bitmasks. */
355 /* Endpoint enable. */
356 #define DMA_EP_CFG_ENABLE BIT(0)
358 /* DMA_EP_CMD - bitmasks. */
359 /* Endpoint reset. */
360 #define DMA_EP_CMD_EPRST BIT(0)
361 /* Transfer descriptor ready. */
362 #define DMA_EP_CMD_DRDY BIT(6)
364 #define DMA_EP_CMD_DFLUSH BIT(7)
366 /* DMA_EP_STS - bitmasks. */
367 /* Interrupt On Complete. */
368 #define DMA_EP_STS_IOC BIT(2)
369 /* Interrupt on Short Packet. */
370 #define DMA_EP_STS_ISP BIT(3)
371 /* Transfer descriptor missing. */
372 #define DMA_EP_STS_DESCMIS BIT(4)
374 #define DMA_EP_STS_TRBERR BIT(7)
376 #define DMA_EP_STS_DBUSY BIT(9)
377 /* Current Cycle Status. */
378 #define DMA_EP_STS_CCS(p) ((p) & BIT(11))
379 /* OUT size mismatch. */
380 #define DMA_EP_STS_OUTSMM BIT(14)
381 /* ISO transmission error. */
382 #define DMA_EP_STS_ISOERR BIT(15)
384 /* DMA_EP_STS_EN - bitmasks. */
385 /* OUT transfer missing descriptor enable. */
386 #define DMA_EP_STS_EN_DESCMISEN BIT(4)
388 #define DMA_EP_STS_EN_TRBERREN BIT(7)
389 /* OUT size mismatch enable. */
390 #define DMA_EP_STS_EN_OUTSMMEN BIT(14)
391 /* ISO transmission error enable. */
392 #define DMA_EP_STS_EN_ISOERREN BIT(15)
394 /* DMA_EP_IEN - bitmasks. */
395 #define DMA_EP_IEN(index) (1 << (index))
396 #define DMA_EP_IEN_EP_OUT0 BIT(0)
397 #define DMA_EP_IEN_EP_IN0 BIT(16)
399 /* DMA_EP_ISTS - bitmasks. */
400 #define DMA_EP_ISTS(index) (1 << (index))
401 #define DMA_EP_ISTS_EP_OUT0 BIT(0)
402 #define DMA_EP_ISTS_EP_IN0 BIT(16)
404 #define gadget_to_cdns2_device(g) (container_of(g, struct cdns2_device, gadget))
405 #define ep_to_cdns2_ep(ep) (container_of(ep, struct cdns2_endpoint, endpoint))
407 /*-------------------------------------------------------------------------*/
408 #define TRBS_PER_SEGMENT 600
409 #define ISO_MAX_INTERVAL 8
410 #define MAX_TRB_LENGTH BIT(16)
411 #define MAX_ISO_SIZE 3076
413 * To improve performance the TRB buffer pointers can't cross
416 #define TRB_MAX_ISO_BUFF_SHIFT 12
417 #define TRB_MAX_ISO_BUFF_SIZE BIT(TRB_MAX_ISO_BUFF_SHIFT)
418 /* How much data is left before the 4KB boundary? */
419 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_ISO_BUFF_SIZE - \
420 ((addr) & (TRB_MAX_ISO_BUFF_SIZE - 1)))
422 #if TRBS_PER_SEGMENT < 2
423 #error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
427 * struct cdns2_trb - represent Transfer Descriptor block.
428 * @buffer: pointer to buffer data.
429 * @length: length of data.
430 * @control: control flags.
432 * This structure describes transfer block handled by DMA module.
440 #define TRB_SIZE (sizeof(struct cdns2_trb))
442 * These two extra TRBs are reserved for isochronous transfer
443 * to inject 0 length packet and extra LINK TRB to synchronize the ISO transfer.
445 #define TRB_ISO_RESERVED 2
446 #define TR_SEG_SIZE (TRB_SIZE * (TRBS_PER_SEGMENT + TRB_ISO_RESERVED))
449 #define TRB_TYPE_BITMASK GENMASK(15, 10)
450 #define TRB_TYPE(p) ((p) << 10)
451 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
454 /* Used for Bulk, Interrupt, ISOC, and control data stage. */
456 /* TRB for linking ring segments. */
459 /* Cycle bit - indicates TRB ownership by driver or hw. */
460 #define TRB_CYCLE BIT(0)
462 * When set to '1', the device will toggle its interpretation of the Cycle bit.
464 #define TRB_TOGGLE BIT(1)
465 /* Interrupt on short packet. */
466 #define TRB_ISP BIT(2)
467 /* Chain bit associate this TRB with next one TRB. */
468 #define TRB_CHAIN BIT(4)
469 /* Interrupt on completion. */
470 #define TRB_IOC BIT(5)
472 /* Transfer_len bitmasks. */
473 #define TRB_LEN(p) ((p) & GENMASK(16, 0))
474 #define TRB_BURST(p) (((p) << 24) & GENMASK(31, 24))
475 #define TRB_FIELD_TO_BURST(p) (((p) & GENMASK(31, 24)) >> 24)
477 /* Data buffer pointer bitmasks. */
478 #define TRB_BUFFER(p) ((p) & GENMASK(31, 0))
480 /*-------------------------------------------------------------------------*/
481 /* Driver numeric constants. */
483 /* Maximum address that can be assigned to device. */
484 #define USB_DEVICE_MAX_ADDRESS 127
486 /* One control and 15 IN and 15 OUT endpoints. */
487 #define CDNS2_ENDPOINTS_NUM 31
489 #define CDNS2_EP_ZLP_BUF_SIZE 512
491 /*-------------------------------------------------------------------------*/
492 /* Used structures. */
497 * struct cdns2_ring - transfer ring representation.
498 * @trbs: pointer to transfer ring.
499 * @dma: dma address of transfer ring.
500 * @free_trbs: number of free TRBs in transfer ring.
501 * @pcs: producer cycle state.
502 * @ccs: consumer cycle state.
503 * @enqueue: enqueue index in transfer ring.
504 * @dequeue: dequeue index in transfer ring.
507 struct cdns2_trb *trbs;
517 * struct cdns2_endpoint - extended device side representation of USB endpoint.
518 * @endpoint: usb endpoint.
519 * @pending_list: list of requests queuing on transfer ring.
520 * @deferred_list: list of requests waiting for queuing on transfer ring.
521 * @pdev: device associated with endpoint.
522 * @name: a human readable name e.g. ep1out.
523 * @ring: transfer ring associated with endpoint.
524 * @ep_state: state of endpoint.
525 * @idx: index of endpoint in pdev->eps table.
526 * @dir: endpoint direction.
527 * @num: endpoint number (1 - 15).
528 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK.
529 * @interval: interval between packets used for ISOC and Interrupt endpoint.
530 * @buffering: on-chip buffers assigned to endpoint.
531 * @trb_burst_size: number of burst used in TRB.
532 * @skip: Sometimes the controller cannot process isochronous endpoint ring
533 * quickly enough and it will miss some isoc tds on the ring and
534 * generate ISO transmition error.
535 * Driver sets skip flag when receive a ISO transmition error and
536 * process the missed TDs on the endpoint ring.
538 * @wa1_trb: TRB assigned to WA1.
539 * @wa1_trb_index: TRB index for WA1.
540 * @wa1_cycle_bit: correct cycle bit for WA1.
542 struct cdns2_endpoint {
543 struct usb_ep endpoint;
544 struct list_head pending_list;
545 struct list_head deferred_list;
547 struct cdns2_device *pdev;
550 struct cdns2_ring ring;
552 #define EP_ENABLED BIT(0)
553 #define EP_STALLED BIT(1)
554 #define EP_STALL_PENDING BIT(2)
555 #define EP_WEDGE BIT(3)
556 #define EP_CLAIMED BIT(4)
557 #define EP_RING_FULL BIT(5)
558 #define EP_DEFERRED_DRDY BIT(6)
571 unsigned int wa1_set:1;
572 struct cdns2_trb *wa1_trb;
573 unsigned int wa1_trb_index;
574 unsigned int wa1_cycle_bit:1;
578 * struct cdns2_request - extended device side representation of usb_request
580 * @request: generic usb_request object describing single I/O request.
581 * @pep: extended representation of usb_ep object.
582 * @trb: the first TRB association with this request.
583 * @start_trb: number of the first TRB in transfer ring.
584 * @end_trb: number of the last TRB in transfer ring.
585 * @list: used for queuing request in lists.
586 * @finished_trb: number of trb has already finished per request.
587 * @num_of_trb: how many trbs are associated with request.
589 struct cdns2_request {
590 struct usb_request request;
591 struct cdns2_endpoint *pep;
592 struct cdns2_trb *trb;
595 struct list_head list;
600 #define to_cdns2_request(r) (container_of(r, struct cdns2_request, request))
602 /* Stages used during enumeration process.*/
603 #define CDNS2_SETUP_STAGE 0x0
604 #define CDNS2_DATA_STAGE 0x1
605 #define CDNS2_STATUS_STAGE 0x2
608 * struct cdns2_device - represent USB device.
609 * @dev: pointer to device structure associated whit this controller.
610 * @gadget: device side representation of the peripheral controller.
611 * @gadget_driver: pointer to the gadget driver.
612 * @lock: for synchronizing.
613 * @irq: interrupt line number.
614 * @regs: base address for registers
615 * @usb_regs: base address for common USB registers.
616 * @ep0_regs: base address for endpoint 0 related registers.
617 * @epx_regs: base address for all none control endpoint registers.
618 * @interrupt_regs: base address for interrupt handling related registers.
619 * @adma_regs: base address for ADMA registers.
620 * @eps_dma_pool: endpoint Transfer Ring pool.
621 * @setup: used while processing usb control requests.
622 * @ep0_preq: private request used while handling EP0.
623 * @ep0_stage: ep0 stage during enumeration process.
624 * @zlp_buf: zlp buffer.
625 * @dev_address: device address assigned by host.
626 * @eps: array of objects describing endpoints.
627 * @selected_ep: actually selected endpoint. It's used only to improve
628 * performance by limiting access to dma_ep_sel register.
629 * @is_selfpowered: device is self powered.
630 * @may_wakeup: allows device to remote wakeup the host.
631 * @status_completion_no_call: indicate that driver is waiting for status
632 * stage completion. It's used in deferred SET_CONFIGURATION request.
633 * @in_lpm: indicate the controller is in low power mode.
634 * @pending_status_wq: workqueue handling status stage for deferred requests.
635 * @pending_status_request: request for which status stage was deferred.
636 * @eps_supported: endpoints supported by controller in form:
637 * bit: 0 - ep0, 1 - epOut1, 2 - epIn1, 3 - epOut2 ...
638 * @burst_opt: array with the best burst size value for different TRB size.
639 * @onchip_tx_buf: size of transmit on-chip buffer in KB.
640 * @onchip_rx_buf: size of receive on-chip buffer in KB.
642 struct cdns2_device {
644 struct usb_gadget gadget;
645 struct usb_gadget_driver *gadget_driver;
647 /* generic spin-lock for drivers */
651 struct cdns2_usb_regs __iomem *usb_regs;
652 struct cdns2_ep0_regs __iomem *ep0_regs;
653 struct cdns2_epx_regs __iomem *epx_regs;
654 struct cdns2_interrupt_regs __iomem *interrupt_regs;
655 struct cdns2_adma_regs __iomem *adma_regs;
656 struct dma_pool *eps_dma_pool;
657 struct usb_ctrlrequest setup;
658 struct cdns2_request ep0_preq;
662 struct cdns2_endpoint eps[CDNS2_ENDPOINTS_NUM];
666 bool status_completion_no_call;
668 struct work_struct pending_status_wq;
669 struct usb_request *pending_status_request;
671 u8 burst_opt[MAX_ISO_SIZE + 1];
678 #define CDNS2_IF_EP_EXIST(pdev, ep_num, dir) \
679 ((pdev)->eps_supported & \
680 (BIT(ep_num) << ((dir) ? 0 : 16)))
682 dma_addr_t cdns2_trb_virt_to_dma(struct cdns2_endpoint *pep,
683 struct cdns2_trb *trb);
684 void cdns2_pending_setup_status_handler(struct work_struct *work);
685 void cdns2_select_ep(struct cdns2_device *pdev, u32 ep);
686 struct cdns2_request *cdns2_next_preq(struct list_head *list);
687 struct usb_request *cdns2_gadget_ep_alloc_request(struct usb_ep *ep,
689 void cdns2_gadget_ep_free_request(struct usb_ep *ep,
690 struct usb_request *request);
691 int cdns2_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
692 void cdns2_gadget_giveback(struct cdns2_endpoint *pep,
693 struct cdns2_request *priv_req,
695 void cdns2_init_ep0(struct cdns2_device *pdev, struct cdns2_endpoint *pep);
696 void cdns2_ep0_config(struct cdns2_device *pdev);
697 void cdns2_handle_ep0_interrupt(struct cdns2_device *pdev, int dir);
698 void cdns2_handle_setup_packet(struct cdns2_device *pdev);
699 int cdns2_gadget_resume(struct cdns2_device *pdev, bool hibernated);
700 int cdns2_gadget_suspend(struct cdns2_device *pdev);
701 void cdns2_gadget_remove(struct cdns2_device *pdev);
702 int cdns2_gadget_init(struct cdns2_device *pdev);
703 void set_reg_bit_8(void __iomem *ptr, u8 mask);
704 int cdns2_halt_endpoint(struct cdns2_device *pdev, struct cdns2_endpoint *pep,
707 #endif /* __LINUX_CDNS2_GADGET */